CN1326210C - 具有到衬底的互连的集成电路及其方法 - Google Patents

具有到衬底的互连的集成电路及其方法 Download PDF

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Publication number
CN1326210C
CN1326210C CNB028231287A CN02823128A CN1326210C CN 1326210 C CN1326210 C CN 1326210C CN B028231287 A CNB028231287 A CN B028231287A CN 02823128 A CN02823128 A CN 02823128A CN 1326210 C CN1326210 C CN 1326210C
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CN
China
Prior art keywords
gate dielectric
grid
gate
substrate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028231287A
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English (en)
Chinese (zh)
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CN1592951A (zh
Inventor
道格拉斯·M·雷伯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1592951A publication Critical patent/CN1592951A/zh
Application granted granted Critical
Publication of CN1326210C publication Critical patent/CN1326210C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
CNB028231287A 2001-10-22 2002-09-27 具有到衬底的互连的集成电路及其方法 Expired - Fee Related CN1326210C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/986,232 2001-10-22
US09/986,232 US6555915B1 (en) 2001-10-22 2001-10-22 Integrated circuit having interconnect to a substrate and method therefor

Publications (2)

Publication Number Publication Date
CN1592951A CN1592951A (zh) 2005-03-09
CN1326210C true CN1326210C (zh) 2007-07-11

Family

ID=25532216

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028231287A Expired - Fee Related CN1326210C (zh) 2001-10-22 2002-09-27 具有到衬底的互连的集成电路及其方法

Country Status (7)

Country Link
US (1) US6555915B1 (https=)
EP (1) EP1479101A2 (https=)
JP (1) JP2006500759A (https=)
KR (1) KR20040048985A (https=)
CN (1) CN1326210C (https=)
AU (1) AU2002327714A1 (https=)
WO (1) WO2003036702A2 (https=)

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* Cited by examiner, † Cited by third party
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JP2003031801A (ja) * 2001-07-16 2003-01-31 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US7654221B2 (en) * 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7297605B2 (en) * 2004-05-10 2007-11-20 Texas Instruments Incorporated Source/drain extension implant process for use with short time anneals
DE102004038369B4 (de) * 2004-08-06 2018-04-05 Austriamicrosystems Ag Hochvolt-NMOS-Transistor und Herstellungsverfahren
US7150516B2 (en) * 2004-09-28 2006-12-19 Hewlett-Packard Development Company, L.P. Integrated circuit and method for manufacturing
KR100657142B1 (ko) * 2005-06-03 2006-12-13 매그나칩 반도체 유한회사 이미지센서의 픽셀 쉬링크를 위한 콘택 구조 및 그 제조방법
JP6374718B2 (ja) * 2014-07-14 2018-08-15 矢崎総業株式会社 電気素子
JP6268070B2 (ja) * 2014-09-16 2018-01-24 矢崎総業株式会社 メッキ材及び端子金具
WO2016010053A1 (ja) * 2014-07-14 2016-01-21 矢崎総業株式会社 電気素子
JP6268055B2 (ja) * 2014-07-15 2018-01-24 矢崎総業株式会社 端子及びコネクタ
JP6272744B2 (ja) * 2014-10-24 2018-01-31 矢崎総業株式会社 板状導電体及び板状導電体の表面処理方法
US10038081B1 (en) 2017-09-06 2018-07-31 Nxp Usa, Inc. Substrate contacts for a transistor
US10679987B2 (en) * 2017-10-31 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0342778A1 (en) * 1988-03-24 1989-11-23 Nortel Networks Corporation Ion implanted semiconductor device
US5087589A (en) * 1987-06-12 1992-02-11 Massachusetts Institute Of Technology Selectively programmable interconnections in multilayer integrated circuits
JP2000031296A (ja) * 1998-06-30 2000-01-28 Motorola Inc Ｃｍｏｓ半導体素子およびその形成方法
US6262486B1 (en) * 1997-04-01 2001-07-17 Micron Technology, Inc. Conductive implant structure in a dielectric

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03101255A (ja) * 1989-09-14 1991-04-26 Sony Corp 半導体装置
JPH04162519A (ja) * 1990-10-24 1992-06-08 Sony Corp Ｍｏｓ型半導体装置の製造方法
US5783469A (en) * 1996-12-10 1998-07-21 Advanced Micro Devices, Inc. Method for making nitrogenated gate structure for improved transistor performance
US6074904A (en) * 1998-04-21 2000-06-13 Advanced Micro Devices, Inc. Method and structure for isolating semiconductor devices after transistor formation
US6077748A (en) * 1998-10-19 2000-06-20 Advanced Micro Devices, Inc. Advanced trench isolation fabrication scheme for precision polysilicon gate control
KR100281908B1 (ko) * 1998-11-20 2001-02-15 김덕중 반도체소자 및 그 제조방법
JP3723410B2 (ja) * 2000-04-13 2005-12-07 三洋電機株式会社 半導体装置とその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087589A (en) * 1987-06-12 1992-02-11 Massachusetts Institute Of Technology Selectively programmable interconnections in multilayer integrated circuits
EP0342778A1 (en) * 1988-03-24 1989-11-23 Nortel Networks Corporation Ion implanted semiconductor device
US6262486B1 (en) * 1997-04-01 2001-07-17 Micron Technology, Inc. Conductive implant structure in a dielectric
JP2000031296A (ja) * 1998-06-30 2000-01-28 Motorola Inc Ｃｍｏｓ半導体素子およびその形成方法

Also Published As

Publication number Publication date
JP2006500759A (ja) 2006-01-05
CN1592951A (zh) 2005-03-09
US20030075806A1 (en) 2003-04-24
WO2003036702A2 (en) 2003-05-01
EP1479101A2 (en) 2004-11-24
AU2002327714A1 (en) 2003-05-06
US6555915B1 (en) 2003-04-29
WO2003036702A3 (en) 2003-11-06
KR20040048985A (ko) 2004-06-10

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SE01 Entry into force of request for substantive examination
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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070711

Termination date: 20110927