CN1324654C - 金属栅极形成方法 - Google Patents

金属栅极形成方法 Download PDF

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CN1324654C
CN1324654C CNB011393157A CN01139315A CN1324654C CN 1324654 C CN1324654 C CN 1324654C CN B011393157 A CNB011393157 A CN B011393157A CN 01139315 A CN01139315 A CN 01139315A CN 1324654 C CN1324654 C CN 1324654C
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张世亿
宣俊协
崔亨福
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SK Hynix Inc
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Abstract

本发明涉及形成可容易地去除伪多晶硅膜的例如集成MOS晶体管中的镶嵌金属栅极的方法。该方法包括以下步骤:形成镶嵌栅极绝缘膜32和伪栅极用多晶硅膜33的工序,在包含上述伪多晶硅膜33的晶片31上形成夹层绝缘膜36的工序,抛光夹层绝缘膜以露出上述伪多晶硅膜的工序,利用旋转蚀刻方法对上述露出的伪多晶硅膜进行湿蚀刻的工序。

Description

金属栅极形成方法
                        技术领域
本发明涉及适用于高集成半导体器件中的金属栅极的制造方法,具体地说,是涉及形成可容易地去除伪多晶硅膜的高集成MOS晶体管的镶嵌栅极的方法。
                        背景技术
以前,在这种半导体器件中,使用多晶硅栅极和多硅酸盐(ポリサイド)栅极等作为栅极,多晶硅栅极存在以下问题:因栅极损耗现象引起的栅极绝缘膜的有效厚度增加,因搀杂物从p+或n+多晶硅栅极渗透到衬底的现象和搀杂物分布变化引起的阈值电压的变化等。
利用现有的多晶硅的栅极还存在所谓的在宽度很细小的线上无法实现低电阻值的问题。
因此,需要开发可代替利用现有的多晶硅的栅极的新物质和新结构的栅极。
对应于该要求进行了积极的金属栅极的开发,通过在制造金属栅极时不使用搀杂物,不仅解决了因现有的多晶硅栅极产生的问题,而且,作为金属栅极,通过使功函数位于硅的中间能带隙的金属,可形成在NMOS晶体管和PMOS晶体管区域中对称地形成阈电压的单一栅极。此时,在金属栅极的物质中可使用W、WN、Ti、TiN、Mo和Ta等。
在通常利用多晶硅栅极的半导体器件的制造方法来制造利用金属栅极的半导体器件时,会产生以下严重的问题:金属栅极难以形成图形,在源极/漏极的离子注入时等离子体产生损伤,以及离子注入后,因热处理工序而产生热损伤。
为了解决上述伴随着金属栅极的使用而产生的工序上的问题,而提出形成金属栅极的新的工序,即镶嵌金属栅极的制造工序。该镶嵌金属栅极的制造工序如下:在将多晶硅栅极形成为伪栅极时形成源极/漏极区域,以制造半导体器件,在去除形成于所述伪栅极中的多晶硅栅极时,在镶嵌工序中形成金属栅极。
参照图1至图6来说明现有的镶嵌金属栅极的制造工序。
如图1所示,在晶片10、即由硅衬底构成的半导体衬底上形成通常的多晶硅栅极的方法中,在形成硅氧化膜和多晶硅膜后,以制成图形的方式形成伪栅极绝缘膜11和伪栅极12。
接着,在进行通常的离子注入工序后形成源极/漏极区域13时,在伪栅极绝缘膜11和伪栅极12的侧壁上形成衬垫14。此时,源极/漏极区域13也可形成为LDD(Lightly Doped Drain)结构,首先,形成伪栅极12,之后形成低浓度的源极/漏极区域13,在形成侧壁衬垫14后,形成高浓度的源极/漏极区域。
如图2所示,在半导体衬底10的整个表面上形成夹层绝缘膜15时,如图3所示,进行CMP(chemical mechanical polishing)工序,抛光夹层绝缘膜15,以便露出伪栅极12。
如图4所示,以选择蚀刻方法来去除露出的伪栅极12和其下部的露出的伪栅极绝缘膜11,从而露出半导体衬底10。由此,在去除伪栅极12和伪栅极绝缘膜11的部位上形成沟槽16。
如图5所示,在包括沟槽16的夹层绝缘膜15上形成薄膜绝缘膜17和钨等金属膜18时,进行CMP工序,露出夹层绝缘膜15。因此,如图6所示,形成镶嵌栅极绝缘膜19和镶嵌金属栅极20。
因为上述形成现有的镶嵌金属栅极20的方法在晶体管的源极/漏极的形成工序后形成镶嵌金属栅极20,所以解决了以前的金属栅极难以形成图形、在源极/漏极用的离子注入时等离子体产生损伤、以及离子注入后因热处理工序而产生热损伤等的问题。
在形成这种镶嵌金属栅极时,其中最重要的一个工序是如图1至图4所述的选择去除作为伪栅极12的物质的多晶硅膜的工序。该工序防止了去除伪栅极用多晶硅膜时由氮化膜构成的侧壁衬垫14和由CVD氧化膜构成的夹层绝缘膜15的损伤,特别是必须防止晶片、即硅衬底10的损伤。多晶硅膜的残留物(residue)不会残留在沟槽16内。
图7(A)、(B)表示现有的去除用于伪栅极中的伪多晶硅膜的方法。
图7(A)表示现有的通过干蚀刻工序去除伪多晶硅膜的工序,图7(B)表示现有的通过湿蚀刻工序去除伪多晶硅膜的工序。
图7(A)所示的干蚀刻工序利用等离子体P深腐蚀去除伪多晶硅膜,图7(B)所示的湿蚀刻工序是在湿电解槽21的湿蚀刻溶液(wet chemical)23中通过上述方法将形成伪多晶硅膜的晶片22浸渍规定时间以去除伪多晶硅膜的静(static)蚀刻方法。
但是,上述现有的去除伪多晶硅膜的工序存在如下问题。
首先,现有的利用等离子体的深蚀刻工序问题在于:在通过等离子体蚀刻伪多晶硅膜而形成图4所示的沟槽16时,会诱发等离子体对晶片、即硅衬底10的损伤,和需要进行后处理工序以除去在干式深蚀刻工序时产生的大量聚合体。
另一方面,上述的利用湿蚀刻方法的湿蚀刻的去除伪多晶硅膜的工序可防止因干蚀刻时等离子体引起的半导体衬底的损伤,在作为各向异性蚀刻方面比干蚀刻方法好。不过,湿蚀刻方法的优点在于蚀刻多晶硅膜时明显比蚀刻其它薄膜快。
                           发明内容
为了解决上述现有技术的问题,本发明的目的在于提供一种利用旋转蚀刻方法可快速地蚀刻伪多晶硅膜的形成伪金属栅极的方法。
为了达到上述本发明的目的,本发明提供一种镶嵌金属栅极的方法,包括以下步骤:在晶片上形成伪栅绝缘膜和伪栅极用多晶硅膜的工序;在包含上述伪多晶硅膜的晶片上形成夹层绝缘膜的工序,抛光夹层绝缘膜,以便露出上述伪多晶硅膜的工序,利用旋转蚀刻方法,对上述露出的伪多晶硅膜进行湿蚀刻的工序,其中,该蚀刻溶液包括HF和HNO3,HF∶HNO3约为1∶10至1∶50。
根据本发明实施例的镶嵌金属栅极的形成方法,在所述湿蚀刻工序中,在旋转晶片的状态下,向伪多晶硅膜的表面上喷射湿蚀刻溶液,旋转蚀刻上述伪多晶硅膜。
此时,上述晶片的旋转速度为500至2000rpm,上述湿蚀刻溶液使用HF和HNO3的混合溶液,上述湿蚀刻溶液的温度为20至100℃。
                        附图说明
图1是通常的形成镶嵌金属栅极的制造工序图。
图2是通常的形成镶嵌金属栅极的制造工序图。
图3是通常的形成镶嵌金属栅极的制造工序图。
图4是通常的形成镶嵌金属栅极的制造工序图。
图5是通常的形成镶嵌金属栅极的制造工序图。
图6是通常的形成镶嵌金属栅极的制造工序图。
图7(A)、(B)是说明在现有的形成镶嵌金属栅极的工序中去除伪多晶硅膜的方法的图。
图8是说明本发明的形成镶嵌金属栅极的原理的图。
图9是根据本发明的一个实施例形成镶嵌金属栅极的制造工序图。
图10是根据本发明的一个实施例形成镶嵌金属栅极的制造工序图。
图11是根据本发明的一个实施例形成镶嵌金属栅极的制造工序图。
图12是说明在本发明的形成镶嵌金属栅极的工序中去除伪多晶硅膜的方法的图。
图13(A)、(B)是在本发明的形成镶嵌金属栅极的工序中去除伪多晶硅膜后的电子显微镜照片。
                      具体实施方式
图8是说明利用根据本发明的实施例的旋转蚀刻方法去除伪多晶硅膜的方法的图。图9至图11是表示利用根据本发明的实施例的旋转蚀刻方法形成镶嵌金属栅极的工序图。
参照图8,利用本发明的旋转蚀刻方法去除伪多晶硅膜的方法是作为如下的动态(dynamic)湿蚀刻方法的旋转蚀刻方法(spin etching):在向箭头a方向旋转在其上部形成伪多晶硅膜的晶片31的同时,利用蚀刻溶液喷射装置40向上述晶片31喷射湿蚀刻溶液b,去除伪多晶硅膜。
参照图9至图11来说明根据本发明一个实施例的镶嵌金属栅极的形成方法。
首先,在晶片、即由硅构成的半导体衬底31上形成伪栅极氧化膜32和伪栅极用伪多晶硅膜33后,形成侧壁衬垫34和源极/漏极区域35,在硅衬底31的整个表面形成夹层绝缘膜36。此时,可用通常的方法将源极/漏极区域35形成为LDD结构。
如图10所示,通过CMP工序将夹层绝缘膜36蚀刻到露出伪多晶硅膜33。
如图11所示,边旋转形成使用图8的旋转蚀刻方法露出的伪多晶硅膜的半导体衬底31,边喷射湿蚀刻溶液,快速去除伪多晶硅膜33。
之后,虽然未图示,但在去除伪多晶硅膜33后,形成镶嵌栅极绝缘膜和镶嵌金属栅极。
参照图12来具体说明利用本发明的旋转蚀刻方法去除伪多晶硅膜的方法。
图12是说明在旋转的半导体衬底31中的湿蚀刻溶液b的流动的图。图12中的箭头c的方向和长度分别表示蚀刻溶液b的流动方向和流速。与图7(B)所示的现有湿蚀刻方法不同之处在于,向半导体衬底31的表面、即伪多晶硅膜33的表面喷射湿蚀刻溶液,蚀刻该伪多晶硅膜33。此时,由蚀刻溶液b的流速来决定伪多晶硅膜33的蚀刻速度,蚀刻溶液b的流速增大到半导体衬底31的旋转速度rpm(rotation per min)左右。
首先,假设半导体衬底31的旋转速度非常快。在以数千rpm高速旋转的衬底31内,流体以随着旋转角速度和向心角速度的非常快的速度移动,边去除伪多晶硅膜边在形成的沟槽37内如下动作。
以数千以上高旋转的湿蚀刻溶液b非常快地在衬底31的边缘移动。在高旋转情况下,大部分蚀刻溶液b不流入镶嵌沟槽37,而是越过该沟槽37的上方,仅有一部分液体流入沟槽37内。
因为流入沟槽37内的蚀刻溶液b流速快,所以产生涡流(eddy flow),不能到达沟槽37的外部。因此,新鲜的溶液b不能供给到引导的沟槽37内,所以不能去除沟槽37内的多晶硅膜33。
接着,假设以较低的速度旋转衬底31。在上述衬底31以低速放置的状态下喷射湿蚀刻溶液b,将如图7(B)所示,可以比将衬底31浸渍在电解槽21内的湿蚀刻溶液23中去除伪多晶硅膜的方法更有效地去除沟槽37内的伪多晶硅膜33。即,当以较低的速度旋转衬底31时,与高速旋转衬底31的情况不同,大部分的蚀刻溶液b流入沟槽37内,在沟槽37内部产生的涡流减少,可持续地向沟槽37的内部提供新鲜的湿蚀刻溶液b。因此,提供给沟槽37内部的溶液b由于衬底31的旋转而受到机械力(Mechanical force),进一步提高了多晶硅膜33的蚀刻速度。
下述表1表示利用本发明的旋转蚀刻方法和现有的湿蚀刻方法去除伪多晶硅膜时的条件。
                                     表1
  现有的湿蚀刻方法的一个例子   本发明的旋转蚀刻方法的一个例子
  实验条件   NH4OH∶H2O=1∶2-1∶20温度:86℃浸渍在湿电解槽中   HF∶HNO3=1∶20温度:20-100℃晶片的旋转速度:500-2000rpm蚀刻溶液喷射流量:0.3-1.31pm
  各种薄膜的蚀刻速度(/min)   多晶硅:90热氧化膜(SiO2):0.2CVD氧化膜(HDP SiO2):0.3-1氮化膜(Si3N4):0.3-1   多晶硅:12,000热氧化膜(SiO2):540CVD氧化膜(HDP SiO2):700氮化膜(Si3N4):60
  对于多晶硅膜的蚀刻选择比   热氧化膜(SiO2)450∶1CVD氧化膜(HDP SiO2)90-300∶1氮化膜(Si3N4)90-300∶1   热氧化膜(SiO2)22∶1CVD氧化膜(HDP SiO2)17∶1氮化膜(Si3N4)200∶1
从上述表1可知,在装有现有的多晶硅膜蚀刻时通常使用的NH4OH+H2O溶液的湿蚀刻溶液的湿电解槽23中,在86℃下多晶硅膜的蚀刻速度约为90/min。但是,本发明的旋转蚀刻方法以0.81pm(liter per min)的流量来喷射作为蚀刻溶液的HF∶HNO3的比例为1∶20的溶液,以1400rpm旋转衬底31时,即使是室温23℃,多晶硅膜33的蚀刻速度为12000/min,可尽快地进行蚀刻。
图13(A)、(B)是在上述表1所示实验条件下在10秒钟内旋转蚀刻本发明沟槽37内的多晶硅膜33时拍摄的照片。同图的照片是去除图12的伪多晶硅膜33后的电子显微镜照片。此时,图13(A)是表示存储器单元区域的窄沟槽37的照片,图13(B)是表示周边电路部的宽沟槽37的照片。
参照图13(A)、(B),可知可很好地去除沟槽37内的多晶硅膜33,在宽的沟槽37和窄的沟槽内可同时很好地去除多晶硅膜33。
从上述表1可知,虽然本发明的旋转蚀刻情况与现有技术相比,对于氧化膜和氮化膜的蚀刻选择比差,但参照图13(A)、(B),显示衬底31内没有任何损伤。因此,可知本发明的旋转蚀刻方法对于多晶硅膜与氧化膜和氮化膜的蚀刻选择比不成问题。
虽然可设想由于晶片、即半导体衬底31的旋转引起图形损坏,但参照图13(A)、(B)可知,本发明的旋转蚀刻方法的伪多晶硅膜去除时,不会产生伴随晶片旋转的图形损坏现象。
根据本发明实施例的旋转蚀刻时的工序条件可知,当在晶片的旋转速度为500-2000rpm、HF∶HNO3的混合比例为1∶10-1∶50、化合物喷射流量为0.3-2.0pm、化合物温度在20-100℃范围内时,可最有效地去除沟槽37内的伪多晶硅膜33。
上述本发明的去除镶嵌栅极形成用伪多晶硅膜的方法,通过边旋转晶片边使用喷射湿蚀刻溶液的旋转蚀刻方法,与现有的湿蚀刻方法相比,具有可以快100倍以上地去除伪多晶硅膜的效果。
另外,本发明在不脱离其精神的范围内可进行各种各样的变更。

Claims (4)

1.一种形成镶嵌金属栅极的方法,包括以下步骤:
在一晶片上形成用于伪栅极的一伪栅极绝缘膜和一多晶硅膜;
在该晶片上形成一夹层绝缘膜;
抛光该夹层绝缘膜,以便露出该伪多晶硅膜的上表面;和
应用旋转蚀刻工序,对露出的伪多晶硅膜进行湿蚀刻,
其中,该蚀刻溶液包括HF和HNO3,HF∶HNO3为1∶10至1∶50。
2.根据权利要求1所述的形成镶嵌金属栅极的方法,其特征在于:
湿蚀刻伪多晶硅膜的步骤包括在旋转晶片的同时将一蚀刻溶液供给到该晶片的上表面的步骤。
3.根据权利要求2所述的形成镶嵌金属栅极的方法,其特征在于:
以500至2000rpm的速度旋转该晶片。
4.根据权利要求1所述的形成镶嵌金属栅极的方法,其特征在于:
该蚀刻溶液的温度为20至100℃。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040060565A (ko) * 2002-12-30 2004-07-06 동부전자 주식회사 반도체 소자의 더미 게이트 및 도핑을 이용한 이중 게이트산화막 제조방법
US7071086B2 (en) * 2003-04-23 2006-07-04 Advanced Micro Devices, Inc. Method of forming a metal gate structure with tuning of work function by silicon incorporation
US6891229B2 (en) * 2003-04-30 2005-05-10 Freescale Semiconductor, Inc. Inverted isolation formed with spacers
US7199021B2 (en) * 2004-06-22 2007-04-03 Texas Instruments Incorporated Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
KR100641933B1 (ko) 2004-10-06 2006-11-02 주식회사 하이닉스반도체 반도체 소자의 형성 방법
US20060095327A1 (en) * 2004-11-01 2006-05-04 Vaughn Charles A System and method for identifying customer offers
US7479684B2 (en) * 2004-11-02 2009-01-20 International Business Machines Corporation Field effect transistor including damascene gate with an internal spacer structure
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
DE102006013721B4 (de) * 2006-03-24 2011-12-08 Infineon Technologies Ag Halbleiterschaltungsanordnung und zugehöriges Verfahren zur Temperaturerfassung
US20080104917A1 (en) * 2006-11-02 2008-05-08 Whelan Brian J Self-adhering waterproofing membrane
KR20090038972A (ko) * 2007-10-17 2009-04-22 삼성전자주식회사 콘택홀 형성방법 및 그를 이용한 반도체 메모리소자의제조방법
US8415254B2 (en) * 2008-11-20 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for removing dummy poly in a gate last process
US8268085B2 (en) * 2009-03-20 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming metal gate transistors
CN101930913B (zh) * 2009-06-26 2012-05-23 中芯国际集成电路制造(上海)有限公司 金属栅电极形成方法
CN102087980A (zh) * 2009-12-04 2011-06-08 中国科学院微电子研究所 高性能半导体器件及其形成方法
CN102543739A (zh) * 2010-12-22 2012-07-04 中芯国际集成电路制造(上海)有限公司 制作半导体器件的方法
CN102779754B (zh) * 2011-05-12 2015-04-08 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN102810491B (zh) * 2011-06-03 2015-12-09 中国科学院微电子研究所 后栅工艺移除多晶硅假栅制程的监控方法
CN103107074B (zh) * 2011-11-11 2015-09-02 中芯国际集成电路制造(上海)有限公司 一种金属栅极的形成方法
CN103531453B (zh) 2012-07-02 2016-12-21 中芯国际集成电路制造(上海)有限公司 半导体集成器件及其制作方法
CN103730422B (zh) * 2012-10-16 2017-09-26 中国科学院微电子研究所 半导体器件制造方法
CN103794482B (zh) * 2012-10-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 金属栅极的形成方法
CN103928331B (zh) * 2013-01-11 2016-08-10 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN103928402B (zh) 2013-01-11 2016-09-07 中芯国际集成电路制造(上海)有限公司 共用栅极的半导体结构及对应的形成方法
US9130059B2 (en) * 2013-01-18 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device having a capping layer
CN104241131B (zh) * 2013-06-09 2017-08-25 中芯国际集成电路制造(上海)有限公司 金属栅极晶体管的形成方法
KR102178827B1 (ko) * 2014-02-13 2020-11-13 삼성전자 주식회사 Mosfet, 그 제조 방법, 및 mosfet을 구비한 반도체 장치
CN105225950B (zh) * 2014-05-29 2018-03-30 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管的形成方法、mos晶体管的形成方法
KR102295029B1 (ko) * 2015-03-31 2021-08-27 삼성전자주식회사 반도체 소자의 제조방법
US9960161B2 (en) 2016-01-12 2018-05-01 International Business Machines Corporation Low resistive electrode for an extendable high-k metal gate stack
DE102020125324A1 (de) 2020-02-26 2021-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Teilweise gerichtetes Ätzverfahren und die daraus resultierenden Strukturen
US11374110B2 (en) * 2020-02-26 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Partial directional etch method and resulting structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942449A (en) * 1996-08-28 1999-08-24 Micron Technology, Inc. Method for removing an upper layer of material from a semiconductor wafer
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869866A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
JPH11135745A (ja) * 1997-10-29 1999-05-21 Toshiba Corp 半導体装置及びその製造方法
KR100271769B1 (ko) * 1998-06-25 2001-02-01 윤종용 반도체소자의 제조방법, 이를 위한 반도체소자 제조용 식각액조성물 및 반도체소자
JP3025478B2 (ja) * 1998-07-13 2000-03-27 松下電器産業株式会社 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942449A (en) * 1996-08-28 1999-08-24 Micron Technology, Inc. Method for removing an upper layer of material from a semiconductor wafer
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

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