CN1321340A - 具有漏极延伸区的横向薄膜硅绝缘体(soi)pmos器件 - Google Patents

具有漏极延伸区的横向薄膜硅绝缘体(soi)pmos器件 Download PDF

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CN1321340A
CN1321340A CN00801827A CN00801827A CN1321340A CN 1321340 A CN1321340 A CN 1321340A CN 00801827 A CN00801827 A CN 00801827A CN 00801827 A CN00801827 A CN 00801827A CN 1321340 A CN1321340 A CN 1321340A
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T·莱塔维克
M·辛普森
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Koninklijke Philips NV
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

Abstract

一种横向薄膜硅绝缘体(SOI)PMOS器件,包含半导体基片、在所述基片上的埋入绝缘层以及在所述埋入绝缘层上的SOI层中的横向PMOS晶体管器件,该晶体管器件具有:形成在n型导电的体区域中的p型导电源区域;邻近所述体区域的n型导电的横向漂移区;p型导电并且通过所述横向漂移区在横向上与所述体区域隔开的的漏极区域;以及在一部分所述体区域上方的门电极,其中沟道区在工作期间形成并且在靠近所述体区域的所述横向漂移区的一部分的上方延伸,所述门电极通过绝缘区域与所述体区域和漂移区绝缘。为了简单地经济地制造PMOS晶体管器件,所述横向漂移区在至少其横向范围的大部分上方设有线性分级电荷分布,并且表面邻接p型导电漏极延伸区域设在所述漂移区中并且从所述漏极区域延伸到源区域附近,但是没有直接与所述源区域接触。

Description

具有漏极延伸区的横向 薄膜硅绝缘体(SOI)PMOS器件
本发明所属的技术领域是半导体绝缘体(SOI)器件，具体涉及适用于高电压用途的横向SOI PMOS器件。在制造高电压功率器件中，通常必须在例如击穿电压、尺寸、“接通”电阻和制造简易性和可靠性方面上取得折衷和平衡。改进一个参数例如击穿电压常常会导致其他参数例如“接通”电阻的降低。理想上，这种器件最好在所有方面都具有优良的特性，且其工作和制造缺陷最小。
横向薄膜SOI器件的一个特别优选的形式包括：半导体基片，在半导体基片上的埋入绝缘层以及在埋入绝缘层上的半导体表面层中的横向晶体管器件，该晶体管器件例如MOSFET包括在埋入绝缘层上的半导体表面层，并且具有：形成在对着第一导电型体区域的第二导电型体区域中的第一导电型源区域；在体区域的沟道区上方且与之绝缘的绝缘门电极；第一导电型横向漂移区；以及通过漂移区与沟道区横向隔开的第一导电型漏极区域。
在图1中显示出这种类型的器件，该图为与本申请共同转让的并在这里被引用作为参考的相关的美国专利Nos.5246870(涉及方法)和5412241(涉及器件)所共有。上述专利的在图1中所示的器件是一种具有多方面特性的横向SOIPMOS器件，例如一种具有线性横向掺杂区和覆盖在上面的场电极的压缩的SOI层，以提高运行。一般来说，该器件是一种n沟道或NMOS晶体管，具有n型源区域和漏区域，它是采用一种被称作NMOS技术制成的。
虽然在薄膜SOI器件方面的趋势朝着具有压缩的SOI层的方向发展，但是对于未压缩的器件如在美国专利No.5300448中所示的器件而言具有某些优点，如简易性，易于制造和更低的结构成本，该专利是和本申请一起被共同转让的并且在这里被引用作为参考。
虽然上述类型的器件通常是采用如上所述的NMOS技术制成的n沟道器件，但是最好能实现采用标准技术的p沟道或PMOS高电压晶体管。在美国专利No.5710451中显示出实现这个的一种方法，该专利同样是和本申请一起被共同转让的并在这里被引用作为参考。然而，在该参考文献中所示的结构需要半导体联接区域，因此制造更复杂且昂贵，并且只在特定的工作模式中才能被用作PMOS晶体管。
因此，很显然为了提高功率半导体器件的性能，已经采用了许多技术和方法，并且一直在努力以获得这些参数如击穿电压、尺寸、电流负载能力和制造简易性的更接近的最佳组合。虽然上述结构都能在器件性能方面提供不同程度的改进，但是没有一种器件或结构能完全优化所有的针对高电压高电流工作的设计要求，并且能灵活地制造出PMOS以及NMOS器件。
因此，最好具有一种能够在高电压高电流环境下具有高性能的晶体管器件结构，并且具有能够采用普通技术实现PMOS结构的相对简单且经济的设计。
因此本发明的一个目的在于提供一种能够在高电压高电流环境下具有高性能的晶体管器件结构。本发明还有一个目的在于提供这样一种晶体管器件结构，其中PMOS器件可以采用普通的技术来简单而又经济地生产。
根据本发明，这些目的可以在上述类型的横向薄膜SOI PMOS器件结构中实现，其中横向漂移区设有线性分级的电荷分布，这样在横向漂移区中的掺杂级沿着从漏极区域朝着源区域的方向增加，并且其中表面邻接的p型导电型漏极延伸区域设在漂移区中并且从漏极区域延伸到源区域附近，但是没有与源区域直接接触。
在本发明的优选实施方案中，电介质层设在漂移区域上方，并且导电场电极设在电介质层上以及在漂移区域的至少一部分上方。
在本发明的另一个优选实施方案中，导电场电极与PMOS器件的源区域联接。
符合根据本发明的横向薄膜SOI PMOS器件提供的显著的改进之处在于，使得这些器件适用于在高电压高电流的环境下以及在特别高的击穿电压的情况下工作的令人满意的性能特性的组合，本发明的器件能够采用普通技术在能够实施PMOS结构的相对简单而又经济的设计中实现。
本发明的这些和其它方面将参照下面所述的实施方案来阐明并变得更加清楚。
参照以下说明书并结合附图来阅读将可以更加彻底地理解本发明，其中：
图1显示出根据本发明优选的实施方案的横向薄膜SOI PMOS器件的简化的剖视图；
图2显示出根据本发明另一个优选的实施方案的横向薄膜SOI PMOS器件的简化的剖视图。
图中，具有相同导电型的半导体区域在这些剖视图中被显示出沿着相同方向画有阴影线，并且应该理解的是这些图不是按比例画的。
在图1的简化的剖视图中，横向薄膜器件在这里是一种SOI PMOS晶体管20，它包括半导体基片22、埋入绝缘层24以及其中构造有该器件的半导体表面SOI层26。PMOS晶体管包括p型导电的源区域28,n型导电的体区域30,n型导电的横向漂移区32以及p型导电的漏极区域34。基本的器件结构还包括，门电极36，显示出通过氧化物绝缘区域38与该器件下面的半导体表面层26和其它导电部分彻底绝缘。
另外，PMOS晶体管20可以包括与源区或28接触的体接触表面区域40，它位于体区域30中并且与体区域的导电类型相同，但是比体区域的掺杂高。与源区域28的电接触由源接触电极42提供，而漏极区域34设有漏极接触电极44。
要知道的是，在该图显示出的简化的代表性器件描述了特定的器件结构，但是在本发明的范围可以采用在器件几何形状和结构方面的各种变形。
根据本发明，PMOS晶体管20设有面联接的p型导电漏极延伸区域46，它从漏极区34的区域延伸到源区域附近，但是没有和源区或28直接接触。另外，p型导电的缓冲区48可以选择地设在漂移区32中并且在漏极区34下面从漏极延伸区或46向下延伸到埋入绝缘层24上。
横向漂移区32在至少其横向范围的大部分上面设有线性分级的电荷分布，这样在横向漂移区中的掺杂级沿着从漏极区34朝着源区域28的方面增加。在横向漂移区中的线性分级电荷分布和与n型漂移区32形成表面p-n结的p型导电漏极延伸的组合导致一种新的器件结构，该结构通过结点和MOS RESURF机构的组合维持电压。
在图2的简化的剖视图中，显示出横向薄膜SOI PMOS器件的第二实施方案。由于该器件的下层结构类似于图1的结构，并且为了便于分辨，所以相同的元件分配有相同的附图标记，因此图2中与图1共有的部分将不再详细描述。图2的结构与图1的结构的不同之处在于电介质层50设在图1的PMOS器件上面，并且导电场电极52设在电介质层50上并且位于漂移区的至少一部分的上方。在本发明的优选实施方案中，导电场电极52设在大部分漂移区52上方，并且通过源电极42与源区域28相连。
虽然可以认识到在本发明的范围内可以考虑许多不同的结构和选择，但是各种代表性的设计参数和材料是以集中在与普通的现有技术结构不同的那些器件部分上的非限制性实施例给出的。
如上所述，本发明的PMOS器件形成在没有压缩的SOI层中，因此避免了与许多现有技术的器件一样在形成相对厚的局部氧化物区域方面的耗时、花费和复杂性。通常在本发明中所采用的没有压缩的SOI层26的厚度可以在大约1.0到1.5微米的范围内，并具有厚度大约为0.5微米的表面邻接p型导电漏极延伸区域46。用于SOI层的n型部分的通常的背景掺杂级大约在5×1015到1×1016cm-3的范围内，并具有线性分级的电荷分布，通过提供具有在大约9.0×1010到1.6×1011cm-2/微米的范围内的从漏极到源极1.6×1013到2.0×1013cm-2的最大n型插入，所述电荷分布被设在至少横向漂移区的主要部分上方，这样在横向漂移区中的掺杂级沿着从漏极区域朝着源极区域的方向增加。线性分级的电荷分布可以设在漂移区的整个横向范围上，或者设在小于其整个横向范围的大部分上。表面邻接漏极延伸区域掺杂有在大约2×1012到6×1012cm-2的范围内的p型导电掺杂剂，这样该漏极延伸区域就具有大约为7000ohms/平方英寸的额定薄膜电阻。
源极和漏极区域(28,34)为p型导电并且掺杂级大约为2×1015cm-2，并且n型体区域30的掺杂级在大约1×1013到5×1013cm-2的范围内。应该指出的是，采用独立的掺杂步骤以形成体区域是任选的，因为体区域可以选择性地由部分n型漂移区32形成。缓冲区48(可选的)的掺杂级在大约1×1013到3×1013cm-2的范围内，而n型导电体接触表面区域40的掺杂级为大约2×1015cm-2。
在图2的实施方案中，导电场电极52通常由金属例如铝形成，并且设在电介质层50的上方，该电介质层厚度通常在大约1.0-1.5微米的范围内并且由沉积的氧化物、氮化物或这两种材料形成。
要重点指出的是，上述参数只是构成代表值，应该知道的是在本发明的范围内可以设想许多不同的结构和变化，尤其是对于掺杂级、层厚、有或没有任意区等方面，只要是本发明的必要技术特征都可以被结合，尤其是在其横向范围的主要部分上提供具有线性分级的电荷分布的横向漂移区，并且在漂移区中提供表面邻接的p型导电漏极延伸区域。
通过上述方式，本发明提供一种能够在高电压高电流环境下具有高性能的横向SOI器件结构，同时使得能够采用普通的技术以简单而又经济的方式制造PMOS器件。
虽然已经参照几个优选实施方案具体显示并描述了本发明，但是对于那些本领域普通技术人员来说应该理解的是，在不脱离本发明的精神或范围的情况下可以作出各种形式的变化。在该申请中应该理解的是元件前面的单词“a”或“an”没有包含这种元件的数量，并且单词“包含”没有排除那些所描述的或请求的之外的其它元件或步骤。

Claims (6)

1．一种横向薄膜硅绝缘体(SOI)PMOS器件(20)，包含半导体基片(22)、在所述基片上的埋入绝缘层(24)以及在所述埋入绝缘层上的SOI层(26)中的横向PMOS晶体管器件，该晶体管器件具有：形成在n型导电的体区域(30)中的p型导电源区域(28)；邻近所述体区域的n型导电的横向漂移区(32)；p型导电并且通过所述横向漂移区(32)在横向上与所述体区域隔开的的漏极区域(34)；以及在一部分所述体区域上方的门电极(36)，其中沟道区在工作期间形成并且在靠近所述体区域的所述横向漂移区的一部分的上方延申，所述门电极(36)通过绝缘区域(38)与所述体区域(30)和漂移区(32)绝缘，其特征在于，所述横向漂移区(32)在至少其横向范围的主要部分上方设有线性分级电荷分布，这样在所述横向漂移区中的掺杂级沿着从所述漏极区域(34)朝着所述区域(28)的方向增加，并且表面邻接p型导电漏极延伸区域(46)设在所述漂移区(32)中并且从所述漏极区域(34)延伸到源区域附近，但是没有直接与所述源区域(28)接触。
2．如权利要求1所述的横向薄膜硅绝缘体(SOI)PMOS器件(20)，其中所述n型体区域(30)由所述n型漂移区(32)的一部分形成。
3．如权利要求1所述的横向薄膜硅绝缘体(SOI)PMOS器件(20)，其中N型导电的体接触表面区域(40)设在所述体区域中并接触所述源区域。
4．如权利要求1所述的横向薄膜硅绝缘体(SOI)PMOS器件(20)，还包含在所述漂移区(32)中的P型导电的缓冲区(48)，该缓冲区在所述漏极区域(34)下面从所述漏极延伸区域(46)延伸到所述埋入绝缘层(24)。
5．如权利要求1所述的横向薄膜硅绝缘体(SOI)PMOS器件(20)，还包含在所述PMOS器件上方的电介质层(50)以及在所述电介质层上并且位于所述漂移区(32)的至少一部分上方的导电场电极(52)。
6．如权利要求5所述的横向薄膜硅绝缘体(SOI)PMOS器件(20)，其中所述导电场电极(52)设在所述漂移区(32)的主要部分的上方，并且与PMOS器件的所述源区域(30)相连。
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