WO2023122876A1 - 薄膜晶体管及其制作方法、显示基板 - Google Patents

薄膜晶体管及其制作方法、显示基板 Download PDF

Info

Publication number
WO2023122876A1
WO2023122876A1 PCT/CN2021/141591 CN2021141591W WO2023122876A1 WO 2023122876 A1 WO2023122876 A1 WO 2023122876A1 CN 2021141591 W CN2021141591 W CN 2021141591W WO 2023122876 A1 WO2023122876 A1 WO 2023122876A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
orthographic projection
substrate
thin film
base substrate
Prior art date
Application number
PCT/CN2021/141591
Other languages
English (en)
French (fr)
Inventor
胡合合
王东方
刘凤娟
宁策
李正亮
贺家煜
曲燕
赵坤
黄杰
雷利平
林允植
张舜航
姚念琦
李菲菲
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/141591 priority Critical patent/WO2023122876A1/zh
Priority to CN202180004214.4A priority patent/CN116670834A/zh
Publication of WO2023122876A1 publication Critical patent/WO2023122876A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the technical field of thin film transistors, in particular to a thin film transistor, a manufacturing method thereof, and a display substrate.
  • TFT thin film transistor
  • the technical problem to be solved in the present disclosure is to provide a thin film transistor, its manufacturing method, and a display substrate, which can increase the withstand voltage range of the thin film transistor.
  • a thin film transistor comprising:
  • a source electrode and a drain electrode located on a side of the active layer away from the base substrate, the source electrode and the drain electrode are respectively connected to the active layer;
  • the resistance between the gate and the drain is greater than the resistance between the gate and the source.
  • the orthographic projection of the gate on the substrate does not overlap with the orthographic projection of the drain on the substrate, and the orthographic projection of the gate on the substrate The projection overlaps with an orthographic projection of the source on the substrate substrate.
  • the active layer includes a first part in contact with the drain and a second part in contact with the source, and the orthographic projection of the first part on the base substrate is the same as that of the gate
  • the orthographic projections of the poles on the base substrate do not overlap, and the orthographic projections of the second part on the base substrate overlap with the orthographic projections of the grid on the base substrate;
  • the thin film transistor also includes:
  • An additional gate the orthographic projection of the additional gate on the base substrate overlaps with the orthographic projection of the first portion on the base substrate.
  • the orthographic projection of the active layer on the substrate falls within the orthographic projection of the gate on the substrate;
  • the active layer includes a a first portion and a second portion in contact with the source;
  • the thin film transistor also includes:
  • the orthographic projection of the additional gate on the substrate falls within the orthographic projection of the gate on the substrate.
  • the shortest distance between the first boundary of the additional gate close to the source and the second boundary of the drain close to the source in a direction parallel to the substrate is a1, a1 is greater than 0 and less than L, where L is the channel length of the thin film transistor.
  • the active layer includes a first portion in contact with the drain and a second portion in contact with the source, and the resistivity of the first portion is greater than that of the second portion.
  • the resistivity Rs of the first part satisfies: 100M ⁇ / ⁇ Rs ⁇ 1M ⁇ / ⁇ .
  • the shortest distance between the third boundary of the first part on the side close to the source and the second boundary of the drain on the side close to the source in a direction parallel to the substrate It is a2 is greater than 0um and less than or equal to 2um.
  • the thin film transistor also includes:
  • the resistivity of the conductive pattern is greater than the resistivity of the drain, and the active layer is electrically connected to the drain through the conductive pattern .
  • the resistivity R of the conductive pattern satisfies: 100M ⁇ / ⁇ R ⁇ 1M ⁇ / ⁇ .
  • the orthographic projection of the gate on the substrate does not overlap with the orthographic projection of the source on the substrate, and the orthographic projection of the gate on the substrate does not overlap with the orthographic projection of the source on the substrate.
  • the orthographic projections of the drains on the base substrate do not overlap;
  • the fourth boundary of the first orthographic projection of the gate on the base substrate close to the source is the same as the second orthographic projection of the source on the base substrate close to the gate.
  • the distance between the fifth boundary of the side is a3,
  • the first orthographic projection of the gate on the substrate is close to the sixth boundary on the side of the drain and the third orthographic projection of the drain on the substrate is close to the gate.
  • the distance between the seventh boundary of the side is a3,
  • a3 is greater than 0.
  • a3 is less than 2um.
  • the thin film transistor also includes:
  • the active layer includes a third part and a fourth part, the orthographic projection of the third part on the base substrate is located between the first orthographic projection and the second orthographic projection, and is identical to the Neither the first orthographic projection nor the second orthographic projection coincides, and the orthographic projection of the fourth part on the base substrate is located between the first orthographic projection and the third orthographic projection, and is consistent with the Neither the first orthographic projection nor the third orthographic projection overlaps, and the third portion and the fourth portion are lightly doped regions.
  • An embodiment of the present disclosure provides a display substrate including the thin film transistor as described above.
  • the voltage applied to the additional gate is 5-10V.
  • the voltage applied to the gate is V1
  • the voltage applied to the additional gate is V/2-V.
  • An embodiment of the present disclosure provides a method for manufacturing a thin film transistor, including:
  • An active layer is formed on a side of the gate away from the base substrate, and an orthographic projection of the active layer on the base substrate overlaps with an orthographic projection of the gate on the base substrate ;
  • the resistance between the gate and the drain is greater than the resistance between the gate and the source.
  • FIGS. 1-10 are structural schematic diagrams of thin film transistors according to embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of the relationship between the value of embodiment a of the present disclosure and the breakdown voltage of the thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor, a manufacturing method thereof, and a display substrate, which can improve the withstand voltage range of the thin film transistor.
  • An embodiment of the present disclosure provides a thin film transistor, including:
  • a source electrode and a drain electrode located on a side of the active layer away from the base substrate, the source electrode and the drain electrode are respectively connected to the active layer;
  • the resistance between the gate and the drain is greater than the resistance between the gate and the source.
  • the resistance between the gate and the drain of the thin film transistor is greater than the resistance between the gate and the source, and the withstand voltage range of the thin film transistor is proportional to the resistance between the gate and the drain.
  • the withstand voltage range of the thin film transistor is proportional to the resistance between the gate and the drain.
  • the orthographic projection of the gate on the substrate does not overlap with the orthographic projection of the drain on the substrate, and the orthographic projection of the gate on the substrate The projection overlaps with the orthographic projection of the source on the base substrate, so that the active layer between the gate and the drain is far away from the gate, where the electric field of the gate is weak, and it is difficult for the gate to respond to this Part of the active layer is effectively regulated, so that the resistance of the channel between the gate and the drain can be increased, the current density near the drain can be reduced, and the withstand voltage range of the thin film transistor can be improved.
  • a thin film transistor includes a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer 08 on a base substrate 06, wherein , the active layer 04 includes a first portion 042 in contact with the drain 03 and a second portion 043 in contact with the source 02, the orthographic projection of the first portion 042 on the base substrate is identical to the The orthographic projection of the grid 01 on the base substrate does not overlap, and the orthographic projection of the second part 043 on the base substrate overlaps with the orthographic projection of the grid 02 on the base substrate , can be completely overlapped or partially overlapped, so that the distance between the gate 02 and the first part 042 is relatively long, and it is difficult for the gate 02 to effectively regulate the first part 042, so that the resistance of the first part 042 can be increased when the thin film transistor is working , reducing the current density near the drain 03 , thereby increasing the withstand voltage range of the thin film transistor.
  • the thin film transistor While it is difficult for the gate 02 to effectively regulate the first part 042, it will reduce the on-state current of the thin film transistor.
  • the thin film transistor also includes:
  • the orthographic projection partially overlaps the orthographic projection of the first portion 042 on the base substrate, or the orthographic projection of the additional grid on the substrate falls within the orthographic projection of the first portion 042 on the substrate substrate, or , the orthographic projection of the first portion 042 on the substrate falls within the orthographic projection of the additional gate on the substrate.
  • the first part 042 can be regulated, and the on-state current of the thin film transistor can be adjusted. Specifically, when a positive voltage signal is applied to the additional gate 05, the current of the first part 042 can be reduced.
  • the resistor increases the on-state current of the thin film transistor; when a negative voltage signal is applied to the additional gate 05, the resistance of the first part 042 can be increased to reduce the on-state current of the thin film transistor.
  • the voltage applied to the additional gate 05 can be 5-10V, so as to ensure the on-state current of the thin film transistor.
  • the additional gate 05 can be located on the same side of the active layer 04 as the gate 01 , or can be located on a different side of the active layer 04 , and the additional gate 05 and the gate 01 are insulated from each other.
  • the first boundary of the additional gate 05 close to the source 02 and the second boundary of the drain 03 close to the source 02 are in a direction parallel to the substrate.
  • the shortest distance above is a1, a1 is greater than 0 and less than L, L is the channel length of the thin film transistor, the channel is the part of the active layer corresponding to the gap between the source and the drain, and the channel is on the base substrate
  • the orthographic projection overlaps the orthographic projection of the gap between the source and drain on the base substrate. a1 greater than 0 and less than L can ensure that the additional gate will not regulate all regions of the channel, but only mainly regulate the channel near the drain.
  • the thin film transistor includes a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer 08 on a base substrate 06, wherein , the active layer 04 includes a first portion 042 in contact with the drain 03 and a second portion 043 in contact with the source 02, and the orthographic projection of the active layer 04 on the substrate 06 is located at the gate 01 In the orthographic projection on the substrate substrate 06 .
  • the gate 01 can regulate the entire channel.
  • the thin film transistor further includes: An additional grid 05 on one side of the base substrate, the orthographic projection of the additional grid 05 on the base substrate overlaps with the orthographic projection of the first portion 042 on the base substrate. It may be that the orthographic projection of the additional grid on the base substrate partially overlaps the orthographic projection of the first portion 042 on the base substrate, or the orthographic projection of the additional grid on the base substrate falls into the first portion 042 on the base substrate. Or, the orthographic projection of the first portion 042 on the base substrate falls within the orthographic projection of the additional grid on the base substrate.
  • the orthographic projection of the additional grid 05 on the base substrate falls within the orthographic projection of the grid 01 on the base substrate, of course, the additional grid 05 is in A part of the orthographic projection on the base substrate may also be located outside the orthographic projection of the grid 01 on the base substrate.
  • the first part 042 can be regulated, the resistance of the first part 042 can be adjusted, and the on-state current of the thin film transistor can be adjusted.
  • a positive voltage signal is applied to the additional gate 05
  • the resistance of the first part 042 can be increased to reduce the on-state current of the thin film transistor.
  • the voltage applied to the additional gate 05 may be V1/2-V1, where V1 is the voltage applied to the gate.
  • the first boundary of the additional gate 05 close to the source 02 and the second boundary of the drain 03 close to the source 02 are in a direction parallel to the substrate.
  • the shortest distance above is a1, a1 is greater than 0 and less than L, L is the channel length of the thin film transistor, the channel is the part of the active layer corresponding to the gap between the source and the drain, and the channel is on the base substrate
  • the orthographic projection overlaps the orthographic projection of the gap between the source and drain on the base substrate. a1 greater than 0 and less than L can ensure that the additional gate will not regulate all regions of the channel, but only mainly regulate the channel near the drain.
  • the thin film transistor includes a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer 08 on a base substrate 06, wherein , the active layer 04 includes a first part 041 in contact with the drain 03 and a second part 043 in contact with the source 02, and the first part 041 can be subjected to a high-resistance treatment, for example, the first part 041 is Plasma treatment makes the resistivity of the first part 041 greater than that of the second part 043, so that when the thin film transistor is working, the resistance of the first part 041 can be increased, the current density near the drain 03 can be reduced, and the resistance of the thin film transistor can be improved. pressure range.
  • the resistivity Rs of the first part 041 may satisfy: 100M ⁇ / ⁇ Rs ⁇ 1M ⁇ / ⁇ .
  • the third boundary of the first portion 041 on the side close to the source 02 and the second boundary of the drain 03 on the side close to the source 02 are parallel to the base substrate.
  • the shortest distance in the direction is a2, and a2 is greater than 0um and less than or equal to 2um. This will not make the entire channel a high-resistance area, but only ensure that the resistance of the channel close to the drain is relatively large.
  • the thin film transistor includes a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer 08 on a base substrate 06, wherein A conductive pattern 09 is arranged between the active layer 04 and the drain 03, the resistivity of the conductive pattern 09 is greater than the resistivity of the drain 03, and the active layer 04 communicates with the conductive pattern 09 through the conductive pattern 09
  • the drain 03 is electrically connected. In this way, by setting the conductive pattern 09 with high resistance, the resistance between the gate 01 and the drain 03 can be relatively large, the current density near the drain 03 can be reduced, and the withstand voltage range of the thin film transistor can be increased.
  • the resistivity R of the conductive pattern 09 may satisfy: 100M ⁇ / ⁇ R ⁇ 1M ⁇ / ⁇ .
  • molybdenum oxide can be used for the conductive pattern 09 .
  • the thin film transistor includes a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer 08 on a base substrate 06, wherein , the orthographic projection of the gate 01 on the base substrate does not overlap with the orthographic projection of the source 02 on the base substrate, and the orthographic projection of the gate 01 on the substrate does not overlap with the drain
  • the orthographic projections of the pole 02 on the base substrate do not overlap;
  • the first orthographic projection of the gate 01 on the base substrate is close to the fourth boundary on the side of the source 02 and the source 02
  • the distance between the fifth boundary on the side of the second orthographic projection on the base substrate close to the gate 01 is a3, and the first orthographic projection of the gate 01 on the base substrate is close to the
  • the distance between the sixth boundary on the side of the drain 03 and the seventh boundary on the side of the gate 01 of the third orthographic projection of the drain 03 on the base substrate is a3, wherein a3 Greater than
  • the intensity of the gate electric field at the dotted ellipse frame is relatively weak, and this part of the channel (the channel in the dotted ellipse frame) cannot be effectively regulated, which will make the resistance of this part of the channel relatively large, reducing the
  • the current density near the drain 03 increases the withstand voltage range of the thin film transistor.
  • this part of the channel is hardly affected by the electric field of the gate, and the conductivity is poor.
  • a3 is less than 2um.
  • the orthographic projection of the grid 01 on the base substrate does not overlap with the orthographic projection of the source 02 on the base substrate
  • the orthographic projection of the gate 01 on the base substrate does not overlap with the The orthographic projection of the drain 02 on the base substrate does not overlap; there is no parasitic capacitance between the gate 01 and the source 02 and the drain 03, which can reduce the power consumption of the thin film transistor.
  • the thin film transistor also includes:
  • the buffer layer 10 located between the gate and the base substrate, the buffer layer can be SiNx, in which there is a large amount of hydrogen, which can diffuse into the active layer, making the active layer conductive, and improving the opening of the thin film transistor. state current;
  • the active layer includes a third portion 044 and a fourth portion 045, the orthographic projection of the third portion 044 on the base substrate is located between the first orthographic projection and the second orthographic projection, and Neither the first orthographic projection nor the second orthographic projection coincides, and the orthographic projection of the fourth portion 045 on the base substrate is located between the first orthographic projection and the third orthographic projection , and do not coincide with the first orthographic projection and the third orthographic projection, the third part 044 and the fourth part 045 are lightly doped regions, and the conductivity is enhanced, which is conducive to the on-state of the thin film transistor current.
  • the thickness of the gate insulating layer can be appropriately reduced, such as less than 300nm .
  • FIG. 5 and FIG. 6 show H-type thin film transistors.
  • the thin film transistors can also be V-type.
  • FIG. 7 is a schematic cross-sectional view of FIG. 9 along the direction indicated by a3.
  • the size of the gate is smaller than the size of the active layer, so that there is no overlap between the gate and the source and drain.
  • they can be arranged in the manner shown in Figure 10 to ensure that there is no overlap between the gate and the source and drain.
  • FIG. 11 is a schematic diagram of the relationship between the value of a and the breakdown voltage of the thin film transistor according to the embodiment of the present disclosure, wherein a includes a1, a2 and a3. It can be seen that when the value of a is less than or equal to 0, the breakdown voltage of the thin film transistor The voltage is relatively small, acting on 20V; when the value of a is greater than 0, the greater the value of a, the greater the breakdown voltage of the thin film transistor, which can improve the withstand voltage performance of the thin film transistor.
  • An embodiment of the present disclosure provides a display substrate including the thin film transistor as described above.
  • the display substrate includes a thin film transistor as shown in FIG. 1 , and when the display substrate is displaying, the voltage applied to the additional gate is 5-10V.
  • the display substrate includes a thin film transistor as shown in FIG. 2 , when the display substrate is displaying, the voltage applied to the gate is V1, and the voltage applied to the additional gate is V /2-V.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the display device includes but not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply.
  • the above structure of the display device does not constitute a limitation on the display device, and the display device may include more or less of the above components, or combine certain components, or arrange different components.
  • the display device includes but is not limited to a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device can be any product or component with display function such as LCD TV, liquid crystal display, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.
  • the display device may be a display product driven by high mobility and high voltage, such as a display product with a resolution above 4K, a TV product with a resolution above 8K, and a VR product.
  • An embodiment of the present disclosure provides a method for manufacturing a thin film transistor, including:
  • An active layer is formed on a side of the gate away from the base substrate, and an orthographic projection of the active layer on the base substrate overlaps with an orthographic projection of the gate on the base substrate ;
  • the resistance between the gate and the drain is greater than the resistance between the gate and the source.
  • the resistance between the gate and the drain of the thin film transistor is greater than the resistance between the gate and the source, and the withstand voltage range of the thin film transistor is proportional to the resistance between the gate and the drain.
  • the withstand voltage range of the thin film transistor is proportional to the resistance between the gate and the drain.
  • the orthographic projection of the gate on the substrate does not overlap with the orthographic projection of the drain on the substrate, and the orthographic projection of the gate on the substrate The projection overlaps with the orthographic projection of the source on the base substrate, so that the active layer between the gate and the drain is far away from the gate, where the electric field of the gate is weak, and it is difficult for the gate to respond to this Part of the active layer is effectively regulated, so that the resistance of the channel between the gate and the drain can be increased, the current density near the drain can be reduced, and the withstand voltage range of the thin film transistor can be improved.
  • forming a thin film transistor includes: sequentially forming a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer on a substrate 06. 08, wherein the active layer 04 includes a first part 042 in contact with the drain 03 and a second part 043 in contact with the source 02, and the positive side of the first part 042 on the base substrate
  • the projection does not overlap with the orthographic projection of the grid 01 on the base substrate, and the orthographic projection of the second part 043 on the base substrate is the same as the orthographic projection of the grid 02 on the base substrate.
  • the orthographic projection overlap can be complete or partial, so that the gate 02 is far away from the first part 042, and it is difficult for the gate 02 to effectively regulate the first part 042, so that when the thin film transistor is working, the first part 042 can be improved.
  • the resistance of 042 reduces the current density near the drain 03, thereby increasing the withstand voltage range of the thin film transistor.
  • the thin film transistor While it is difficult for the gate 02 to effectively regulate the first part 042, it will reduce the on-state current of the thin film transistor.
  • the thin film transistor also includes:
  • the orthographic projection partially overlaps the orthographic projection of the first portion 042 on the base substrate, or the orthographic projection of the additional grid on the substrate falls within the orthographic projection of the first portion 042 on the substrate substrate, or , the orthographic projection of the first portion 042 on the substrate falls within the orthographic projection of the additional gate on the substrate.
  • the first part 042 can be regulated and the on-state current of the thin film transistor can be adjusted. Specifically, when a positive voltage signal is applied to the additional gate 05, the current of the first part 042 can be reduced.
  • the resistor increases the on-state current of the thin film transistor; when a negative voltage signal is applied to the additional gate 05, the resistance of the first part 042 can be increased to reduce the on-state current of the thin film transistor.
  • the voltage applied to the additional gate 05 can be 5-10V, so as to ensure the on-state current of the thin film transistor.
  • the additional gate 05 can be located on the same side of the active layer 04 as the gate 01 , or can be located on a different side of the active layer 04 , and the additional gate 05 and the gate 01 are insulated from each other.
  • the first boundary of the additional gate 05 close to the source 02 and the second boundary of the drain 03 close to the source 02 are in a direction parallel to the substrate.
  • the shortest distance above is a1, a1 is greater than 0 and less than L, L is the channel length of the thin film transistor, the channel is the part of the active layer corresponding to the gap between the source and the drain, and the channel is on the base substrate
  • the orthographic projection overlaps the orthographic projection of the gap between the source and drain on the base substrate. a1 greater than 0 and less than L can ensure that the additional gate will not regulate all regions of the channel, but only mainly regulate the channel near the drain.
  • forming a thin film transistor includes: sequentially forming a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer on a substrate 06. 08, wherein the active layer 04 includes a first portion 042 in contact with the drain 03 and a second portion 043 in contact with the source 02, and the orthographic projection of the active layer 04 on the substrate 06 is located at The gate 01 is in orthographic projection on the substrate substrate 06 .
  • the gate 01 can regulate the entire channel.
  • the thin film transistor further includes: An additional grid 05 on one side of the base substrate, the orthographic projection of the additional grid 05 on the base substrate overlaps with the orthographic projection of the first portion 042 on the base substrate. It may be that the orthographic projection of the additional grid on the base substrate partially overlaps the orthographic projection of the first portion 042 on the base substrate, or the orthographic projection of the additional grid on the base substrate falls into the first portion 042 on the base substrate. Or, the orthographic projection of the first portion 042 on the base substrate falls within the orthographic projection of the additional grid on the base substrate.
  • the orthographic projection of the additional grid 05 on the base substrate falls within the orthographic projection of the grid 01 on the base substrate, of course, the additional grid 05 is in A part of the orthographic projection on the base substrate may also be located outside the orthographic projection of the grid 01 on the base substrate.
  • the first part 042 can be regulated, the resistance of the first part 042 can be adjusted, and the on-state current of the thin film transistor can be adjusted.
  • a positive voltage signal is applied to the additional gate 05
  • the resistance of the first part 042 can be increased to reduce the on-state current of the thin film transistor.
  • the voltage applied to the additional gate 05 may be V1/2-V1, where V1 is the voltage applied to the gate.
  • the first boundary of the additional gate 05 close to the source 02 and the second boundary of the drain 03 close to the source 02 are in a direction parallel to the substrate.
  • the shortest distance above is a1, a1 is greater than 0 and less than L, L is the channel length of the thin film transistor, the channel is the part of the active layer corresponding to the gap between the source and the drain, and the channel is on the base substrate
  • the orthographic projection overlaps the orthographic projection of the gap between the source and drain on the base substrate. a1 greater than 0 and less than L can ensure that the additional gate will not regulate all regions of the channel, but only mainly regulate the channel near the drain.
  • forming a thin film transistor includes: sequentially forming a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer on a substrate 06.
  • the active layer 04 includes a first portion 041 in contact with the drain 03 and a second portion 043 in contact with the source 02, and the first portion 041 can be subjected to high resistance treatment, for example, the second A part of 041 is subjected to plasma treatment, so that the resistivity of the first part 041 is greater than that of the second part 043, so that when the thin film transistor is working, the resistance of the first part 041 can be increased, the current density near the drain 03 can be reduced, and the thin film can be improved.
  • the withstand voltage range of the transistor is a first portion 041 in contact with the drain 03 and a second portion 043 in contact with the source 02, and the first portion 041 can be subjected to high resistance treatment, for example, the second A part of 041 is subjected to plasma treatment, so that the resistivity of the first part 041 is greater than that of the second part 043, so that when the thin film transistor is working, the resistance of the first part 041 can be increased, the current density near the drain 03 can be reduced, and the
  • the resistivity Rs of the first part 041 may satisfy: 100M ⁇ / ⁇ Rs ⁇ 1M ⁇ / ⁇ .
  • the third boundary of the first portion 041 on the side close to the source 02 and the second boundary of the drain 03 on the side close to the source 02 are parallel to the base substrate.
  • the shortest distance in the direction is a2, and a2 is greater than 0um and less than or equal to 2um. This will not make the entire channel a high-resistance area, but only ensure that the resistance of the channel close to the drain is relatively large.
  • forming a thin film transistor includes: sequentially forming a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer on a substrate 06. 08, wherein a conductive pattern 09 is formed between the active layer 04 and the drain 03, the resistivity of the conductive pattern 09 is greater than the resistivity of the drain 03, and the active layer 04 passes through the conductive pattern 09 It is electrically connected with the drain 03.
  • the conductive pattern 09 with high resistance, the resistance between the gate 01 and the drain 03 can be relatively large, the current density near the drain 03 can be reduced, and the withstand voltage range of the thin film transistor can be increased.
  • the resistivity R of the conductive pattern 09 may satisfy: 100M ⁇ / ⁇ R ⁇ 1M ⁇ / ⁇ .
  • molybdenum oxide can be used for the conductive pattern 09 .
  • forming a thin film transistor includes: sequentially forming a gate 01, a gate insulating layer 07, an active layer 04, a source 02, a drain 03, and an interlayer insulating layer on a substrate 06.
  • the orthographic projection of the grid 01 on the base substrate does not overlap with the orthographic projection of the source 02 on the base substrate, and the orthographic projection of the gate 01 on the base substrate and The orthographic projection of the drain 02 on the base substrate does not overlap;
  • the first orthographic projection of the gate 01 on the base substrate is close to the fourth boundary on the side of the source 02 and the The distance between the fifth boundary of the second orthographic projection of the source 02 on the base substrate on the side close to the gate 01 is a3, and the first orthographic projection of the gate 01 on the base substrate is a3.
  • FIG. 5 is a schematic plan view of the thin film transistor shown in FIG. 7
  • FIG. 7 is a schematic cross-sectional view of FIG. 5 along the direction indicated by a3.
  • the intensity of the gate electric field at the dotted ellipse frame is relatively weak, and this part of the channel (the channel in the dotted ellipse frame) cannot be effectively regulated, which will make the resistance of this part of the channel relatively large, reducing the
  • the current density near the drain 03 increases the withstand voltage range of the thin film transistor.
  • this part of the channel is hardly affected by the electric field of the gate, and the conductivity is poor.
  • a3 is less than 2um.
  • the orthographic projection of the grid 01 on the base substrate does not overlap with the orthographic projection of the source 02 on the base substrate
  • the orthographic projection of the gate 01 on the base substrate does not overlap with the The orthographic projection of the drain 02 on the base substrate does not overlap; there is no parasitic capacitance between the gate 01 and the source 02 and the drain 03, which can reduce the power consumption of the thin film transistor.
  • the manufacturing method of the thin film transistor further includes:
  • a buffer layer 10 is formed between the gate and the base substrate.
  • the buffer layer can be SiNx, which has a large amount of hydrogen, which can diffuse into the active layer, making the active layer conductive, and improving the opening of the thin film transistor. state current;
  • the active layer includes a third portion 044 and a fourth portion 045, the orthographic projection of the third portion 044 on the base substrate is located between the first orthographic projection and the second orthographic projection, and Neither the first orthographic projection nor the second orthographic projection coincides, and the orthographic projection of the fourth portion 045 on the base substrate is located between the first orthographic projection and the third orthographic projection , and do not coincide with the first orthographic projection and the third orthographic projection, the third part 044 and the fourth part 045 are lightly doped regions, and the conductivity is enhanced, which is conducive to the on-state of the thin film transistor current.
  • the hydrogen content in the buffer layer can be controlled, specifically, the ratio of NH 3 : SiH 4 in the film-forming process can be controlled to be >5.
  • the thickness of the gate insulating layer can be appropriately reduced, such as less than 300nm .
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for related parts, please refer to the description of the product embodiment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本公开提供了一种薄膜晶体管及其制作方法、显示基板，属于薄膜晶体管技术领域。其中，薄膜晶体管包括：衬底基板；位于所述衬底基板上的栅极；位于所述栅极远离所述衬底基板一侧的有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；位于所述有源层远离所述衬底基板一侧的源极和漏极，所述源极和所述漏极分别与所述有源层连接；其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。本公开能够提高薄膜晶体管的耐压范围。

Description

薄膜晶体管及其制作方法、显示基板 技术领域
本公开涉及薄膜晶体管技术领域，特别是指一种薄膜晶体管及其制作方法、显示基板。
背景技术
目前，薄膜晶体管(TFF)阵列已经在显示产品领域得到了广泛的应用。随着显示产品对TFT驱动电流的提升，所需驱动电压也逐渐增大，驱动电压增大会导致TFT击穿或失效。因此，TFT耐压能力的提升非常重要。
发明内容
本公开要解决的技术问题是提供一种薄膜晶体管及其制作方法、显示基板，能够提高薄膜晶体管的耐压范围。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种薄膜晶体管，包括：
衬底基板；
位于所述衬底基板上的栅极；
位于所述栅极远离所述衬底基板一侧的有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
位于所述有源层远离所述衬底基板一侧的源极和漏极，所述源极和所述漏极分别与所述有源层连接；
其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
一些实施例中，所述栅极在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠，所述栅极在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影重叠。
一些实施例中，所述有源层包括与所述漏极接触的第一部分和与所述源 极接触的第二部分，所述第一部分在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影不重叠，所述第二部分在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
所述薄膜晶体管还包括：
附加栅极，所述附加栅极在所述衬底基板上的正投影与所述第一部分在所述衬底基板上的正投影重叠。
一些实施例中，所述有源层在所述衬底基板上的正投影落入所述栅极在所述衬底基板上的正投影内；所述有源层包括与所述漏极接触的第一部分和与所述源极接触的第二部分；
所述薄膜晶体管还包括：
位于所述有源层远离所述衬底基板一侧的附加栅极，所述附加栅极在所述衬底基板上的正投影与所述第一部分在所述衬底基板上的正投影重叠。
一些实施例中，所述附加栅极在所述衬底基板上的正投影落入所述栅极在所述衬底基板上的正投影内。
一些实施例中，所述附加栅极靠近所述源极一侧的第一边界与所述漏极靠近所述源极的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度。
一些实施例中，所述有源层包括与所述漏极接触的第一部分和与所述源极接触的第二部分，所述第一部分的电阻率大于所述第二部分的电阻率。
一些实施例中，所述第一部分的电阻率Rs满足：100MΩ/□≥Rs≥1MΩ/□。
一些实施例中，所述第一部分靠近所述源极一侧的第三边界与所述漏极靠近所述源极一侧的第二边界在平行于所述衬底基板的方向上的最短距离为a2，a2大于0um小于等于2um。
一些实施例中，所述薄膜晶体管还包括：
位于所述有源层和所述漏极之间的导电图形，所述导电图形的电阻率大于所述漏极的电阻率，所述有源层通过所述导电图形与所述漏极电连接。
一些实施例中，所述导电图形的电阻率R满足：100MΩ/□≥R≥1MΩ/□。
一些实施例中，所述栅极在衬底基板上的正投影与所述源极在所述衬底 基板上的正投影不重叠，所述栅极在衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠；
所述栅极在所述衬底基板上的第一正投影靠近所述源极一侧的第四边界与所述源极在所述衬底基板上的第二正投影靠近所述栅极一侧的第五边界之间的距离为a3，
所述栅极在所述衬底基板上的第一正投影靠近所述漏极一侧的第六边界与所述漏极在所述衬底基板上的第三正投影靠近所述栅极一侧的第七边界之间的距离为a3，
其中，a3大于0。
一些实施例中，a3小于2um。
一些实施例中，所述薄膜晶体管还包括：
位于所述栅极和所述衬底基板之间的缓冲层；
所述有源层包括第三部分和第四部分，所述第三部分在所述衬底基板上的正投影位于所述第一正投影与所述第二正投影之间，且与所述第一正投影和所述第二正投影均不重合，所述第四部分在所述衬底基板上的正投影位于所述第一正投影与所述第三正投影之间，且与所述第一正投影和所述第三正投影均不重合，所述第三部分和所述第四部分为轻掺杂区域。
本公开的实施例提供一种显示基板，包括如上所述的薄膜晶体管。
一些实施例中，在所述显示基板进行显示时，施加在所述附加栅极上的电压为5-10V。
一些实施例中，在所述显示基板进行显示时，施加在所述栅极上的电压为V1，施加在所述附加栅极上的电压为V/2-V。
本公开的实施例提供一种薄膜晶体管的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成栅极；
在所述栅极远离所述衬底基板的一侧形成有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
在所述有源层远离所述衬底基板的一侧形成源极和漏极，所述源极和所 述漏极分别与所述有源层连接；
其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
附图说明
图1-图10为本公开实施例薄膜晶体管的结构示意图；
图11为本公开实施例a的值与薄膜晶体管的击穿电压之间的关系示意图。
附图标记
01 栅极
02 源极
03 漏极
04 有源层
05 附加栅极
06 衬底基板
07 栅绝缘层
08 层间绝缘层
041、042 第一部分
043 第二部分
044 第三部分
045 第四部分
09 导电图形
10 缓冲层
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开的实施例提供一种薄膜晶体管及其制作方法、显示基板，能够提高薄膜晶体管的耐压范围。
本公开的实施例提供一种薄膜晶体管，包括：
衬底基板；
位于所述衬底基板上的栅极；
位于所述栅极远离所述衬底基板一侧的有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
位于所述有源层远离所述衬底基板一侧的源极和漏极，所述源极和所述漏极分别与所述有源层连接；
其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
本实施例中，薄膜晶体管的栅极与漏极之间的电阻大于栅极与源极之间的电阻，薄膜晶体管的耐压范围与栅极与漏极之间的电阻成正比，本实施例中，通过将栅极与漏极之间的电阻设置的比较大，能够降低漏极附近的电流密度，提高薄膜晶体管的耐压范围。
一些实施例中，所述栅极在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠，所述栅极在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影重叠，这样栅极与漏极之间的有源层部分距离栅极较远，此位置栅极电场较弱，栅极难以对这部分有源层形成有效调控，从而能够提高栅极与漏极之间沟道的电阻，降低漏极附近的电流密度，进而提高薄膜晶体管的耐压范围。
一具体示例中，如图1所示，薄膜晶体管包括位于衬底基板06上的栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分042和与所述源极02接触的第二部分043，所述第一部分042在所述衬底基板上的正投影与所述栅极01在所述衬底基板上的正投影不重叠，所述第二部分043在所述衬底基板上的正投影与所述栅极02在所述衬底基板上的正投影重叠，可以是完全重叠也可以是部分重叠，这样栅极02与第一部分042的距离较远，栅极02难以对第一部分042形成有效调控，从而在薄膜晶体管工作时，能够提高第一部分042的电阻，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
栅极02难以对第一部分042形成有效调控的同时，会降低薄膜晶体管的开态电流，为了保证薄膜晶体管的开态电流，如图1所示，所述薄膜晶体管还包括：
附加栅极05，所述附加栅极05在所述衬底基板上的正投影与所述第一部分042在所述衬底基板上的正投影重叠，可以是附加栅极在衬底基板上的正投影与第一部分042在所述衬底基板上的正投影部分重叠，或者，附加栅极在衬底基板上的正投影落入第一部分042在所述衬底基板上的正投影内，或者，第一部分042在所述衬底基板上的正投影落入附加栅极在衬底基板上的正投影内。
这样通过在附加栅极05上施加电信号，可以对第一部分042进行调控，调整薄膜晶体管的开态电流，具体地，在向附加栅极05上施加正电压信号时，能够降低第一部分042的电阻，提高薄膜晶体管的开态电流；在向附加栅极05上施加负电压信号时，能够提高第一部分042的电阻，降低薄膜晶体管的开态电流。具体地，在薄膜晶体管工作时，施加在附加栅极05上的电压可以为5-10V，这样可以保证薄膜晶体管的开态电流。
附加栅极05可以与栅极01位于有源层04的同一侧，也可以位于有源层04的不同侧，并且，附加栅极05与栅极01之间彼此绝缘。
如图1所示，所述附加栅极05靠近所述源极02一侧的第一边界与所述漏极03靠近所述源极02的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度，沟道即有源层对应源极和漏极之间间隙的部分，沟道在衬底基板上的正投影与源极和漏极之间间隙在衬底基板上的正投影重叠。a1大于0小于L可以保证附加栅极不会对沟道的所有区域进行调控，而只会主要调控靠近漏极的沟道。
一具体示例中，如图2所示，薄膜晶体管包括位于衬底基板06上的栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分042和与所述源极02接触的第二部分043，有源层04在衬底基板06上的正投影位于栅极01在衬底基板06上的正投影内。
本实施例中，栅极01能够对整个沟道进行调控，为了增加栅极与漏极之间的电阻，如图2所示，所述薄膜晶体管还包括：位于所述有源层04远离所述衬底基板一侧的附加栅极05，所述附加栅极05在所述衬底基板上的正投影与所述第一部分042在所述衬底基板上的正投影重叠。可以是附加栅极在衬底基板上的正投影与第一部分042在所述衬底基板上的正投影部分重叠，或者，附加栅极在衬底基板上的正投影落入第一部分042在所述衬底基板上的正投影内，或者，第一部分042在所述衬底基板上的正投影落入附加栅极在衬底基板上的正投影内。
如图2所示，所述附加栅极05在所述衬底基板上的正投影落入所述栅极01在所述衬底基板上的正投影内，当然，所述附加栅极05在所述衬底基板上的正投影的一部分还可以位于所述栅极01在所述衬底基板上的正投影之外。
这样通过在附加栅极05上施加电信号，可以对第一部分042进行调控，调整第一部分042的电阻，并调整薄膜晶体管的开态电流，具体地，在向附加栅极05上施加正电压信号时，能够降低第一部分042的电阻，提高薄膜晶体管的开态电流；在向附加栅极05上施加负电压信号时，能够提高第一部分042的电阻，降低薄膜晶体管的开态电流。具体地，在薄膜晶体管工作时，施加在附加栅极05上的电压可以为V1/2-V1，V1为施加在栅极上的电压。
如图2所示，所述附加栅极05靠近所述源极02一侧的第一边界与所述漏极03靠近所述源极02的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度，沟道即有源层对应源极和漏极之间间隙的部分，沟道在衬底基板上的正投影与源极和漏极之间间隙在衬底基板上的正投影重叠。a1大于0小于L可以保证附加栅极不会对沟道的所有区域进行调控，而只会主要调控靠近漏极的沟道。
一具体示例中，如图3所示，薄膜晶体管包括位于衬底基板06上的栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分041和与所述源极02接触的第二部分043，可以对第一部分041进行高阻化处理，比如对第一部分041 进行等离子体处理，使得第一部分041的电阻率大于第二部分043的电阻率，从而在薄膜晶体管工作时，能够提高第一部分041的电阻，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
具体地，所述第一部分041的电阻率Rs可以满足：100MΩ/□≥Rs≥1MΩ/□。
如图3所示，所述第一部分041靠近所述源极02一侧的第三边界与所述漏极03靠近所述源极02一侧的第二边界在平行于所述衬底基板的方向上的最短距离为a2，a2大于0um小于等于2um，这样不会使得整个沟道都是高阻区，而只会保证靠近漏极的沟道的电阻比较大。
一具体示例中，如图4所示，薄膜晶体管包括位于衬底基板06上的栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，在有源层04和漏极03之间设置有导电图形09，所述导电图形09的电阻率大于所述漏极03的电阻率，所述有源层04通过所述导电图形09与所述漏极03电连接。这样，通过设置高电阻的导电图形09，能够使得栅极01与漏极03之间的电阻比较大，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
一些实施例中，所述导电图形09的电阻率R可以满足：100MΩ/□≥R≥1MΩ/□。具体地，导电图形09可以采用氧化钼。
一具体示例中，如图7所示，薄膜晶体管包括位于衬底基板06上的栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述栅极01在衬底基板上的正投影与所述源极02在所述衬底基板上的正投影不重叠，所述栅极01在衬底基板上的正投影与所述漏极02在所述衬底基板上的正投影不重叠；所述栅极01在所述衬底基板上的第一正投影靠近所述源极02一侧的第四边界与所述源极02在所述衬底基板上的第二正投影靠近所述栅极01一侧的第五边界之间的距离为a3，所述栅极01在所述衬底基板上的第一正投影靠近所述漏极03一侧的第六边界与所述漏极03在所述衬底基板上的第三正投影靠近所述栅极01一侧的第七边界之间的距离为a3，其中，a3大于0。图5为图7所示薄膜晶体管的平面示意图，图7为图5在a3所示方向上的截面示意图。
本实施例中，栅极电场在椭圆虚线框处的强度比较弱，对该部分沟道(椭圆虚线框内的沟道)不能形成有效地调控，会使得该部分沟道的电阻比较大，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。在栅极开启时，该部分沟道几乎不受栅极电场的影响，导电性能较差，为了保证薄膜晶体管的开态电流，a3小于2um。
另外，所述栅极01在衬底基板上的正投影与所述源极02在所述衬底基板上的正投影不重叠，所述栅极01在衬底基板上的正投影与所述漏极02在所述衬底基板上的正投影不重叠；栅极01与源极02和漏极03之间不存在寄生电容，能够降低薄膜晶体管的功耗。
为了保证薄膜晶体管的开态电流，如图8所示，所述薄膜晶体管还包括：
位于所述栅极和所述衬底基板之间的缓冲层10，缓冲层可以采用SiNx，其中有大量的氢，可以扩散到有源层中，使得有源层导体化，提高薄膜晶体管的开态电流；
所述有源层包括第三部分044和第四部分045，所述第三部分044在所述衬底基板上的正投影位于所述第一正投影与所述第二正投影之间，且与所述第一正投影和所述第二正投影均不重合，所述第四部分045在所述衬底基板上的正投影位于所述第一正投影与所述第三正投影之间，且与所述第一正投影和所述第三正投影均不重合，所述第三部分044和所述第四部分045为轻掺杂区域，导电性能增强，有利于薄膜晶体管的开态电流。
由于栅极的阻挡，有源层对应栅极的区域受氢的影响较小，可以满足半导体的开关作用；并且由于薄膜晶体管的耐压性能提升，栅绝缘层的厚度可以适当降低，比如小于300nm。
在多个薄膜晶体管的情况下，可以按照图6所示的方式进行排布，保证栅极与源极和漏极之间无交叠。
图5和图6所示为H型薄膜晶体管，如图9所示，薄膜晶体管还可以为V型，图7为图9在a3所示方向上的截面示意图。在a3所示方向上，栅极的尺寸小于有源层的尺寸，使得栅极与源极和漏极之间无交叠。在多个薄膜晶体管的情况下，可以按照图10所示的方式进行排布，保证栅极与源极和漏 极之间无交叠。
图11为本公开实施例a的值与薄膜晶体管的击穿电压之间的关系示意图，其中，a包括a1、a2和a3，可以看出，a的值小于等于0时，薄膜晶体管的击穿电压比较小，为20V作用；当a的值大于0时，a的值越大，薄膜晶体管的击穿电压越大，可以提高薄膜晶体管的耐压性能。
本公开的实施例提供一种显示基板，包括如上所述的薄膜晶体管。
一些实施例中，显示基板包括如图1所示的薄膜晶体管，在所述显示基板进行显示时，施加在所述附加栅极上的电压为5-10V。
一些实施例中，显示基板包括如图2所示的薄膜晶体管，在所述显示基板进行显示时，施加在所述栅极上的电压为V1，施加在所述附加栅极上的电压为V/2-V。
本公开的实施例还提供一种显示装置，包括如上所述的显示基板。该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
具体地，显示装置可以为高迁移率高电压驱动的显示产品，如4K分辨率以上显示产品、8K分辨率以上电视产品和VR产品等。
本公开的实施例提供一种薄膜晶体管的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成栅极；
在所述栅极远离所述衬底基板的一侧形成有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
在所述有源层远离所述衬底基板的一侧形成源极和漏极，所述源极和所述漏极分别与所述有源层连接；
其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
本实施例中，薄膜晶体管的栅极与漏极之间的电阻大于栅极与源极之间的电阻，薄膜晶体管的耐压范围与栅极与漏极之间的电阻成正比，本实施例中，通过将栅极与漏极之间的电阻设置的比较大，能够降低漏极附近的电流密度，提高薄膜晶体管的耐压范围。
一些实施例中，所述栅极在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠，所述栅极在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影重叠，这样栅极与漏极之间的有源层部分距离栅极较远，此位置栅极电场较弱，栅极难以对这部分有源层形成有效调控，从而能够提高栅极与漏极之间沟道的电阻，降低漏极附近的电流密度，进而提高薄膜晶体管的耐压范围。
一具体示例中，如图1所示，形成薄膜晶体管包括：在衬底基板06上依次形成栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分042和与所述源极02接触的第二部分043，所述第一部分042在所述衬底基板上的正投影与所述栅极01在所述衬底基板上的正投影不重叠，所述第二部分043在所述衬底基板上的正投影与所述栅极02在所述衬底基板上的正投影重叠，可以是完全重叠也可以是部分重叠，这样栅极02与第一部分042的距离较远，栅极02难以对第一部分042形成有效调控，从而在薄膜晶体管工作时，能够提高第一部分042的电阻，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
栅极02难以对第一部分042形成有效调控的同时，会降低薄膜晶体管的开态电流，为了保证薄膜晶体管的开态电流，如图1所示，所述薄膜晶体管还包括：
附加栅极05，所述附加栅极05在所述衬底基板上的正投影与所述第一 部分042在所述衬底基板上的正投影重叠，可以是附加栅极在衬底基板上的正投影与第一部分042在所述衬底基板上的正投影部分重叠，或者，附加栅极在衬底基板上的正投影落入第一部分042在所述衬底基板上的正投影内，或者，第一部分042在所述衬底基板上的正投影落入附加栅极在衬底基板上的正投影内。
这样通过在附加栅极05上施加电信号，可以对第一部分042进行调控，调整薄膜晶体管的开态电流，具体地，在向附加栅极05上施加正电压信号时，能够降低第一部分042的电阻，提高薄膜晶体管的开态电流；在向附加栅极05上施加负电压信号时，能够提高第一部分042的电阻，降低薄膜晶体管的开态电流。具体地，在薄膜晶体管工作时，施加在附加栅极05上的电压可以为5-10V，这样可以保证薄膜晶体管的开态电流。
附加栅极05可以与栅极01位于有源层04的同一侧，也可以位于有源层04的不同侧，并且，附加栅极05与栅极01之间彼此绝缘。
如图1所示，所述附加栅极05靠近所述源极02一侧的第一边界与所述漏极03靠近所述源极02的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度，沟道即有源层对应源极和漏极之间间隙的部分，沟道在衬底基板上的正投影与源极和漏极之间间隙在衬底基板上的正投影重叠。a1大于0小于L可以保证附加栅极不会对沟道的所有区域进行调控，而只会主要调控靠近漏极的沟道。
一具体示例中，如图2所示，形成薄膜晶体管包括：在衬底基板06上依次形成栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分042和与所述源极02接触的第二部分043，有源层04在衬底基板06上的正投影位于栅极01在衬底基板06上的正投影内。
本实施例中，栅极01能够对整个沟道进行调控，为了增加栅极与漏极之间的电阻，如图2所示，所述薄膜晶体管还包括：位于所述有源层04远离所述衬底基板一侧的附加栅极05，所述附加栅极05在所述衬底基板上的正投影与所述第一部分042在所述衬底基板上的正投影重叠。可以是附加栅极在 衬底基板上的正投影与第一部分042在所述衬底基板上的正投影部分重叠，或者，附加栅极在衬底基板上的正投影落入第一部分042在所述衬底基板上的正投影内，或者，第一部分042在所述衬底基板上的正投影落入附加栅极在衬底基板上的正投影内。
如图2所示，所述附加栅极05在所述衬底基板上的正投影落入所述栅极01在所述衬底基板上的正投影内，当然，所述附加栅极05在所述衬底基板上的正投影的一部分还可以位于所述栅极01在所述衬底基板上的正投影之外。
这样通过在附加栅极05上施加电信号，可以对第一部分042进行调控，调整第一部分042的电阻，并调整薄膜晶体管的开态电流，具体地，在向附加栅极05上施加正电压信号时，能够降低第一部分042的电阻，提高薄膜晶体管的开态电流；在向附加栅极05上施加负电压信号时，能够提高第一部分042的电阻，降低薄膜晶体管的开态电流。具体地，在薄膜晶体管工作时，施加在附加栅极05上的电压可以为V1/2-V1，V1为施加在栅极上的电压。
如图2所示，所述附加栅极05靠近所述源极02一侧的第一边界与所述漏极03靠近所述源极02的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度，沟道即有源层对应源极和漏极之间间隙的部分，沟道在衬底基板上的正投影与源极和漏极之间间隙在衬底基板上的正投影重叠。a1大于0小于L可以保证附加栅极不会对沟道的所有区域进行调控，而只会主要调控靠近漏极的沟道。
一具体示例中，如图3所示，形成薄膜晶体管包括：在衬底基板06上依次形成栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述有源层04包括与所述漏极03接触的第一部分041和与所述源极02接触的第二部分043，可以对第一部分041进行高阻化处理，比如对第一部分041进行等离子体处理，使得第一部分041的电阻率大于第二部分043的电阻率，从而在薄膜晶体管工作时，能够提高第一部分041的电阻，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
具体地，所述第一部分041的电阻率Rs可以满足：100MΩ/□≥Rs≥1MΩ/□。
如图3所示，所述第一部分041靠近所述源极02一侧的第三边界与所述漏极03靠近所述源极02一侧的第二边界在平行于所述衬底基板的方向上的最短距离为a2，a2大于0um小于等于2um，这样不会使得整个沟道都是高阻区，而只会保证靠近漏极的沟道的电阻比较大。
一具体示例中，如图4所示，形成薄膜晶体管包括：在衬底基板06上依次形成栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，在有源层04和漏极03之间形成导电图形09，所述导电图形09的电阻率大于所述漏极03的电阻率，所述有源层04通过所述导电图形09与所述漏极03电连接。这样，通过设置高电阻的导电图形09，能够使得栅极01与漏极03之间的电阻比较大，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。
一些实施例中，所述导电图形09的电阻率R可以满足：100MΩ/□≥R≥1MΩ/□。具体地，导电图形09可以采用氧化钼。
一具体示例中，如图7所示，形成薄膜晶体管包括：在衬底基板06上依次形成栅极01、栅绝缘层07、有源层04、源极02、漏极03、层间绝缘层08，其中，所述栅极01在衬底基板上的正投影与所述源极02在所述衬底基板上的正投影不重叠，所述栅极01在衬底基板上的正投影与所述漏极02在所述衬底基板上的正投影不重叠；所述栅极01在所述衬底基板上的第一正投影靠近所述源极02一侧的第四边界与所述源极02在所述衬底基板上的第二正投影靠近所述栅极01一侧的第五边界之间的距离为a3，所述栅极01在所述衬底基板上的第一正投影靠近所述漏极03一侧的第六边界与所述漏极03在所述衬底基板上的第三正投影靠近所述栅极01一侧的第七边界之间的距离为a3，其中，a3大于0。图5为图7所示薄膜晶体管的平面示意图，图7为图5在a3所示方向上的截面示意图。
本实施例中，栅极电场在椭圆虚线框处的强度比较弱，对该部分沟道(椭圆虚线框内的沟道)不能形成有效地调控，会使得该部分沟道的电阻比较大，降低漏极03附近的电流密度，进而提高薄膜晶体管的耐压范围。在栅极开启时，该部分沟道几乎不受栅极电场的影响，导电性能较差，为了保证薄膜晶 体管的开态电流，a3小于2um。
另外，所述栅极01在衬底基板上的正投影与所述源极02在所述衬底基板上的正投影不重叠，所述栅极01在衬底基板上的正投影与所述漏极02在所述衬底基板上的正投影不重叠；栅极01与源极02和漏极03之间不存在寄生电容，能够降低薄膜晶体管的功耗。
为了保证薄膜晶体管的开态电流，如图8所示，所述薄膜晶体管的制作方法还包括：
在所述栅极和所述衬底基板之间形成缓冲层10，缓冲层可以采用SiNx，其中有大量的氢，可以扩散到有源层中，使得有源层导体化，提高薄膜晶体管的开态电流；
所述有源层包括第三部分044和第四部分045，所述第三部分044在所述衬底基板上的正投影位于所述第一正投影与所述第二正投影之间，且与所述第一正投影和所述第二正投影均不重合，所述第四部分045在所述衬底基板上的正投影位于所述第一正投影与所述第三正投影之间，且与所述第一正投影和所述第三正投影均不重合，所述第三部分044和所述第四部分045为轻掺杂区域，导电性能增强，有利于薄膜晶体管的开态电流。
其中，通过控制缓冲层的成膜工艺，可以控制缓冲层中氢的含量，具体地，可以控制成膜工艺中，NH 3：SiH 4比例>5。
由于栅极的阻挡，有源层对应栅极的区域受氢的影响较小，可以满足半导体的开关作用；并且由于薄膜晶体管的耐压性能提升，栅绝缘层的厚度可以适当降低，比如小于300nm。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不 同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种薄膜晶体管，其特征在于，包括：
    衬底基板；
    位于所述衬底基板上的栅极；
    位于所述栅极远离所述衬底基板一侧的有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
    位于所述有源层远离所述衬底基板一侧的源极和漏极，所述源极和所述漏极分别与所述有源层连接；
    其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述栅极在所述衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠，所述栅极在所述衬底基板上的正投影与所述源极在所述衬底基板上的正投影重叠。
  3. 根据权利要求2所述的薄膜晶体管，其特征在于，
    所述有源层包括与所述漏极接触的第一部分和与所述源极接触的第二部分，所述第一部分在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影不重叠，所述第二部分在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
    所述薄膜晶体管还包括：
    附加栅极，所述附加栅极在所述衬底基板上的正投影与所述第一部分在所述衬底基板上的正投影重叠。
  4. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述有源层在所述衬底基板上的正投影落入所述栅极在所述衬底基板上的正投影内；所述有源层包括与所述漏极接触的第一部分和与所述源极接触的第二部分；
    所述薄膜晶体管还包括：
    位于所述有源层远离所述衬底基板一侧的附加栅极，所述附加栅极在所述衬底基板上的正投影与所述第一部分在所述衬底基板上的正投影重叠。
  5. 根据权利要求4所述的薄膜晶体管，其特征在于，
    所述附加栅极在所述衬底基板上的正投影落入所述栅极在所述衬底基板上的正投影内。
  6. 根据权利要求3或4所述的薄膜晶体管，其特征在于，所述附加栅极靠近所述源极一侧的第一边界与所述漏极靠近所述源极的第二边界在平行于所述衬底基板的方向上的最短距离为a1，a1大于0小于L，L为所述薄膜晶体管的沟道长度。
  7. 根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层包括与所述漏极接触的第一部分和与所述源极接触的第二部分，所述第一部分的电阻率大于所述第二部分的电阻率。
  8. 根据权利要求7所述的薄膜晶体管，其特征在于，所述第一部分的电阻率Rs满足：100MΩ/□≥Rs≥1MΩ/□。
  9. 根据权利要求7所述的薄膜晶体管，其特征在于，所述第一部分靠近所述源极一侧的第三边界与所述漏极靠近所述源极一侧的第二边界在平行于所述衬底基板的方向上的最短距离为a2，a2大于0um小于等于2um。
  10. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述有源层和所述漏极之间的导电图形，所述导电图形的电阻率大于所述漏极的电阻率，所述有源层通过所述导电图形与所述漏极电连接。
  11. 根据权利要求10所述的薄膜晶体管，其特征在于，所述导电图形的电阻率R满足：100MΩ/□≥R≥1MΩ/□。
  12. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述栅极在衬底基板上的正投影与所述源极在所述衬底基板上的正投影不重叠，所述栅极在衬底基板上的正投影与所述漏极在所述衬底基板上的正投影不重叠；
    所述栅极在所述衬底基板上的第一正投影靠近所述源极一侧的第四边界 与所述源极在所述衬底基板上的第二正投影靠近所述栅极一侧的第五边界之间的距离为a3，
    所述栅极在所述衬底基板上的第一正投影靠近所述漏极一侧的第六边界与所述漏极在所述衬底基板上的第三正投影靠近所述栅极一侧的第七边界之间的距离为a3，
    其中，a3大于0。
  13. 根据权利要求12所述的薄膜晶体管，其特征在于，a3小于2um。
  14. 根据权利要求12所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述栅极和所述衬底基板之间的缓冲层；
    所述有源层包括第三部分和第四部分，所述第三部分在所述衬底基板上的正投影位于所述第一正投影与所述第二正投影之间，且与所述第一正投影和所述第二正投影均不重合，所述第四部分在所述衬底基板上的正投影位于所述第一正投影与所述第三正投影之间，且与所述第一正投影和所述第三正投影均不重合，所述第三部分和所述第四部分为轻掺杂区域。
  15. 一种显示基板，其特征在于，包括如权利要求1-14中任一项所述的薄膜晶体管。
  16. 根据权利要求15所述的显示基板，其特征在于，包括如权利要求3所述的薄膜晶体管，在所述显示基板进行显示时，施加在所述附加栅极上的电压为5-10V。
  17. 根据权利要求15所述的显示基板，其特征在于，包括如权利要求5所述的薄膜晶体管，在所述显示基板进行显示时，施加在所述栅极上的电压为V1，施加在所述附加栅极上的电压为V1/2-V1。
  18. 一种薄膜晶体管的制作方法，其特征在于，包括：
    提供一衬底基板；
    在所述衬底基板上形成栅极；
    在所述栅极远离所述衬底基板的一侧形成有源层，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重叠；
    在所述有源层远离所述衬底基板的一侧形成源极和漏极，所述源极和所述漏极分别与所述有源层连接；
    其中，所述栅极与所述漏极之间的电阻大于所述栅极与所述源极之间的电阻。
PCT/CN2021/141591 2021-12-27 2021-12-27 薄膜晶体管及其制作方法、显示基板 WO2023122876A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/141591 WO2023122876A1 (zh) 2021-12-27 2021-12-27 薄膜晶体管及其制作方法、显示基板
CN202180004214.4A CN116670834A (zh) 2021-12-27 2021-12-27 薄膜晶体管及其制作方法、显示基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/141591 WO2023122876A1 (zh) 2021-12-27 2021-12-27 薄膜晶体管及其制作方法、显示基板

Publications (1)

Publication Number Publication Date
WO2023122876A1 true WO2023122876A1 (zh) 2023-07-06

Family

ID=86996800

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/141591 WO2023122876A1 (zh) 2021-12-27 2021-12-27 薄膜晶体管及其制作方法、显示基板

Country Status (2)

Country Link
CN (1) CN116670834A (zh)
WO (1) WO2023122876A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996019833A1 (en) * 1994-12-20 1996-06-27 Francis John Clough High voltage thin film semiconductor device
CN1321340A (zh) * 1999-08-31 2001-11-07 皇家菲利浦电子有限公司 具有漏极延伸区的横向薄膜硅绝缘体(soi)pmos器件
JP2006093684A (ja) * 2004-08-27 2006-04-06 Toshiba Corp 半導体装置及びそれを用いた光半導体リレー装置
CN1838433A (zh) * 2005-03-24 2006-09-27 三菱电机株式会社 半导体器件以及图像显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996019833A1 (en) * 1994-12-20 1996-06-27 Francis John Clough High voltage thin film semiconductor device
CN1321340A (zh) * 1999-08-31 2001-11-07 皇家菲利浦电子有限公司 具有漏极延伸区的横向薄膜硅绝缘体(soi)pmos器件
JP2006093684A (ja) * 2004-08-27 2006-04-06 Toshiba Corp 半導体装置及びそれを用いた光半導体リレー装置
CN1838433A (zh) * 2005-03-24 2006-09-27 三菱电机株式会社 半导体器件以及图像显示装置

Also Published As

Publication number Publication date
CN116670834A (zh) 2023-08-29

Similar Documents

Publication Publication Date Title
US11031419B2 (en) Array substrate, method for manufacturing the same, and display device
JP2024028628A5 (zh)
US11437411B2 (en) Thin film transistor drive backplane and micro-light emitting diode display
TWI476931B (zh) 薄膜電晶體與具有此薄膜電晶體的畫素結構
US9711544B2 (en) Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, display device
WO2015074332A1 (zh) 一种液晶显示面板
TWI497182B (zh) 顯示裝置
JP6359650B2 (ja) アレイ基板、表示装置及びアレイ基板の製作方法
US9553176B2 (en) Semiconductor device, capacitor, TFT with improved stability of the active layer and method of manufacturing the same
US10381384B2 (en) Array substrate, method for manufacturing array substrate, display panel and display device
US11587953B2 (en) Drive backplane and display panel
US20130161612A1 (en) Display device and image display system employing the same
US9515191B2 (en) Thin-film field effect transistor, driving method thereof, array substrate, display device, and electronic product
CN114019736B (zh) 显示基板和显示装置
TW201044087A (en) Pixel designs of improving the aperture ratio in an LCD
CN104733478A (zh) 一种阵列基板及其制作方法、显示装置
WO2023122876A1 (zh) 薄膜晶体管及其制作方法、显示基板
WO2023122875A1 (zh) 薄膜晶体管及其制作方法、显示基板
WO2017143660A1 (zh) 阵列基板、显示面板以及液晶显示装置
CN113433747B (zh) 阵列基板及制作方法、移动终端
CN105140298A (zh) 薄膜晶体管和阵列基板
CN113299666B (zh) 显示面板及其驱动方法、显示装置
WO2018218725A1 (zh) 显示面板
JP3203753U (ja) 表示装置
US20240234532A1 (en) Thin film transistor, manufacturing method for the same, and display substrate

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180004214.4

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 17925222

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21969263

Country of ref document: EP

Kind code of ref document: A1