CN1321282A - 具有集成电路和传输线圈的数据载体 - Google Patents
具有集成电路和传输线圈的数据载体 Download PDFInfo
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Abstract
一种数据载体(1),包括一集成电子元件(3)和一传输线圈(12),所述传输线圈(12)的短匝部分(21、22、23、24、25)是由连接线形成的,所述连接线设置在所述集成电子元件(3)的元件表面(4)的区域内的集成电子元件(3)上,所述连接线最好是由导电导轨构成。
Description
本发明涉及一种如权利要求1前序部分所述的数据载体。
本发明还涉及一种如权利要求7前序部分所述的集成电子元件。
数据载体和集成电子元件是公知的,比如,美国专利文件US5705852A中就公开了这样的数据载体和集成电子元件。可以参见该专利文件的图3所公开的实施例及其相应的描述。在该实施例中,具有n个线匝(coil turn),从垂直于元件(component)表面的方向看,其中(n-1)个线匝从位于线圈接点之间和连接接点之间的集成电路下面通过。这就可能使至少在位于线圈接点和连接接点之间的短匝部分(short tum portions)的区域内,线匝具有很窄的尺寸,线匝之间具有很小的间距。因而可能导致制造线圈的相当大的困难,也使得形成集成电子元件的线圈接点与连接接点之间的导电连接的制造相当困难,这是人们所不希望的。而且,在公知的布置方案中存在一个问题,即实践中几乎总是存在这样的情形,在集成电子元件的元件表面上与连接接点相邻还设有接点表面,比如,用于执行测试的接点表面和/或相接触界面的接点表面--这些附加的接点表面可以相对容易地使得穿过线圈接点和连接接点之间的线匝的短匝部分区域导致短路,这是一种不利的影响,在最坏的情形下会防止无错误的操作,这也是人们所不希望的。
本发明的目的是用一种简单的方式、特别是通过简单的方法来避免上述困难,以实现数据载体的改进和集成电子元件的改进。
为了实现上述目的,本发明提供的一种如权利要求1前序部分所述的数据载体具有如权利要求1特征部分所述的特征。
为了实现上述目的,本发明提供的一种如权利要求7前序部分所述的集成电子元件具有如权利要求7特征部分所述的特征。
根据本发明提供的特征,可以用一种简单的方式、特别是通过简单的方法来实现,而实际上无需增加额外的花费,即,位于连接接点之间和线圈接点之间的传输线圈的线匝的短匝部分可以具有很窄的形状并能够用很高的压缩密度来布置,而在元件表面区域能相对于附加的接点表面被精确定界,以便能够确定地避免不希望的短路危险。
根据本发明的数据载体,当具有如权利要求2所述的附加技术特征时,发现十分有利。实践中发现这样的布置很有利,因为传输线圈的主要部分的制造能够以一种简单、公知的方式来完成,并且,在传输线圈的线匝中在由连接线形成的短匝部分与长匝部分之间的导电接的制造也能以一种简单的方式来完成。
根据本发明的数据载体,当具有如权利要求3所述的附加技术特征时,发现十分有利。本发明的数据载体如此布置的优点是,可以从本质上使集成电子元件插入数据载体变得特别可靠和抗干扰插入。
根据本发明的数据载体和集成电子元件,当具有如权利要求4和8所述的附加技术特征时,发现更加有利。因而,可以用一种公知的技术来制造其连接线,同时由于能够节约成本和提高精确度而普遍受欢迎。
如上所述,根据本发明的数据载体和用于该数据载体的集成电子元件,当具有如权利要求5和9所述的附加技术特征时,发现更加有利。还发现,根据本发明的数据载体和用于该数据载体的集成电子元件,当具有如权利要求6和10所述的附加技术特征时更加有利。特别是,根据本发明的两个实施例,实践中发生的各种情形都能够以一种简单方式实现。
本发明的上述和其他方面将通过对本发明下面的实施例的描述而得到进一步说明。
下面将结合附图所示的3个实施例对本发明进行更加详细的描述,但是,本发明决不局限于此。
图1为本发明数据载体的第一实施例的放大平面图,其包括本发明第一实施例的集成电子元件。
图2为图1中圆圈Ⅱ所指的数据载体的详图,其包括本发明第一实施例的集成电子元件。
图3为从本发明第一实施例的集成电子元件的背面看的顶视图,其被嵌埋在图1和图2所示的数据载体内。
图4以与图3同样的方式示出本发明的集成电子元件的第二实施例。
图5以与图3和图4同样的方式、用较小比例示出本发明的集成电子元件的第三实施例,其形成了图5所示模块的一部分。
如图1所示,用点划线表示数据载体1。该数据载体1为一种通称为芯片卡的卡式数据载体。数据载体1包括一数据载体本体2,图1和2所示的数据载体本体2好象由一种透明材料制成。本发明的数据载体本体2用注塑成型法制成。然而,本体2也可以用多个薄片通过层叠层压法压合而成。
一集成电子元件3被嵌埋在所述数据载体1的本体2内。该集成电子元件3具有一元件表面4,在图1和图2中表面4被集成元件3所遮盖,因而是不可见的,但在图3中是可见的。集成元件3具有两个连接接点5和6,两接点在元件表面4的区域内彼此相隔一段距离。这里,两连接接点5和6是由接点表面5和6形成的,通常是焊盘。此时的接点表面5和6主要由铝及少量的附加物组成。接点凸起(contact elevvation)7、8分别与每一接点表面5和6连接。这样的接点凸起通常是一种凸块。这里,凸块7和8由金制成。或者,凸块7和8也可以用其它金属(如锡、镍或钯)或一种导电胶制成。
集成元件3还在元件表面4上设有测试接点表面9、10和11。此时,在这3个测试接点表面9、10和11上未设凸块。当然,也可以选择一种具有凸块的实施例。通过这3个测试接点表面9、10和11可以执行对集成元件3的测试程序。
如图1所示,在数据载体本体2内还嵌埋有一传输线圈12。该传输线圈12包括一第一线圈接点13和一第二线圈接点14。两线圈接点13和14彼此相隔一段距离。第一线圈接点13通过第一凸块7用电导与第一连接接点5连接。第二线圈接点14通过第二凸块8用电导与第二连接接点6连接。传输线圈12还包括线匝,比如,第一线匝15,第二线匝16,第三线匝17,第四线匝18,第五线匝19和第六线匝20。两线圈接点13和14通过这6个线匝15至20被彼此电互连。这样的传输线圈也可以设有比6个线匝更少或更多的线匝。
5个线匝15,16,17,18和19中的每一个分别包括一短线匝部分21,22,23,24和25。当从元件表面4的横向方向看时,短线匝部分21,22,23,24和25在彼此相隔一段距离的两线圈接点13和14之间及彼此相隔一段距离的两连接接点5和6之间延伸。而且,6个线匝15,16,17,18、19和20中的每一个分别包括一长线匝部分26,27,28,29、30和31。此时,长线匝部分26至31与两线圈接点13和14被用一种蚀刻法制成的,但是它们也可以用一种丝网印刷法制成。印刷电路技术方面的其它已知方法也可以用来形成传输线圈12的长匝部分26至31、线匝15至20及线圈接点13和14。线匝15至20的长匝部分26至31在它们长度方向的主要部分上具有一恒定、相对较大的宽度B,在图1中是可见的。长匝部分26至31仅仅在邻近集成元件3的区域变窄,而具有一相对较小的宽度b,在图1中可见,尤其参见图2。
第一长匝部分26通过电导其一端与第一线圈接点13连接,而另一端与第一短匝部分21连接。第二长匝部分27的一端与第一短匝部分21连接,而另一端与第二短匝部分22连接。第三长匝部分28通过电导其一端与第二短匝部分22连接,而另一端与第三短匝部分23连接。第四长匝部分29通过电导其一端与第三短匝部分23连接,而另一端与第四短匝部分24连接。第五长匝部分30通过电导其一端与第四短匝部分24连接,而另一端与第五短匝部分25连接。第六长匝部分30通过电导其一端与第五短匝部分25连接,而另一端与第二线圈接点14连接。
在图1和2所示的数据载体1中以及在数据载体1的集成电子元件3中,布置在两线圈接点13和14之间和两连接接点5和6之间的传输线圈12的短匝部分21、22、23、24和25,被通过连接线21、22、23、24和25以一种特别有利的方式而形成,而连接线21、22、23、24和25被设置在集成元件3的元件表面4上。这里,每一连接线21至25均由一种用集成电路技术制造的导电导轨形成。在此情形下,作为连接线21至25的所有5个导电导轨沿一倾斜路径延伸。这样的好处是可以获得有利的空间。
需要注意的是,如图1和2所示,长匝部分26至31被全部嵌埋在数据载体1的主要部分数据载体本体2内,长匝部分26至31包括端点32、33、34、35、36,37、38、39、40和41,这些端点的朝向集成电路3一侧的那部分未被嵌埋在数据载体本体2内,而长匝部分26至31的端点32至41用电导与连接线21、22、23、24和25的线端42、43、44、45、46,47、48、49、50和51连接。为了保持图2的清晰,位于集成电路3下面的长匝部分26至31的端点32至41被用虚线表示。同样,在图2中,两线圈接点13和14的位于集成电路3下面的那部分也用虚线表示。在图3中,仅仅表示出图1和图2所示数据载体的集成元件3,其中,两线圈接点13和14以及长匝部分均用点线只示出一部分。均由导电导轨构成的短匝部分21至25,比如连接线21至25在它们线端42至51的区域内被分别与凸块接点52、53、54、55、56,57、58、59、60和61连接,目的是为了在长匝部分26至31与短匝部分21至25之间建立导电连接。
从图3可以清楚看到,在集成元件3的两连接接点5和6之间以及在两线圈接点13和14之间,线匝15至20的短匝部分21至25被以高压缩密度布置,它们在元件表面4上彼此相对准确定界,并相对于附加设置的测试接点表面9、10和11准确定界。因此,用一种简单的方式,就可靠地防止了在短匝部分21至25区域内引起的不希望的短路危险。
如图4所示的集成电子元件3大体上具有与图3所示的集成电子元件3相同的结构,但是,在图4所示的集成电子元件3中,作为连接线21至25比如短匝部分21至25的所有导电导轨都是沿直线路径延伸。
图5示出一种被嵌埋在数据载体1中的模块62。在图5中,数据载体1用点划线表示。模块62包括一作为一元件的集成电子元件3,该集成电子元件3实质上与图4所示的集成电子元件3相似,与图4所示的集成电子元件3不同之处仅仅在于连接线21、22、23、24和25以及连接接点5和6没有凸块。
模块62还包括一元件载体63。该元件载体63具有一载体表面64,在载体表面64上设置集成电子元件3。在载体表面64上通过接点表面设置有中间接点65、66、67、68、69、70、71、72、73、74、75和76,其中的中间接点66至75被用电导分别与长匝部分26、27、28、29和30的各个端点32、33、34、35、36,37、38、39、40和41连接,又分别与连接线21、22、23、24和25的各个线端42、43、44、45、46,47、48、49、50和51连接。这里,导电连接是由各自的焊线77、78、79、80、81、82、83、84、85和86分别形成的。需要注意的是,用电导与第一线圈接点13连接的中间接点65,被用电导通过另一焊线87与第一连接接点5连接。用电导与第二线圈接点14连接的中间接点76,被用电导通过另一焊线88与第二连接接点6连接。最后需要注意的是,此时,中间接点65至76各自分别设有一凸块89、90、91、92、93、94、95、96、97、98、99和100。这些中间接点65至76更通常的是不设凸块。
而且,在载体表面64上还有3个中间接点101、102和103,其每一中间接点由一接点表面形成。这里,中间接点101被通过另一焊线104与集成元件3的测试接点表面9连接。中间接点102被通过另一焊线105与集成元件3的测试接点表面10连接。中间接点103被通过另一焊线106与集成元件3的测试接点表面11连接。
图4和图5所示的实施例可带来与图1和图2所示的数据载体及其集成电子元件3相同的优点。
Claims (10)
1.一种数据载体(1),具有一载体本体(2),在所述载体本体(2)内嵌埋有一集成电子元件(3),所述元件包括一元件表面(4),在所述元件表面(4)的区域内设有两个连接接点(5,6),所述连接接点(5,6)彼此相隔一段距离;以及
在所述载体本体(2)内还嵌埋有一传输线圈(12),所述线圈包括两个线圈接点(13,14),所述线圈接点(13,14)彼此相隔一段距离并被用电导与所述连接接点(5,6)连接,所述线圈还包括线匝(15、16、17、18、19、20),所述线匝与所述两线圈接点(13,14)电连接,所述线匝还包括短匝部分(21、22、23、24、25),从垂直于元件表面(4)的方向看,所述短匝部分在彼此相隔一段距离的两线圈接点(13,14)之间以及彼此相隔一段距离的两连接接点(5,6)之间延伸,所述线匝还包括长匝部分(26,27,28,29、30、31),所述每一长匝部分被用电导与至少一个短匝部分(21、22、23、24、25)连接,其特征在于:
所述传输线圈(12)的在两线圈接点(13,14)之间及两连接接点(5,6)之间延伸的所述短匝部分(21、22、23、24、25),是由连接线(21、22、23、24、25)形成的,这些连接线设置在所述集成电子元件(3)的元件表面(4)的区域内。
2.根据权利要求1所述的数据载体(1),其特征在于:所述长匝部分(26,27,28,29、30、31)被全部嵌埋在所述载体本体(2)内;所述长匝部分(26,27,28,29、30、31)具有端点(32、33、34、35、36,37、38、39、40、41),这些端点至少部分未被嵌埋在所述载体本体(2)内;所述长匝部分(26,27,28,29、30、31)的端点(32、33、34、35、36,37、38、39、40、41)被用电导与连接线(21、22、23、24、25)的线端(42、43、44、45、46,47、48、49、50、51)连接。
3.根据权利要求1所述的数据载体(1),其特征在于:所述集成电子元件(3)形成一模块(62)的一部分,所述模块(62)被嵌埋在所述数据载体(1)内并包括一元件载体(63),所述元件载体(63)包括一载体表面(64),在所述载体表面(64)上设置所述集成电子元件(3)及中间接点(66、67、68、69、70、71、72、73、74、75),所述每一中间接点与一长匝部分(26,27,28,29、30、31)的一个端点(32、33、34、35、36,37、38、39、40、41)以及一连接线(21、22、23、24、25)的一个线端(42、43、44、45、46,47、48、49、50、51)连接。
4.根据权利要求1所述的数据载体(1),其特征在于:所述每一连接线(21、22、23、24、25)是由集成电路技术所制造的一导电导轨而形成的。
5.根据权利要求4所述的数据载体(1),其特征在于:所述作为连接线(21、22、23、24、25)的所有导电导轨都是沿直线路径布置的。
6.根据权利要求4所述的数据载体(1),其特征在于:所述作为连接线(21、22、23、24、25)的至少一部分导电导轨是沿一成角度的路径布置的。
7.一种集成电子元件(3),包括一元件表面(4),在所述元件表面(4)的区域内设有两个连接接点(5,6),设置所述连接接点以便与一传输线圈(12)的两个线圈接点(13,14)电连接,以及
在所述数据载体(1)内设置载体本体(2),以及在所述载体本体(2)内嵌埋一传输线圈(12),所述线圈包括彼此相隔一段距离的两个线圈接点(13,14),所述线圈还包括与所述两线圈接点(13,14)电连接的线匝(15、16、17、18、19、20),所述线匝包括短匝部分(21、22、23、24、25),从垂直于元件表面(4)的方向看,所述短匝部分在彼此相隔一段距离的两连接接点(5,6)之间延伸,所述线匝还包括长匝部分(26,27,28,29、30、31),所述每一长匝部分被用电导与至少一个短匝部分(21、22、23、24、25)连接,其特征在于:
在所述集成电子元件(3)的元件表面(4)的区域内设置连接线(21、22、23、24、25),这些连接线是作为所述传输线圈(12)的线匝(15、16、17、18、19)的短匝部分(21、22、23、24、25)而设计的。
8.根据权利要求7所述的集成电子元件(3),其特征在于:所述每一连接线(21、22、23、24、25)是由集成电路技术所制造的一导电导轨而形成的。
9.根据权利要求8所述的集成电子元件(3),其特征在于:所述作为连接线(21、22、23、24、25)的所有导电导轨都是沿直线路径布置的。
10.根据权利要求8所述的集成电子元件(3),其特征在于:所述作为连接线(21、22、23、24、25)的至少一部分导电导轨是沿一成角度的路径布置的。
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FR2872945B1 (fr) * | 2004-07-07 | 2007-01-12 | Oberthur Card Syst Sa | Entite electronique comportant une antenne, inlay et module pour une telle entite |
JP5874181B2 (ja) * | 2011-03-14 | 2016-03-02 | 株式会社村田製作所 | コイルモジュールおよび非接触電力伝送システム |
JP2013229937A (ja) * | 2013-07-26 | 2013-11-07 | Dainippon Printing Co Ltd | ブースターアンテナ基板 |
CN104377439B (zh) | 2013-08-15 | 2019-08-27 | 德昌电机(深圳)有限公司 | 天线电路及制造方法 |
US11916405B2 (en) * | 2019-01-02 | 2024-02-27 | Ge Hybrid Technologies, Llc | Wireless power transmission apparatus with multiple controllers |
JP2022552923A (ja) | 2019-05-21 | 2022-12-21 | ゼネラル・エレクトリック・カンパニイ | 複数の一次コイルおよび隣接コイルミューティングを備えたワイヤレス送電装置 |
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ATE383621T1 (de) | 2008-01-15 |
KR20010089362A (ko) | 2001-10-06 |
EP1125247A1 (en) | 2001-08-22 |
JP2003508833A (ja) | 2003-03-04 |
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US6552422B1 (en) | 2003-04-22 |
KR100762530B1 (ko) | 2007-10-01 |
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