CN1309038C - 高密度区域阵列焊料微接合互连结构及制造方法 - Google Patents

高密度区域阵列焊料微接合互连结构及制造方法 Download PDF

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CN1309038C
CN1309038C CNB028260872A CN02826087A CN1309038C CN 1309038 C CN1309038 C CN 1309038C CN B028260872 A CNB028260872 A CN B028260872A CN 02826087 A CN02826087 A CN 02826087A CN 1309038 C CN1309038 C CN 1309038C
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little
carrier
layer
chip
lining
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CN1608316A (zh
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约翰·哈罗德·梅格莱因
凯文·肖恩·彼得拉尔卡
桑帕斯·普鲁肖坦
卡洛斯·胡安·桑布切蒂
理查德·保罗·福兰
乔治·弗雷德里克·沃克
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Ultratech Corp
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International Business Machines Corp
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Abstract

本发明教导了一种用于通过布置在互连载体上的微接合阵列互连一系列器件芯片的系统。载体上安置有微接合容座的密集阵列，该容座具有附着层、阻挡层和贵金属层；器件晶片上制造有微接合焊垫阵列，该焊垫包括附着层、阻挡层和可熔焊料层，且定位在与阻挡容座相匹配的位置；所述器件芯片通过微接合阵列连接于所述载体，形成了可实现非常高的输入/输出密度和芯片内部布线密度的互连。

Description

高密度区域阵列焊料
微接合互连结构及制造方法
技术领域
本发明属于微电子领域，更特别地属于制造和互连通常称作“芯片”的极小半导体器件的领域。
背景技术
在过去二十年里，硅晶体管技术中集成度的提高推动了用于计算、通信和微控制应用的硅芯片所使用的电路从大规模集成(LSI)到很大规模集成(VLSI)以及现在的超大规模集成(ULSI)电路的转变。这些高集成硅芯片的最佳利用要求对支持器件例如存储芯片进行更高空间效率的封装。进一步，随着移动通信器件、手提管理器(organizer)和计算器件的出现，也促进了将这些不同的功能集成在单个的小型系统内。这反过来推动了微电子工业向着片上系统(SOC)方法发展。
简而言之，片上系统方法试图在同一个硅芯片上集成许多不同的器件功能，从而单个大芯片能够向终端用户提供各种功能。尽管在概念上非常诱人，但是由于多种原因使得这种方法在实践中令人沮丧。第一，不同微电子器件(例如存储芯片、逻辑芯片、无线通信芯片等)最佳的材料、制造处理和特征尺寸彼此迥异。将它们都组合在同一个芯片上意味着要进行妥协，这会限制SOC中每一个器件块(deviceblocks)可实现的性能。第二，大量功能块的集成需要大的芯片尺寸，并在芯片上构建许多层布线。这两个因素都趋向于降低产量和增加每个芯片的成本，这是人们不期望的。第三，人们必须设计和构建的每一个整体功能组合(例如存储和微处理器，无线通信和微处理器等)，导致各种芯片部件数目和产品混合(product mix)，这不利于低成本制造。最后，用于在单个SOC上组合不同系列的材料、处理和集成方案所需的专门技能在单个企业内经常不能够获得，而这些是当前不同微电子行业的一部分。
SOC的一个诱人的备选方案是封装上系统(system-on-a-package)或者SOP，其中在第一级封装载体(first levelpackaging carrier)上组合了大量的芯片，每一个芯片都优化了其独特的功能并且可能在不同的专业用于制造该特殊芯片的工厂中制造，第一级封装载体连接这些芯片并允许最终的封装发挥单一系统的功能。这种封装中所需的互连水平和输入-输出(I/O)密度预期远远地大于目前在印刷电路板或者多层陶瓷技术中可获得的水平。因为人们期望这种在上面组装了芯片的SOP载体代替SOC，所以有理由预期互连和I/O的密度应当介于芯片上线路远后端(far back end of theline，FBEOL)互连水平所使用的密度(典型地布线和通道(via)处于500nm-1000nm的间距)和最激进(aggressive)的封装基片所使用的密度(典型地布线和通道处于10,000-20,000nm的间距)之间。如果载体本身用硅制造，则在SOP载体所需的布线尺寸和间距上扩展FBEOL处理是切实可行的。此外，但是，载体需要支持高I/O密度以便互连安装在它上面的各种器件芯片。系统的间隔尺寸越大，也就是说，系统分割成亚单元或者芯片越精细，所需的I/O数目越大。可以预料，这种I/O密度必然需要尺寸和空间等级为5-10μm的键合焊垫(bonding pad)，这处于目前典型封装I/O焊垫可能的范围之外，目前典型封装I/O焊垫的尺寸和空间至少要粗糙10-20倍。
因此，人们高度期望实现一种微接合(microjoining)结构，其能够将多个芯片互连到封装上系统载体上从而获得比目前的技术状况显著提高的芯片间输入/输出密度。
因此，本发明的主要目的是使超高密度互连成为可能，推动超大规模集成电路芯片(逻辑、微处理器、存储器、网络开关)的使用。目前的倒装(flip)晶片焊接技术只能够实现大约150μm中心上的75mm焊垫。我们的方法能够获得比这一水平高达1000倍或者更多的极高密度。这通过独特的处理流程加以实现，其在制造接触焊垫时不需要任何特殊的光刻步骤并且在线路后端(BEOL)互连水平上使用这些器件芯片的精细特征。
发明内容
本发明提出了一种结构，其由器件部件(半导体芯片、光学器件例如激光器、离散或集成无源部件等)与载体之间互连的精细间距阵列(小至5μm上的2.5μm焊垫)构成，器件部件也称作小芯片(chiplet)，载体容纳这些部件中的一个或多个。载体能够是硅、陶瓷或者有机基片，但最优选的用硅制造以便获得最高的互连密度。器件侧上的接合冶金(joining metallurgy)包括附着层、焊料反应阻挡层和可熔焊料接合球。载体侧上的匹配接触焊垫有意地做得比器件侧上的更大，并且包括附着层、焊料反应阻挡层和贵金属保护/焊料润湿层。选择地，所述较大的接触焊垫能够是器件顶层的一部分，并且如果期望的话在载体上集成可熔焊料承受结构。
本发明提供一种微接合互连结构，包括：
(a)载体，其具有用于连接器件部件的互连阵列，包括：Si、陶瓷或有机物的基片，在其上形成的并通过开口暴露布线层的电介质膜，和所述开口内的微接合容座，其从底部到顶部包括衬层、籽晶层、阻挡层和贵金属层，这些层衬装在所述容座的内表面；以及
(b)芯片，其在器件侧上具有微接合焊垫，其从底部到顶部包括衬层、籽晶层、阻挡层和接合金属并与载体侧上的所述微接合容座相匹配；
其特征在于，阻挡层和贵金属层只镀在籽晶层上而不镀在衬层上，从而开口中的所述载体的衬层、籽晶层的暴露部分与电介质膜表面共平面。
根据上述的微接合互连结构，其中衬层材料从包括Ta、TaN、Ti、TiN、W、WN、Cr及其组合的组中选择。
根据上述的微接合互连结构，其中衬层厚度为5nm-120nm。
根据上述的微接合互连结构，其中籽晶层材料是厚度为30-200nm的铜。
根据上述的微接合互连结构，其中阻挡层材料从包括Ni、Co、Pt、Pd及其合金或组合的组中选择。
根据上述的微接合互连结构，其中阻挡层的厚度为100-1000nm。
根据上述的微接合互连结构，其中所述载体的开口具有比所述芯片焊垫更大的尺寸。
本发明提供一种用于将在器件芯片上形成的一系列微接合焊垫连接到在互连载体上形成的微接合容座阵列的工艺，包括如下步骤：
提供载体结构，其包括：Si、陶瓷或有机物的基片，在其上形成的并通过开口暴露布线层的电介质膜；
在该结构上连续沉积衬层和籽晶层；
对该结构进行化学机械抛光，从而使开口中所述载体的衬层和籽晶层的暴露部分与衬层顶表面共平面；
通过电镀连续沉积阻挡层和贵金属层，这些层衬装在所述开口内所述容座的内表面，基本上与电介质膜表面共平面；
提供芯片，其具有包括器件侧上的焊料球的微接合焊垫，与载体结构侧上的所述微接合容座相匹配；
组装该载体结构和该芯片，从而保证微接合焊垫适当地定位在微接合容座内；以及
对组装后的该载体结构和芯片进行焊料回流以便将该微接合焊垫连接到微接合容座上，从而能够实现安装在载体上的器件芯片之间的互连。
根据上述的工艺，其中所述载体结构的开口具有比所述芯片的微接合焊垫更大的尺寸。
本发明前述的和进一步的目的和优点从下面联系附图的优选实施例详细解释中将更加显而易见。
附图简述
图1是器件小芯片在沉积了TaN-Ta、Cu、Ni和接合金属之后的剖面图。
图2是载体晶片在沉积了TaN-Ta、Cu、Ni和贵金属之后的剖面图。
图3是准备接合到成品器件小芯片(底部)上的成品载体(顶部)的剖面图。
优选实施例说明
现在参考附图，首先根据器件小芯片10说明用于制造和组装互连的优选方法的细节：
小芯片处理
现在参考附图，小芯片处理从制造硅器件小芯片晶片12开始，历经半导体器件和底部布线层13和顶部金属布线层级14，施加最终的钝化电介质堆叠16，和终端焊垫通道(TV)的开口19。TV通道开口19的宽度能够小到2.5微米，而钝化层的厚度为大约1微米或小于1微米。然后执行如下步骤：通过溅射或其它真空沉积方法沉积衬层(liner layer)15，其典型地包含大约40nm的氮化钽(TaN)和40nm的钽(Ta)以及籽晶层17，籽晶层包含大约100nm或者更多的真空沉积铜。其它能够使用的衬垫材料包括Ti、TiN、W、WN和Cr等。然后对晶片进行化学-机械抛光(CMP)从而将铜从晶片顶表面上抛掉，终止于Ta表面。这产生了如图1所示的结构，其中铜籽晶17仅保留在TV开口19的顶部和侧壁。电镀大约500nm厚的阻挡层20，其能够是Ni、Co、Pt、Pd等，之后是接合金属层22，其是可熔焊料，例如97％Pb 3％Sn合金、Au-Sn合金或者其它焊料，这取决于所期望的应用和焊接等级。基于Sn的无Pb焊料及其合金也可以用于层22。焊料层厚度能够在2微米到100微米之间选择，这取决于焊料合金和应用需要。需要注意的关键特征是，层20和22仅电镀在存在于TV开口19内的Cu上，而不电镀在存在于晶片顶部的衬层15上。衬层15仅用作电极，在处理中输送电镀电流。随后通过干式等离子体或湿式化学腐蚀从接触焊垫之间的小芯片顶表面区域上除去层15，只在小芯片焊垫结构(底部)的TV通道底部和侧壁上留下剩余的TaN Ta层15’，如图3所示。
载体处理(对于硅载体)：
为处理为在小芯片上制造的焊料微接合提供了匹配连接。载体晶片30包括Si、陶瓷或有机物的基片32，载体晶片30通过最终的互连布线34、沉积最终的钝化堆叠36和TV开口38加以制造。载体上TV通道的尺寸大于小芯片上微接合焊料焊垫的标称尺寸，以便保证微接合能够通过容座(receptacle)合适地置于载体内。
随后对于载体晶片的处理流程具有如下的步骤：通过溅射或其它真空沉积方法沉积衬层(liner layer)39，其典型地由大约40nm的氮化钽(TaN)和40nm的钽(Ta)以及籽晶层40构成，其中籽晶层由大约100nm的真空沉积铜构成。然后对晶片进行化学-机械抛光(CMP)从而将铜从晶片顶表面上抛掉，终止于Ta表面。这在载体上形成了如图2所示的结构，其中铜籽晶40仅保留在TV开口38的底部和侧壁。电镀大约500nm厚的阻挡层41，其能够是Ni、Co、Pt、Pd等，之后是贵金属层22，其优选的是厚度范围为100-1000nm的金。需要注意的关键特征是，层41和42仅电镀在存在于TV开口38内的Cu上，而不电镀在位于载体晶片顶表面的衬层上。衬层39仅用作电极，在处理中输送电镀电流。随后通过干等离子体或湿化学腐蚀从焊垫之间的顶表面区域上除去层39，只在如图3所示载体焊垫结构(顶部)的TV通道底部和侧壁上留下残余的TaN Ta层39。其它用于施加阻挡层41和贵金属层42的方法包括非电镀沉积。非电镀沉积Ni、Co、Pd以及贵金属Au在技术上是已知的并且能够用于代替电镀。如果认为薄金(大约80-120nm)已经足够，那么非电镀Au和浸入的Au是特别适合的。载体的最终特征是用于接收在小芯片上制造的微接合的容座44。
组装处理(及最终结构)
组装包括用类似于常规倒装晶片组装(分离光学和/或电容对准)的方式取放小芯片，并且进行回流接合。无熔接剂的氢回流可能是优选的，因为小芯片与载体之间的间隙太小以致于不能进行有效的熔接剂清洗。
现在已经显见，本公开发明与先前技术相比进一步的主要优点如下：微接合方案允许区域阵列安装非常小的器件例如激光器、微传感器或者驱动器。这些器件能够小到100μm×100μm或者更小，以致于小到不能用标准的倒装芯片接触安装。PbSn焊料的使用允许可重复使用的(reworkable)连接，其用于替换器件芯片以便进行升级或修复。具有这些微接合焊垫的器件能够用任何传统的临时器件附着结构为已知良好器件加以检测、老化(burn in)和分类。因此，尽管互连的间距精细，但是获得已知良好的单元片(die)不成问题。
这样，通过特别参考本发明的优选形式对本发明进行说明，显而易见，可以对其进行各种改变和修饰而不背离由附加权利要求限定的本发明的精神和范围。

Claims (9)

1.一种微接合互连结构，包括：
(c)载体(30)，其具有用于连接器件部件的互连阵列，包括：Si、陶瓷或有机物的基片(32)，在其上形成的并通过开口(38)暴露布线层(34)的电介质膜(36)，和所述开口内的微接合容座，其从底部到顶部包括衬层(39)、籽晶层(40)、阻挡层(41)和贵金属层(42)，这些层衬装在所述容座的内表面；以及
(d)芯片，其在器件侧上具有微接合焊垫，其从底部到顶部包括衬层、籽晶层、阻挡层和接合金属并与载体侧上的所述微接合容座相匹配；
其特征在于，阻挡层和贵金属层只镀在籽晶层上而不镀在衬层上，从而开口中的所述载体的衬层、籽晶层的暴露部分与电介质膜表面共平面。
2.根据权利要求1的微接合互连结构，其中衬层材料从包括Ta、TaN、Ti、TiN、W、WN、Cr及其组合的组中选择。
3.根据权利要求2的微接合互连结构，其中衬层厚度为5nm-120nm。
4.根据权利要求2的微接合互连结构，其中籽晶层材料是厚度为30-200nm的铜。
5.根据权利要求2的微接合互连结构，其中阻挡层材料从包括Ni、Co、Pt、Pd及其合金或组合的组中选择。
6.根据权利要求5的微接合互连结构，其中阻挡层的厚度为100-1000nm。
7.根据任何上述权利要求的微接合互连结构，其中所述载体的开口具有比所述芯片焊垫更大的尺寸。
8.一种用于将在器件芯片上形成的一系列微接合焊垫连接到在互连载体上形成的微接合容座阵列的工艺，包括如下步骤：
提供载体结构(30)，其包括：Si、陶瓷或有机物的基片(32)，在其上形成的并通过开口(38)暴露布线层(34)的电介质膜(36)；
在该结构上连续沉积衬层(39)和籽晶层(40)；
对该结构进行化学机械抛光，从而使开口中所述载体的衬层和籽晶层的暴露部分与衬层顶表面共平面；
通过电镀连续沉积阻挡层(41)和贵金属层(42)，这些层衬装在所述开口内所述容座的内表面，基本上与电介质膜表面共平面；
提供芯片，其具有包括器件侧上的焊料球的微接合焊垫，与载体结构侧上的所述微接合容座相匹配；
组装该载体结构和该芯片，从而保证微接合焊垫适当地定位在微接合容座内；以及
对组装后的该载体结构和芯片进行焊料回流以便将该微接合焊垫连接到微接合容座上，从而能够实现安装在载体上的器件芯片之间的互连。
9.根据权利要求8的工艺，其中所述载体结构的开口具有比所述芯片的微接合焊垫更大的尺寸。
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