TWI222712B - High density area array solder microjoining interconnect structure and fabrication method - Google Patents

High density area array solder microjoining interconnect structure and fabrication method Download PDF

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Publication number
TWI222712B
TWI222712B TW092100860A TW92100860A TWI222712B TW I222712 B TWI222712 B TW I222712B TW 092100860 A TW092100860 A TW 092100860A TW 92100860 A TW92100860 A TW 92100860A TW I222712 B TWI222712 B TW I222712B
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Taiwan
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layer
micro
junction
patent application
slide
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TW092100860A
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TW200302553A (en
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John Harold Magerlein
Kevin Shawn Petrarca
Carlos Juan Sambucetti
Sampath Purushothaman
Richard Paul Volant
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Ibm
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

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Description

件 元 體 導 半 小 極 在 是 別 特 ]， 0 域域聯 領領互 術子及 技電造 之微製 屬於的 所屬f) 明明片 發發晶 、本稱 \ 通 1222712 财 4· __案號92100860 _日 修正_ 五、發明說明（1) 相關的發明 和此一發明相關的還有數個發明，都已經委託給同一 法律事務所，包括一同申請專利的發明Y〇R92〇〇1〇249US1 及YOR920010217US1 。 二、【先前技術】 隨著這二十年來矽電晶體科技的積體化水準越來越 高’計算、通訊及微自動控制所使用的晶片都已經從大型 積體電路（LSI)進步到超大型積體電路（VLSI)，而目前正 向極大型積體電路（ULSI)前進。當這些高度積體化矽晶片 和其他搭配元件例如記憶體要完全發揮功能時，需要比目 前更加節省空間的包裝。此外，隨著行動通訊裝置、電子 掌上萬用手冊（hand held organizers )及掌上電腦的問 世政電子工業一直期望能夠以系統單晶片（373七6111-011- a-chip，S0C)的方式，將這些功能整合在一個小巧的系統 上。 間單而言，系統單晶片就是在同一個石夕晶片上，盡量 整合入各種不同元件的功能，則一高度整合的晶片直接提 供用戶多種功能。雖然概念上看來相當的吸引人，卻有好
1222712 9a 4· 26 月 曰
第一， 通訊晶 ，為了 早晶片 合大量 要更多 成本， 計製造 起，生 造、整 公司通 t號 921008fin 五、發明說明（2) 幾個因素令人望之卻步。 體晶片、邏輯晶片、無線 程、元件尺寸都各自不同 個晶片上，折衷之後系統 到限制。第二，為了要整 跟著增加，而且晶片也需 生產上會降低良率和增加 二，生產者必須要一一設 多種不同的元件混雜在一 後，目前不同的材料、製 中不同的公司掌握，單一 同的專門技術。 各種微電子元件（如記憮 片等等）的最佳材料、製 要把這些元件整合在同一 上各個功能的表現都备為 的功能，晶片的面積二; 層的佈線（wiring )，在 都不是業界所樂見的。第 每一個功能，晶片上會有 產的成本將難以壓低。最 合技術分別由微電子工業 常難以同時掌握這麼多^ <相/對的，只要求整個系統整合在同一個晶片封裝内 六間稱每系統早封裝，system-〇n-a — package，s〇p)，就比較 谷易貫現了。系統中的各個晶片都能分別最佳化，甚至分 別，I同的專屬工廠製造，在第一層封裝載片（carrier^ ^組合彳^ 1接上彼此的連線就能封裝成具有完整功能的系 統在這樣封裝中，互聯層與輸入/輸出密度必須遠大於 印刷電路板或多層陶瓷科技（multilayer logles )能達到的。為了要能夠取代系統單晶片， 系統單封裝的互聯與輪入/輸出密度需要接近遠後段製程 (far back end of the iine，FBE〇L)互聯層（約 50 0 - 1，〇〇〇 nm節距” pi tch”的佈線與中介窗” via”）和包裝基板
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案號 92100860 五、發明說明（3) (約1 0，0 0 0 - 2 0，0 〇 〇 nm節距的佈線與中介窗）的性& SOP載片由矽製成，在載片所需要的佈線大小與節若 連線遠後端的製程可以延伸。此外，载片必須'At p ’ 入/輸出岔度，以互聯其上不同的元件晶片。鬲輪 碎，分為越多子單元或晶片，就會需要越多的輸出 入。據估計，這樣的輸入/輸出密度將會限制連線接點 (bondi ng pad)在5到1 0 # m的的大小與空間。鈇而 至少大上10到20倍的一般封裝輸入/輪出接點，”根目前 辦法滿足這樣的要求。 又有 為了要在系統單封裝上製造遠高於目前技術水準 :/輸出密纟，希望發展載片上的微接合結構以互聯數:輪 Η日 /"7 本么月要目的就疋達到ULSI晶片（包括邏輟 電路、微處理器、記憶體、絪玫 匕輯 聯。目刖的覆晶片焊接技術（fli 互 ,u , v11XP chip solder technology)只能在ι5〇 ψ
Et。*政口口 π 土 , μ m中心製作出75 μ m大小的接 點 本發明可以達到高逵1 〇 η η位、 J接 作接點時不需要特別的微：：上的密度。0為利用製 後段製程（back en“ ：'步驟的獨特流程，以及利用 微結構。 the Une)互聯層元件晶片的細 【發明内容】
1222712 修正
i號921_κη__年财t 26日 五、發明說明（4) 9 所提出的結構包含以下兩個部分。一 (chiplet )的元件成份（devi +、，片 導體晶片，例如雷射的光學元件\〇mP〇nent)(可為半 笙笙、夕門从从件，分離或積體的被動元件 :.寻）之：的精細節距互聯陣列（節距小至在5…心： :二I:.,。一為載有一或多個上述成份的載片。
Uii有機基板都可以作為載片，其中又以矽可達到 最尚互聯密度。元件側的接合材料包含一黏著 反應阻障層及一顆可熔焊材接合小球。 材 積的對應接點，包含一黏著戶、Μ 、 較大面 χ ° s 勒考屬一焊材反應阻障層及一眚 金屬保護/焊材滋潤層。而在需要的情況下，也可以將接、 點作為元件的表層，而改將可熔焊材承受結構（“訂4 structure )製作在載片上。 、接下來將配合附圖，仔細的說明本發明適合的實作方 法，同時本發明的優點及更進一步的目標也會加以介紹。 四、【實施方式】 藉著附圖的說明，這裡將詳細介紹本發明所提出互聯 結構的製作及組合方法，由元件所在的晶片〗〇開始： 晶片製程： 參考圖式’在石夕元件晶片晶圓12上製作半導體元件及 底層佈線1 3與上方金屬佈線層1 4，最後介質保護層1 6，以 及接點（terminal pad via，TV)開孔（opening ) 1 9。接
第10頁 1222712 9¾ 4. 26 案號92100860_年 月 日 五、發明說明（5) 點開孔1 9可以小到只有2 · 5 /Z m寬，而保護層厚度約i v m或 更小。晶片製程按照以下的步驟執行。以濺鍍或其他真空 方式/儿積襯墊層1 5，襯墊層1 5由約4 〇 〇 A的氮化|旦 (tantalum nitride，TaN)及 4〇〇 A 的钽（Tantalum，
Ta )組成，其他像是鈦（τ丨）、氮化鈦（τ丨N )、鎢 (W)、氮化鎢（WN)或鉻（Cr)也可以作為襯墊層的材 料。接著再沉積約1 000 A或更厚的銅作為種晶層17。接下 來以化學機械研磨（CMP)的方式，將表面不要的銅去除但 留下鈕襯墊層。如此形成如圖一的結構，只有接點開孔19 底部及兩側的銅1 7被留下。再以電鍍的方式製作一層約 5*0 0 0 A巧阻障層2 〇，可用的材料包括鎳、鈷、鉑、鈀等 等。接著是接合金屬層22，為可熔焊材，如97%鉛3%錫合 金、金-錫合金，或視所需用途與焊材而定。不含鉛的錫 ，焊材或其合金亦可用於接合金屬層22。焊材層的厚度隨 者不同的材料及環境大約在2 到1〇〇 左右。此製程最 =的，色在於20和22兩層只附著在接點開孔19的銅上，不 曰附著在日日圓上方的襯塾層。襯塾層
鍍電流。稍後可以電聚乾㈣或化學濕K ’ /，除曰日片上表面接點間的襯墊層1 5而殘留氮化鈕_ =^ 15，。如圖三下方所示，在晶片上只留下接點開孔下 万及兩側的部分。 載片製程（以矽載片為例） 本製程提供用以連接晶片上焊材微接合（s〇ider )的結構。載片晶在製備時，已經製作了
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接著按照以下的步驟執行。以濺鍍或其他真空方 積襯墊層39，襯墊層由約40 0 A氮化鈕及4〇〇 a钽組成' = 著再真空沉積約1 0 00 A或更厚的銅作為種晶層4〇。接， 化學機械研磨（CMP)晶圓，將表面不要的銅去除，並停來 鈕層表面。則在載片上形成如圖二的結構，只有接點 38底部及兩側的銅4〇才被留下來。再以電鍍的方式製^ 層約50 0 0 A的阻障層41，可用的材料包括鎳、鈷、^^ 等等。接著是貴金屬層42，以10 〇〇 A到1 0000 A的金較為 適合。此製程最大的特色在於41和42兩層只附著在接點’、、、 孔38的銅上，不會附著在晶圓上方的襯墊層39。襯墊凡2 純粹只是用來導通製程中的電鍍電流。稍後可以.電滎^ 刻或化學濕餘刻的方式，去除表面上接點間的襯墊層^鬼 而殘留氮化钽-鈕層39，如圖三上方所示，在晶片上胃只留。 下接點開孔下方及兩侧的部分。阻障層4丨和貴金屬層4 2 可以無電沉積（electroless deposition)方式製作。也 電沉積鎳、姑、把與貴金屬金為習知技術，且可用以取g 電鏟。如果認為薄的金（80 0 A到1 2 00 A )就足夠，無電 鍍（electroless plating)及浸泡附著法（immersi、〇n) 尤其適合。隶後在載片上形成供與晶片微接合組合的座 44 〇 ' I 1 1 I 1 S I 麵 ί 1 第12頁 1222712 案號 92100860 9¾ 4. 26 年月曰 修正
第13頁 1222712 案號 921008fU) 五、發明說明（8) r： 2e 曰 修正 組合製程（及結合後的結構） 組合製程中晶片的提起及放置步驟，相當類似於榡 覆晶片接合製程（分光及/或電容對準，split 〇ptics . and/π capacitance aligned)，並利用焊材熔流 (inflow)來接合。因為晶片和載片間距太小，無法有效 清除助熔劑（flux)，較適合使用不須助熔劑的氫熔流方 式0 比起先前的技術，本發明具有以下明顯的優勢。非常 微小的元件例如雷射、微感測器、促動器（actuat〇r)等 等，可以經由微接合的方式裝置在同一平面上，形成面積 陣列（area array )。元件的尺寸可以小至1〇〇 χ 100 或更小，而這種尺寸的元件已經無法以覆晶片的方 式固定。使用鉛錫焊材可以在升級或修理而須更換元件晶 片時重新連接。具有微接合焊材點的元件可先測#、預燒 (bUrned-in)、挑選，確定功能正常之後才裝上。所使 用的暫時固定結構及方法在相關的專利申枝 Y〇R92〇〇1〇249US1中有所描述。因此就算互月聯節距甚小， 仍可獲得已知為良好的晶粒（d丨e )。 〜本發:月在前面的部分已經就較為適當的製作方式，有 者詳細的說明。然而在不悖離本發明的 1222712 案號 92100860 9a 4. 26 年月曰_修正 圖式簡單說明 五、【圖式簡單說明】 圖一為沉積了氮化钽-鈕、銅、鎳和接合金屬後的元件晶 片切面圖。 圖二為沉積了氮化鈕-钽、銅、鎳和貴金屬後的載片晶圓 切面圖。 圖三為完成的載片（上方）及元件晶片（下方）準備接合 時的切面圖。 元件符號說明 1 0晶片 1 3元件及底層佈線 1 5襯塾層 1 7種晶層 2 0阻障層 36介質保護層 3 9襯塾層 41阻障層 1 2晶圓 1 4上方金屬佈線層 1 6介質保護層 1 9接點開孔 3 4互聯佈線層 38接點開孔 40種晶層 42貴金屬層
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Claims (1)

1222712 _案號 92100860 9¾ L 26 免月曰 修正 六、申請專利範圍 1. 一種在一互聯載片（interconnect carrier)上藉一微 接合結構陣列（array micr〇 joint structures)連接 一組元件晶片（device chips )的一系統，包含： 該载片包含一多層基板（multilayer substrate)， 该多層基板之一表面具有複數個微接合座（micro joint receptacles )； 一組微接合點（m i c r o j o i n t p a d s )，位於和該座 (receptacle )接合的該元件晶片上，該組微接合點包含 焊材小球（s ο 1 d e r b a 1 1 s ); 互聯佈線，固定於該載片中，該互聯佈線連接到微接 合點陣列，以互聯該載片上的該元件晶片；以及 其中 在該互聯載片上的該座包含一黏著層（adhesion layer)、一阻障層（barrier layer)及一貴金屬層 (noble metal layer );以及 在該元件晶片上的該微接合點包含一黏著層、一阻障 層及一可溶焊材層（fusible solder layer)。 2·如申請專利範圍第1項所述之系統，其中在該互聯載片 上的該座，依次包含一襯塾層（liner layer)，一種晶 層（seed layer)，該阻障層（barrier layer)及該貴 金屬層（noble metal layer)，都位於該座的内表面。 3 ·如申請專利範圍第2項所述之系統，其中該襯墊層係選
lill
第16頁 1222712 9a 4. 26 _案號92100860 _年月日_Hi_ 六、申請專利範圍 自组（T a )，氮化组（T a N )，鈦（T i )，氮化鈦 (TiN )，鎢（W )，氮化鎢（WN )，鉻（Cr )及其組合所 組成之一群組。 4.如申請專利範圍第3項所述之系統，其中該襯墊層厚度 在50 A到1 20 0 A之間。 1222712 案號 921008Rf) 六、申請專利範圍 aa 4.26 _1 5 ·如申請專利範圍第2項戶斤述之系統，其中該種晶層為厚 度300 A到2000 A的銅。' 6 ·如申請專利範圍第2項所述之系統，其中該阻障層係選 自鎳（Ni)，鈷（c〇)，鉑（Pt)，鈀（Pd)，其合金或 組合所組成之一群組。 _ 7 ·如申請專利範圍第6項所述之系統，其中該阻障層厚度 在1 〇 0 0 A到1 0 〇 〇 〇 a之間。 8·如申請專利範圍第1項所述之系統，其中在該元件晶片 上的该微接合點，依次包含一襯塾層，一種晶層，該阻障 層及該可、熔焊材層（fusible solder layer)。 9 ·如申請專利範圍第8項所述之系統，其中該襯墊層係選 自鈕’氮化组，鈦，氮化鈦，鑛，氮化鑛，鉻或其組合所 組成之一群組。 1 〇 ·如申請專利範圍第8頊所述之系統，其中該種晶層為厚 度3〇“到2_ A的銅。員所 U·如申請專利範圍第8項所述之系統，其中該阻障層係選 自鎳’始，翻，把，其合金或、组合所組成之一群組。 第18頁 1222712 —^孤 4· 26 修正
_案號 92100Sfin__-a 六、申請專利範圍 1 2.如申請專利範圍第11項所述之系統，其中該阻障層厚 度在1 Ο Ο Ο A到1 〇 〇 〇 〇 A之間。 1 3 ·如申請專利範圍第2項所述之系統，其中該载片係由矽 製成，且包含沉積其上之/組互聯佈線，該互聯佈線上表 面上方之一介質保護層，及該介質保護層中的該座。 ^ 1 4 ·如申請專利範圍第1 2項所述之系統，其中該元件晶片 包含位於其上藉佈線連接的一組元件，位於佈線上表面上 方的一介質保護層，以及該介質保護層中的該微接合點。 1 5 ·如申請專利範圍第1 2項所述之系統，其中該元件晶片 係選自包含微處理機晶片，記憶體晶片，微控制器晶片， 雷射二極體晶片，雷射驅動器晶片，光感測器晶片，無線 通訊晶片，與邏輯處理器晶片之一群組。 16· —種微接合互聯結構（microjoint interconnect structure )，包含.： (a) —載片基板（carrier substrate)，具有供連接 元件成份（device components)之一互聯陣列（array of interconnects )； (b) 該載片包含一基板，一介質薄膜（dielectric f i lm )，與微接合座，微接合座包含一黏著層（adhes ion
第19頁 1222712 —~一 ea 4· 26 ___案號921Q0860_年月日_修正 _ 六、申請專利範圍 layer)，一擴散阻障層（diffusion barrier layer)與 一貴金屬層； (c ) 微接合點位於元件側，包含一黏著層，一焊材反 應阻障層（solder reaction barrier layer)，與供每 個成份（component )使用的可熔焊材接合球（fusible solder joint ball); (d )在該載片側之元件上的該微接合點匹配 (m a t c h )該載片側上的微接合座。 1 7 ·如申請專利範圍第1 6項所述之微接合互聯結構，其中 該元件成份為半導體晶片，光學元件晶片等等。 1 8 · —種在一互聯載片上藉一微接合結構陣列連接一組一 件晶片的一製程，包含： 疋 形成該載片’該載片包含一多層基板，該多層基 一表面上具有複數個微接合座； & 於 在該元件θ曰片上形成一組微接合點，接合至該 一表面中的座，該微接合點包含焊材小球； ^ 片之 形成固定於該載片中的互聯佈線，該互聯佈線 該微接合點陣列，以互聯該載片上的該元件晶片。 到 1 9. 一禮微接合互聯結構，包含： (a) —載片基板，具有一供連接元件成份的互聯 列； ΛΟ ^ ο β 案號 921〇QRgQ 年 月 日 修正 六、申請專利範圍 (b)該載片包含一基板與一介質薄膜，該載片與微接 合點各自包含一黏著層，焊材反應阻障層及可熔焊材接合 球； (c )微接合座在該元件側，包含一黏著層，一擴散阻 障層及一貴金屬層； (d )在該載片側的該微接合點匹配該元件上的微接合 座。 20.如/請專利範圍第19項所述之微接合互聯結構，其中 元件晶片係選自包含半導體晶片，光學元件晶片，通訊晶 片之一群組。 儆接合結構陣列 21· —種在一互聯載片上藉 件晶片的一製程，包含： 形成該載片，該載片包 #夕甘α 一表面上且士…多層基板，該多層基板 衣卸上具有禝數個微接合點； 在该元件晶]之_矣 片上之焊材小球接合：該栽☆形成-組微接合座’藉該 點陣列，31ΐ二聯伟缘，該互聯佈線連接該微接
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