CN1298052C - 具有Cu互连的半导体器件及其制造方法 - Google Patents

具有Cu互连的半导体器件及其制造方法 Download PDF

Info

Publication number
CN1298052C
CN1298052C CNB200410002438XA CN200410002438A CN1298052C CN 1298052 C CN1298052 C CN 1298052C CN B200410002438X A CNB200410002438X A CN B200410002438XA CN 200410002438 A CN200410002438 A CN 200410002438A CN 1298052 C CN1298052 C CN 1298052C
Authority
CN
China
Prior art keywords
interconnection
film
semiconductor device
atom
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB200410002438XA
Other languages
English (en)
Other versions
CN1518101A (zh
Inventor
利根川丘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1518101A publication Critical patent/CN1518101A/zh
Application granted granted Critical
Publication of CN1298052C publication Critical patent/CN1298052C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

在半导体器件中的一种Cu连接，它具有不均匀的添加金属原子分布，其中添加金属原子在Cu互连的下表面和侧表面附近含量较高。Cu互连也具有不均匀的硅分布，其中添加硅原子在Cu互连的上表面附近含量较高。这种结构提高了Cu互连的电子迁移阻抗和压力迁移阻抗。

Description

具有Cu互连的半导体器件及其制造方法
发明领域
本发明涉及具有Cu互连的半导体器件及其制造方法。
背景技术
随着半导体器件中更精细的结构和更高的半导体元件集成密度的发展，减少半导体器件中的互连阻抗就变得重要起来。作为减少互连阻抗的措施之一，嵌入Cu互连的半导体器件被引入到实际使用中，其中Cu被用作互连的材料，并且使用所谓的镶嵌处理来制造互连。
需要指出的是，互连不但如上所述减少了互连阻抗，而且应该具有更高的电子迁移阻抗。这同样适用于嵌入Cu连接的情况。
为了获得更高的电子迁移阻抗，将包括诸如Al和Ag等其他金属元素的Cu合金用于Cu连接，如公开的专利申请JP-A2000-150522和JP-A2002-75995所述。在这种技术中，在层间电介质膜中，嵌入到凹槽和/或通孔中的Cu膜形成于由诸如Cu-Al和Cu-Ag等Cu合金做成的籽晶膜上，或者与覆盖在Cu膜之上的其他金属膜有关，因此添加金属原子能够扩散到Cu膜里去。
本发明人发现，上述使用籽晶膜或其他金属膜的技术几乎不会提高压力迁移阻抗，除了电子迁移阻抗以外，压力迁移阻抗也是互连所具有的。
更为确切地说，由于作为互连的一部分的通孔在用于连接覆盖的互连的互连线路的表面上形成，则将机械压力应用于互连线路的通孔和上表面之间的接触部位。这种使用籽晶膜来扩散金属原子的技术，没有提供充足的金属原子使其到达金属线路的表面。因此，由于在Cu连接线路中的微小空穴的移动，由通孔所施加的压力在互连线路的表面上形成了空隙。这种空隙在公开的专利申请JP-A-2000-58544或JP-A-2000-150517中所述的结构中也会产生，其中Cu连接的上表面覆盖着Cu硅化物层。
另一方面，在通过上表面将金属原子扩散到Cu连接以便提高电子迁移阻抗的技术中，由于压力迁移的影响，空隙将产生于Cu连接线路的下表面。由压力迁移所造成的空隙在Cu连接具有更大表面的情况下发生得更经常，例如，在连接线路更宽和/或更长的情况下。
发明内容
考虑到现有技术中的上述问题，本发明的一个目标就是提出一种具有Cu互连的半导体器件，它能够抑制Cu连接的电子迁移和压力迁移。
本发明提出了一种半导体，它包括具有添加金属原子和添加硅原子的第一个Cu互连，其中在第一个Cu互连的下表面和侧表面附近的添加金属原子密度比在它的上表面附近的添加金属原子密度高，并且在它的上表面附近的添加硅原子密度比在它的下表面和侧表面附近的添加硅原子密度高。
根据本发明的半导体器件，这里的Cu互连包括在Cu互连的四个表面附近的添加金属原子和硅原子，因此提高了Cu连接在四个表面上的电子迁移阻抗和压力迁移阻抗。
本发明还提出了一种用于制造半导体器件的方法，包括如下步骤：在包括Cu和添加金属的籽晶膜的上面形成Cu膜；将籽晶膜中的添加金属扩散到Cu膜中；以及，通过Cu互连的上表面，将硅原子扩散到Cu膜中。
根据本发明的方法，这里的Cu互连通过它的四个表面来接收添加金属原子和硅原子，因此提高了Cu互连在四个表面上的电子迁移阻抗和压力迁移阻抗。
需要指出的是，通过Cu互连的上表面进行硅原子的扩散与Cu互连表面上的Cu硅化物膜的形成完全不同。更为确切地说，Cu硅化物膜的形成试图在互连表面的Cu和硅原子之间引起积极的硅化物反应，因此硅到Cu互连的扩散受到硅化物反应的抑制。在本发明方法的优选实施例中，硅化物反应得到抑制，以便硅原子扩散到Cu互连中。
从下面的讲述并参考附图，可以明显知道本发明的上述和其他目标、特征及优势。
附图说明
图1A～1I为根据本发明的第一个实施例，在半导体器件制造处理的连续若干步骤中半导体器件的截面图。
图2A～2I为根据本发明的第二个实施例，在半导体器件制造处理的连续若干步骤中半导体器件的截面图。
具体实施方式
现在参考附图来更加详细地讲述本发明，其中在附图中，类似的组成元素由类似的标号来表示。
图1A～1I示出了根据本发明的第一个实施例来制造半导体器件的制造过程。在图1A中，电介质膜3形成于硅衬底1的表面上，硅衬底1包括诸如晶体管等半导体元件的扩散区2。电介质膜3里面具有接触孔8，它暴露于硅衬底1的扩散区2上。接触孔8中具有嵌入导体6。嵌入导体6包括金属阻挡膜4和钨塞5，其中具有两层结构的金属阻挡膜4包括在扩散区2上的Ti层(图中未示出)和上面覆盖的TiN层(图中未示出)。
如图1B所示，层间电介质膜10淀积在电介质膜3和嵌入导体6上，然后在层间电介质膜10中形成互连凹槽12。互连凹槽12暴露出嵌入导体6和部分电介质膜3。因此，另一个具有包括TaN层和覆盖的Ta层在内的两层结构的金属阻挡膜14，是通过溅射的方法在整个表面上形成的，然后再在上面形成籽晶膜15。籽晶膜15是由包括Cu和添加金属Al在内的Cu合金组成的，并被溅射到金属阻挡膜14上。优选情况下，Cu合金包括0.1～1.5wt％(重量百分比)的Al，最好是不低于0.1wt％和低于1wt％。在这个例子中，Cu合金包括0.5wt％的Al。所添加的金属Al可以用诸如Sn、Ti、Si、In、Ag、Zr、Ni、Mg、Be、Pd、Co、B、Zn、Ca、Au和Ga等其他金属元素来代替或补充。
接着，通过镀或CVD技术，将Cu膜16淀积于整个表面上，如图1B所示，然后在200～400℃的温度下对其进行热处理或退火，以便将籽晶膜15中的Al扩散到Cu层16中去。
这样，就获得了包括作为主要成分的Cu和添加元素Al在内的Cu合金膜20，如图1C所示。这样形成的Cu合金膜20具有不均匀的Al分布，其中从Cu合金膜20的下表面到上表面进行观察，以及从合成的Cu互连的侧表面到上表面进行观察，Al的含量是递减的。
因此，如图1D所示的例子，将CMP(化学-机械式抛光)处理应用于Cu合金膜20的上表面，这样就获得了Cu互连30以作为Cu合金膜20和下面覆盖的金属阻挡膜14的其余部分。接着，Cu互连30为硅烷(SiH4)所辐射，因此在等离子增强型CVD反应器中就收到包括有Cu互连30在内的半导体晶片。用于硅烷辐射的处理条件包括硅烷气流速度为10～500sccm(每秒标准立方厘米)，N2气流速度为100～5000sccm，周围压强为20Torr，处理温度约为350℃，处理时间120s。
上述条件通过Cu互连的上表面将硅原子合适地扩散到Cu互连30中，基本上不会形成Cu的硅化物层，例如，在Cu互连30的上表面不发生硅化物反应。硅原子到Cu互连30的上表面的扩散，在Cu互连30中形成不均匀的硅分布，其中硅含量从Cu互连30的上表面到下表面和侧表面进行观察是递减的。添加硅原子数量最好在Cu互连30的总共原子个数的0.01～8at.％(原子的百分比)。
因此，Cu互连30的Al分布情况为，在Cu互连30的下表面和侧表面附近的Al含量比在上表面附近的Al含量高，并且Cu互连30的硅分布情况为，在Cu互连30的上表面附近的硅含量比在下表面和侧表面附近的硅含量高。
需要指出的是，在硅原子扩散到Cu互连30期间，氧化膜或任何氧化物不应该存在于Cu互连的上表面。为此目的，最好在进行硅烷处理之前，通过使用氢气来对Cu互连上的氧化膜或任何氧化物进行去氧化。这种去氧化可以在用于硅烷处理的等离子增强型CVD反应器中进行。
接着，等离子增强型CVD反应器中的反应气体被切换为SiH(CH3)3、NH3和He的混合物，以便于在整个表面上淀积等离子增强型CVD SiCN膜31，如图1E所示。淀积的SiCN膜31具有抑制Cu扩散的功能，因此称其为Cu扩散抑制膜31。使用同样的等离子增强型CVD反应器，会阻止包括添加Al和Si原子在内的Cu互连30的表面在Cu扩散抑制膜31的淀积期间被氧化。在进行Cu扩散抑制膜31的淀积之前，Cu硅化膜将形成于包括添加Al和Si原子在内的Cu互连30上。
因此，如图1E所示，层间电介质膜32淀积于Cu扩散抑制膜31上，接着形成通孔35，用于容纳通孔塞，以及形成互连凹槽36，用于容纳覆盖在层间电介质膜32和SiCN膜31上面的互连线路。这种结构称为双层镶嵌结构。在本发明的处理中，双层镶嵌结构的形成使用的是通孔优先的技术，凹槽优先的技术，中间优先的技术，或者双重硬掩模的技术。
接着，包括Ta/TaN层在内的金属阻挡膜40和Cu-Al合金籽晶膜41先后淀积于其上，然后使用镀或CVD技术来淀积Cu膜42，如图1F所示。
接着，通过使用热处理或退火处理，将合金籽晶膜41中的Al扩散到Cu膜42中，这样就形成了Cu-Al合金膜45，如图1G所示。
然后进行CMP处理以使其平坦化，直到Cu-Al膜45和金属阻挡膜41使电介质膜32暴露出来，这样就形成了另一个包括Cu-Al合金在内的Cu互连50，如图1H所示。然后用硅烷来辐射Cu互连50，这与对图1D所作的讲述类似，因此就将硅原子扩散到Cu互连50中去。
这样形成的Cu互连50中的Al分布情况为，在下表面和侧表面附近的Al原子含量比较高，Si分布情况为，在上表面附近的Si原子含量比较高。Cu互连50包括在凹槽中水平延伸的Cu互连线路，以及与下面的Cu互连线路30相接触的通孔塞。
然后，Cu扩散抑制膜60淀积在包括Cu互连50在内的整个表面上，如图1I所示。通过重复如图1E～1I所示的步骤，就形成了预定数目的Cu互连。
如上所述，每一个Cu互连30和50都有不均匀的Al分布，也就是说，除了Cu之外的其他金属的分布，其中在下表面和侧表面附近的Al原子含量较高，在上表面附近的Si原子含量较高。这样提高了Cu互连30和50的电子迁移阻抗。另外，在与接触孔8中的导体6相接触的部分，以及在与Cu互连50的通孔塞相接触的部分，Cu互连30的压力迁移阻抗得到提高。对于Cu互连50，压力迁移阻抗在通孔塞和与Cu互连的相接触的部分也得到提高。
在本实施例中，层间电介质膜10和32由诸如SiOC或SiCOH等含碳的硅氧化物膜组成。不过，层间电介质膜10和32也可以由硅氧化物(SiO2)，梯型加氢硅氧烷(梯型氧化物TM)，加氢硅氧烷(HSQ)，含氟硅氧化物(SiOF)，甲基倍半硅氧烷(MSQ)，诸如聚亚苯基、多芳基醚和苯并环丁烯等低介电常数有机聚合物，以及含有多孔的绝缘物质之一组成。
在上述实施例中，每一个金属阻挡膜14和40都具有Ta/TaN两层结构。不过，每一个金属阻挡膜都可以由Ta、TaN、TaSiN、W、WN、WSiN、Ti、TiN或TiSiN膜，或者它们的两层或多层膜来代替。金属阻挡膜可以使用PVD(物理蒸发淀积)，CVD(化学蒸发淀积)或ALD(原子层淀积)等方法来淀积。
图2A～2I示出了根据本发明的第二个实施例，用于制造半导体器件的制造过程。本实施例被应用于所谓的单镶嵌结构。
如图2A～2D所示，导体6和第一层Cu互连30形成于硅衬底1上。第一层Cu互连30与导体6相连，导体6与在硅衬底1中形成的扩散区2相接触。
接着，如图2E所示，Cu扩散抑制膜31和层间电介质膜70先后在整个表面上形成，接着通过有选择性地对Cu扩散抑制膜31和层间电介质膜70进行蚀刻，在单个的镶嵌结构中形成了通孔71。然后在包括通孔71在内的整个表面上形成了包括Ta/TaN层在内的金属阻挡膜72，接着先后形成了籽晶膜(图中未示出)和Cu膜73。然后使用CMP处理来去掉通孔71中的Cu膜73以及金属阻挡膜72和籽晶膜。本实施例中的籽晶膜由Cu组成，而不包括任何诸如Al等其他金属。Cu膜73不包括扩散的硅原子。Cu膜73夹在金属阻挡膜72和Cu扩散抑制膜75之间，因此具有更高的电子迁移阻抗和更高的压力迁移阻抗。
另一种情况是，籽晶膜可以由Cu合金组成，因此除Cu以外还可以包括其他金属原子，它们通过籽晶膜的上表面扩散到Cu膜73中。另外，通过上表面，硅原子可以扩散到Cu互连线路73中。
因此，如图2F所示，层间电介质膜78淀积在整个表面上，接着通过有选择性地对层间电介质膜78和Cu扩散抑制膜75进行蚀刻，形成用于容纳Cu互连线路的互连凹槽79。因此，通过使用类似于图1F所述的处理，形成了金属阻挡膜40、籽晶膜41和Cu膜42，如图2F所示。
因此，如图2G～2I所示，通过使用类似于图1G～1I所述的处理，形成了第二层Cu互连50。
在本实施例中，层间电介质膜10、70和78由诸如SiOC或SiCOH等含碳的硅氧化物组成。不过，层间电介质膜10、70和78也可以由硅氧化物(SiO2)，梯型加氢硅氧烷(梯型氧化物TM)，加氢硅氧烷(HSQ)，含氟硅氧化物(SiOF)，甲基倍半硅氧烷(MSQ)，诸如聚亚苯基、多芳基醚和苯并环丁烯等低介电常数有机聚合物，以及含有多孔的绝缘物质之一组成。
在上述实施例中，每一个金属阻挡膜14、72和40都具有Ta/TaN两层结构。不过，每一个金属阻挡膜都可以由Ta、TaN、TaSiN、W、WN、WSiN、Ti、TiN或TiSiN膜，或者它们的两层或多层电介质膜来代替。金属阻挡膜可以使用PVD(物理蒸发淀积)，CVD(化学蒸发淀积)或ALD(原子层淀积)等方法来淀积。
在上述实施例中，半导体器件具有低电阻的互连，它有着更高的电子迁移阻抗和更高的压力迁移阻抗。
由于上述实施例仅是作为例子，本发明并不局限于上述实施例，本行业的一般熟练人员都可以对其进行各种修正或改动，只要不偏离本发明的范围。例如，在Cu合金中添加金属，处理条件，以及所使用的材料都可以根据需要进行修改。

Claims (11)

1.一种半导体器件，包括具有添加金属原子和添加硅原子的第一Cu互连，其中所述添加金属原子的密度在所述第一Cu互连的下表面和侧表面附近比在其上表面附近高，并且所述添加硅原子的密度在所述上表面的所述附近比在所述下表面和侧表面的所述附近高。
2.如权利要求1所述的半导体器件，其中所述添加金属原子包括从由Al、Sn、Ti、Si、In、Ag、Zr、Ni、Mg、Be、Pd、Co、B、Zn、Ca、Au和Ga组成的组中挑选的一或多种金属的原子。
3.如权利要求1所述的半导体器件，进一步包括第二Cu互连，覆盖在所述的第一Cu互连之上，并且包括有添加金属原子和添加硅原子，其中在所述的第二Cu互连中的所述添加金属原子的密度在所述第一Cu互连的下表面和侧表面附近比在其上表面附近高，并且所述第二Cu互连中的所述添加硅原子的密度在所述上表面的所述附近比在所述下表面和侧表面的所述附近高。
4.如权利要求3所述的半导体器件，其中在所述第二Cu互连中的所述添加金属原子包括从由Al、Sn、Ti、Si、In、Ag、Zr、Ni、Mg、Be、Pd、Co、B、Zn、Ca、Au和Ga组成的组中挑选的一或多种金属的原子。
5.如权利要求3所述的半导体器件，其中所述的第二Cu互连包括Cu互连线路和从所述Cu互连线路延伸并且连接到所述第一Cu互连的通孔塞。
6.如权利要求3所述的半导体器件，其中所述第一Cu互连与所述第二Cu互连经由金属阻挡膜所覆盖的Cu塞连接在一起。
7.一种制造半导体器件的方法，包括如下步骤：
在包括有Cu和添加金属的籽晶膜上形成Cu膜；
将所述籽晶膜中的所述添加金属扩散到所述Cu膜中；以及
通过Cu互连的上表面将硅原子扩散到所述Cu膜中。
8.如权利要求7所述的方法，其中所述硅原子扩散步骤包括将硅烷辐射到所述Cu膜上的步骤。
9.如权利要求8所述的方法，其中所述辐射步骤是在将所述Cu膜用于Cu互连之后进行的。
10.如权利要求7所述的方法，其中所述籽晶膜包括所述添加金属的含量为0.1～1.5wt％。
11.如权利要求7所述的方法，其中所述籽晶膜包括有作为所述添加金属的Al，其重量百分比低于1％且不低于0.1％。
CNB200410002438XA 2003-01-24 2004-01-20 具有Cu互连的半导体器件及其制造方法 Expired - Fee Related CN1298052C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP016700/2003 2003-01-24
JP2003016700A JP4152202B2 (ja) 2003-01-24 2003-01-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1518101A CN1518101A (zh) 2004-08-04
CN1298052C true CN1298052C (zh) 2007-01-31

Family

ID=32767493

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200410002438XA Expired - Fee Related CN1298052C (zh) 2003-01-24 2004-01-20 具有Cu互连的半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US20040150113A1 (zh)
JP (1) JP4152202B2 (zh)
CN (1) CN1298052C (zh)
TW (1) TWI247359B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687917B2 (en) * 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
US8193606B2 (en) * 2005-02-28 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a memory element
DE102005035740A1 (de) * 2005-07-29 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer isolierenden Barrierenschicht für eine Kupfermetallisierungsschicht
DE102005057057B4 (de) * 2005-11-30 2017-01-05 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer isolierenden Deckschicht für eine Kupfermetallisierungsschicht unter Anwendung einer Silanreaktion
US7749361B2 (en) * 2006-06-02 2010-07-06 Applied Materials, Inc. Multi-component doping of copper seed layer
JP4896850B2 (ja) * 2006-11-28 2012-03-14 株式会社神戸製鋼所 半導体装置のＣｕ配線およびその製造方法
US7737013B2 (en) * 2007-11-06 2010-06-15 Varian Semiconductor Equipment Associates, Inc. Implantation of multiple species to address copper reliability
JP5180598B2 (ja) * 2008-01-21 2013-04-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4709238B2 (ja) * 2008-02-08 2011-06-22 株式会社日立製作所 Ｃｕ系配線用材料およびそれを用いた電子部品
JP5380901B2 (ja) 2008-05-12 2014-01-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2010114255A (ja) * 2008-11-06 2010-05-20 Toshiba Corp 半導体装置の製造方法
US8404582B2 (en) * 2010-05-04 2013-03-26 International Business Machines Corporation Structure and method for manufacturing interconnect structures having self-aligned dielectric caps
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110817A (en) * 1999-08-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improvement of electromigration of copper by carbon doping
US6123825A (en) * 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
US6387806B1 (en) * 2000-09-06 2002-05-14 Advanced Micro Devices, Inc. Filling an interconnect opening with different types of alloys to enhance interconnect reliability

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211084B1 (en) * 1998-07-09 2001-04-03 Advanced Micro Devices, Inc. Method of forming reliable copper interconnects
US6046108A (en) * 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
DE10224167B4 (de) * 2002-05-31 2007-01-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Kupferleitung mit erhöhter Widerstandsfähigkeit gegen Elektromigration in einem Halbleiterelement
US7060617B2 (en) * 2002-06-28 2006-06-13 Intel Corporation Method of protecting a seed layer for electroplating
US6846752B2 (en) * 2003-06-18 2005-01-25 Intel Corporation Methods and devices for the suppression of copper hillock formation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6123825A (en) * 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
US6110817A (en) * 1999-08-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improvement of electromigration of copper by carbon doping
US6387806B1 (en) * 2000-09-06 2002-05-14 Advanced Micro Devices, Inc. Filling an interconnect opening with different types of alloys to enhance interconnect reliability

Also Published As

Publication number Publication date
TWI247359B (en) 2006-01-11
US20070093060A1 (en) 2007-04-26
JP4152202B2 (ja) 2008-09-17
US20040150113A1 (en) 2004-08-05
JP2004228445A (ja) 2004-08-12
CN1518101A (zh) 2004-08-04
TW200414363A (en) 2004-08-01

Similar Documents

Publication Publication Date Title
US11990368B2 (en) Doped selective metal caps to improve copper electromigration with ruthenium liner
US7396759B1 (en) Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
US7425506B1 (en) Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films
US6294836B1 (en) Semiconductor chip interconnect barrier material and fabrication method
US11177167B2 (en) Ultrathin multilayer metal alloy liner for nano Cu interconnects
US7524755B2 (en) Entire encapsulation of Cu interconnects using self-aligned CuSiN film
EP1943675B1 (en) Metal interconnect structure for a microelectronic element
US20040004288A1 (en) Semiconductor device and manufacturing method of the same
US6977218B2 (en) Method for fabricating copper interconnects
CN1298052C (zh) 具有Cu互连的半导体器件及其制造方法
KR20110052668A (ko) 금속 배선들을 위한 컨포멀 접착 프로모터 라이너
US10541199B2 (en) BEOL integration with advanced interconnects
US20100193956A1 (en) Multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same
US6727592B1 (en) Copper interconnect with improved barrier layer
US6656834B1 (en) Method of selectively alloying interconnect regions by deposition process
KR100924556B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
JP4492919B2 (ja) 半導体装置の製造方法
US6555474B1 (en) Method of forming a protective layer included in metal filled semiconductor features
US7169706B2 (en) Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition
CN115036270B (zh) 铜互连结构的制作方法
KR20040037305A (ko) 반도체 소자의 금속 배선 형성 방법
WO2004030089A1 (en) Method of forming a copper interconnect with concentrated alloy atoms at copper-passivation interface

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: NEC CORP.

Effective date: 20101119

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20101119

Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: NEC Corp.

CP02 Change in the address of a patent holder

Address after: Tokyo, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: Renesas Electronics Corporation

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070131

Termination date: 20200120