TWI247359B - Integrated circuit structure and fabrication method thereof - Google Patents

Integrated circuit structure and fabrication method thereof Download PDF

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TWI247359B
TWI247359B TW093101154A TW93101154A TWI247359B TW I247359 B TWI247359 B TW I247359B TW 093101154 A TW093101154 A TW 093101154A TW 93101154 A TW93101154 A TW 93101154A TW I247359 B TWI247359 B TW I247359B
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copper
interconnect
film
semiconductor device
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TW200414363A (en
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Takashi Tonegawa
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Nec Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1247359
【發明所屬之技術領域】 且特別有關於，種 本發__，明係有關於一種半導體元件 具有銅内連線的半導體元件輿其製法 【先前技術】 =::體裝置中’除了半導體元件更精細的結構與更 高的積集度外，降低内連線電阻變得越來越重要.而降低 内連線電阻的方法之一，就是在半導體裝置中實際使用嵌 入式銅内連線，而其中的銅用作内連線材料且^二内速線 製造中的鑲嵌製程中。 其中内連線應該具有較高的電子遷移電阻，以降低上 述内連線電阻，·而嵌入式銅内連線適用於此情況。 如日本專利jp — A-2000-150522 與-2002-75995 所述， 將包^鋁及銀的添加金屬的銅合金用於銅内連線中，以得 到較高的電子遷移電阻；在此技術裡，嵌入層間介電膜中 的溝槽與/或介層洞的銅膜，形成於由銅合金所形成的晶 種膜（seed film)上’如銅鋁合金或銅銀合金，或結合 其它金屬膜形成於銅膜上，以使此添加金屬原子可擴散至 銅膜裡。 本發明發現上述使用晶種膜或其它金屬膜的技術，除 對内連線中的電子遷移電阻外，對應力遷移電阻幾乎沒有 改善。 更明確地’由於内連線部份的介層洞通常形成於内連 線的上表面，以與其上方的内連線連結，所以在介層洞與 内連線上表面的接觸窗中就會存在機械應力；而此利用晶
1247359 五、發明說明（2) 種膜來擴散金屬原子的技術，並未提供足夠金屬原子的量 到達内連線表面，因此，銅内連線中微小洞穴的移動會使 介層洞所作用的應力在内連線的上表面產生空隙，此空隙 即使在銅内連線的上表面覆蓋銅矽化物層的日本專利 JP-A-2000-58544 或-2000- 150517 中也會產生。 另一方面，使用經由銅内連線之上表面將金屬原子擴 散至銅内連線以改善電子遷移電阻的技術，由於應力遷移 之故故二隙會在銅内連線的底表面產生，且應力遷移所 產生的空隙較常見於較大表面積的銅内連線裡，即較寬或 較長的内連線中。 【發明内容】 :鑑於上述習知技術中的問冑，本發明的目的之一就 Ϊ的庫力ΐίί銅内連線的半導體裂置，以抑制銅内連線 中的應力遷移電子遷移。 m 一： 目的’本發明提供一種半導體裝置，包括- f加^屬；^ 1包括添加金屬原子與添加的矽原子，其中該 Γ近的密度在該第一銅内連線的底表面與側表面 的矽原子的密 3線的上表面附近，以及其中該添加 一銅内μ第一銅内連線的上表面附近高於該第 j円運線的底表面與側表面附近。 根據本發明的丰導 屬原子與矽原子#裝置，銅内連線中包括的添加金 内連線四個表7… 個表面附近以改善銅 為達上、;κ的電子遷移阻抗與應力遷移阻抗。 κ目的，本發明尚提供一種半導體裝置的製造
2133-6090-PF(N2).ptd 第7頁 1247359 發明說明（3) 五 方法，包括形成一銅膜於於_ 臈上；將上述晶種膜中的上、+、；:有銅與一添加金屬的晶種 述銅膜的上表面擴散至上述銅膜中。 的四個表面使銅内連線中且有，經由銅内連線 抗。 卞遷移阻抗與應力遷移阻 線上中：i子經由銅内連線的上表面㈣，與在銅内連 的形成是在内連線表面上的銅匕物膜 成，Μ山士 e十 、’项于屋生矽化反應而形 方法：―較佳制矽擴散進銅内連線中；在本發明 銅内連、線巾。Λ & 1 ，此石夕化反應將抑制銅原子擴散至 【實施方式】 易懂為$ 2 3 2 2 ί其他目&、特徵和優點能更明顯 說明如下：、+ λ鈿 <列’並配合所附圖式，作詳細 第1 Α至第11圖為本發明實施例1之半導體I I . 在第1Α圖+，介電膜3m访體扁置製程。 接Ϊ:洞中8且形ΐ於石夕基底1的擴散區2暴露出來;、而、1 屬膜4盘鎢；ίΓ.入:導體6 ’此嵌入式導體6包括阻隔金 蜀腺4 /、鎢插塞5 ,此阻隔金屬膜4包括 結構包括於擴散層2上的欽層（未顯示）“;冓上= 第8頁 2133-6090-PF(N2).ptd 1247359
鈦層（未顯示）。 如第1B圖所示，層間介雷胳 、 式導體6上，隨後形成内連壤沉積於介電膜3與嵌入 且將嵌入式導體6與= 層間介請。中， 組層與於1上之知,Λ二 暴露出；之後，包括氮化 所有表面上，然後藉由濺鑛形成於 由銦人厶％ π Λ、 八上形成日日種層1 5，此晶種層丨5是 屬膜1口4上：ί .ίΪ銅和添加金屬銘，且濺鍍至阻隔金 :膜14上’而其中銅合金較佳包含〇. (重量百 二1的在呂’且更佳為不小於〇.lwt%以及小於iwt%，在此
2中，銅合金包括0.5wt%u呂，上述添加金屬在呂可由一種 2峰多其它元素所取代或是再添加，這些金屬係擇自於 鈦石夕銦、銀、鍅、鎳、鎮、鈹、纪、結、侧、 鋅、約、金與鎵。 接I來’藉由電鍍或CVD技術沉積銅膜16於整個表面 上’如第1B圖所示，接著再利用2〇〇〜4〇〇 〇c的熱處理或退 火步驟以將晶種膜1 5的銘擴散至銅層1 6中。 因此’就得到以銅為主成分以及添加鋁的銅合金膜 20 ’如第1C圖所示，銅合金膜2〇中的鋁具有均勻的分佈， k鋼合金膜2 0的底表面往上表面看以及從組合物銅内連線 的側表面往上表面看，其中該鋁含量下降。 之後’如第1D圖所示’例如進行化學機械研磨（C Μ P )製程以處理銅合金膜2〇的上表面，然後剩下銅合金膜20 的部分就成為銅内連線3〇，且此層覆蓋阻隔金屬膜14 ;接 下來，將具有銅内連線3〇的半導體晶圓置於電漿增強化學
2133-6090-PF(N2).ptd 第9頁 五、發明說明（5) 軋相沉積（PECVD )反應爐中，以矽烷（sUane，SiH4 )處 ，鋼内連線30，此矽烷處理的製程條件包括10〜50 0 seem 標準立方公分/ 分鐘，staMard cubic centimeters
Per minute)的矽烷氣體流速、1〇〇〜5〇〇〇 “⑽的氮氣氣 體流速、20 Τ〇ΓΓ的氣體壓力、約35(rc的熱處理與12〇秒 的處理時間。 @ q η ί述提供矽原子經由銅内連線3 〇上表面擴散至銅内連 内的合適條件，且大體上並不會形成銅矽化物層在銅 j線30上表面，即無涉及金屬矽化物反應；而矽原子經 八$内連線30上表面的擴散提供在銅内連線30中一致的矽 =盥，且其中矽含量的分佈從銅内連線30的上表面往底表 表面減少，且此添加矽原子的量較佳佔整體銅内連 ’ 、〇· 01 〜8 at% (原子百分比，atomic percents )。 =此，銅内連線3〇所具有的鋁分佈在底表面與側表面 盘伽L上表面附近還多，而矽分佈在上表面附近比底表面 興側表面附近還多。 上表 卜 田矽原子擴散至銅内連線3 0中時，銅内連線的 之扩面=應f氧化膜或任何氧化物存在，所以在矽烷處理 化I作^ ^藉由氫氣對銅内連線上的氧化膜或任何其它氧 進行。虱化，此去氧化可利用矽烷處理的PECVD反應爐 接下來 3、ΗΝ3 與He 第1 E圖所示 將PECVD反應爐中的反應氣體轉換成SiH(CH3) 以隨後在整個表面沉積pECVD SiCN膜31，如 此沉積的SiCN膜31具有抑制銅擴散的功能，
1247359 五、發明說明（6) 所以稱為銅 免具有添加 制膜3 1時被 加鋁及矽原 之後， 散抑制膜3 1 在層間介電 介電膜32與 為雙鑲嵌結 擴散抑制 鋁及矽原 氧化；在 子的銅内 如第1 E圖 上，接著 膜32中形 銅擴散抑 構；在本 膜31 ; 子的銅 沉積銅 連線30 所示， 在層間 成介層 制膜31 發明製 洞第一形成技術、溝槽第一 利用相同 内連線30 擴散抑制 上形成銅 沉積層間 介電膜32 插塞與内 中形成覆 程中，此 形成技術 或雙硬罩幕 之後， 晶種層4 1， 1 F圖所示。 接下來 散至銅膜42 然後利 41，以使介 内連線50包 第1 D圖中所 中 〇 技術。 沉積具有Ta/TaN 再接著藉由電鑛 的PECVD反應爐可避 表面在沉積銅擴散抑 膜31前，可在具有添 矽化物膜。 介電膜3 2於沉積銅擴 中形成介層洞3 5，以 連線溝槽3 6且在層間 蓋内連線，此結構即 雙鑲嵌結構可為介層 、中間第一形成技術 層的阻隔金屬層40與銅銘合金 或CVD技術沉積銅膜42，如第 ’藉由熱處理或退火將合金金屬膜41中的鋁擴 中’以形成銅鋁合金膜42，如第1G圖所示。 用CMP製程來平坦化銅鋁膜45與阻隔金屬膜 電膜3 2疼出’然後形成另一個銅導線5 0，此銅 ，銅鋁合金，如第1 H圖所示；接下來利用類似 描述的矽烷步驟，將矽原子擴散至銅内連線5 〇 表 多 而：2 f :銅内連線5〇所具有的鋁分佈在底表面與側 面附近、上表面附近還多，而矽分佈在上表面附近較 銅内連線50包括水平延伸的銅内連線，且銅内連線μ 1247359
五、發明說明（7) 中之溝槽與介層洞柄愛 妙 Π插塞與其下之銅内連線30接觸。 線5“Ϊ:==層6〇於整個表面上，包括銅内連 步驟，即可形成=複第1Ε圖至第Π圖的 如上所述，每條銅内連線30與50都具有不均勻的鋁 2銅以外的金屬）及石夕分佈，其"呂分佈在底表面與側 I附近較多，而矽分佈在上表面附近較多，這樣可改盖 ，内連線30與50的電子遷移阻抗；此外，銅内連線3〇在‘ 洞8中的導體6部分與被銅内連線5〇所覆蓋的介層洞插塞 的接觸部分的應力遷移阻抗可改善；在銅内連線5〇中，介 層洞，銅内連線所接觸的部分之應力遷移阻抗也可改善。 在本實施例中，層間介電膜1〇與32是由含碳氧化矽膜所構 成，如SiOC或SiCOH，然而，層間介電膜10與32可由氧化 石夕（Si 02)、梯型的鼠化石夕氧燒（iacjder — type hydrogenated siloxane) (Ladder OxideTM)、氫化石夕氣 烷（hydrogenated sil〇xane，簡稱HSQ)、含氟氧化矽 (SiOF )、含甲基石夕酸鹽類（methylsilsesquioxane，巧 稱MSQ )、低介電常數之有機聚合物，如聚伸苯 (polyphenylene)、聚芳醚（p〇iyaryiether)與苯環丁 烯（benzocyclobutene)，以及這些絕緣體且具有孔洞者 所取代。 在上述實施例中，每層阻隔金屬膜14與40都具有 Ta/TaN兩層結構，然而，這些阻隔金屬膜可由Ta、TaN、 TaSiN、W、WN、WSiN、Ti、TiN或TiSiN膜或兩層或兩層以
2133-6090-PF(N2).ptd 第12頁 1247359_ 圖式簡單說明 第1 A〜1 I圖為本發明實施例1中之半導體裝置的剖面 圖，用以說明其連續製程步驟。 第2 A〜2 I圖為本發明實施例2中之半導體裝置的剖面 圖，用以說明其連續製程步驟。 【符號說明】 1〜ί夕基底 2〜擴散區 3〜介電膜 4〜阻隔金屬膜 5〜 ν鎢插塞 6〜嵌入式導體 8 - -接觸洞 10、70、78〜層間介電膜 12 〜内連線溝槽 14〜其它阻隔金屬膜 15 〜晶種層 16、42、73〜銅膜 20 〜銅合金膜 3 0〜銅内連線 31 、6 0、7 5〜銅擴散抑制膜 32 〜層間介電膜 3 5、7 1〜介層洞 36 〜内連線溝槽 40、72〜阻隔金屬層 41 〜晶種層 4 5〜銅1呂膜 50 〜銅導線
2133-〇090-PF(N2).ptd 第16頁

Claims (1)

1247359 六 '申請專利範圍 1 · 一種半導體步w 屑原子與添加的矽/早，^括一第一銅内連線包括添加倉 卜内連線的底表面虚侧=:金屬原子的密度在i 的上表面附近，以及Α Φ、表面附近南於該第一銅内連線 銅内連線的上表面附;;古該添加的矽原子的密度在該第一 表面附近。 呵於該第一銅内連線的底表面與側 添加金項所述之半導體裝置，其中該 链、锡、鈦、碎、銦之i屬m係擇自 硼、鋅、辟^於锆、鎳、鎂、鈹、鈀、鈷、 鈣、金與鎵所組成之族群。 一第二如申凊專利範圍第1項所述之半導體裝置，尚包括 包括i ,内連線於該第1内連、線上，且該第二銅内連線 線中二σ金屬原子與添加的矽原子，其中於該第二銅内連 側力金屬原子的岔度高於在第一銅Θ連線的底表面與 =、、附近且兩於該第二鋼内連線的上·表面附近，以及其 古二添加的矽原子的密度在該第二銅内連線的上表面附近 Ν ;邊第二銅内連線的底表面與側表面附近。 4·如申請專利範圍第3項所述之半導體裝置，其中該 一内連線中添加金屬原子包括一或一以上之金屬，且該 屬係擇自鋁、錫、鈦、矽、銦、銀、鍅、鎳、鎂、鈹、 鈀、鈷、硼、鋅、鈣、金與鎵所組成之族群。 5·如申請專利範圍第3項所述之半導體裝置，其中該 第一銅内連線包括一銅内連線與一介層洞插塞由上述銅内 連線延伸且與該第一鋼内連線接觸。 _ 第17頁 2133-6090-PF(N2).ptd
6·如申請專利範圍第3項所述之半導體裝置，其中該 第一銅内連線與該第二鋼内連線經由一具有一阻 的銅插塞連接在一起。 _ 五屬膜 7· —種半導體裝置的製造方法，包括： 2於於_具有銅與一添加金屬的晶種膜上，· 法， 法’ 法’ w t % ；a曰9種膜中的上述添加金屬擴散至上述銅膜中· 將:夕：：經由上述鋼膜的上表面擴散至上述銅膜：： 豆中兮二專利靶.圍第7項所述之半導體裝置的製造方 〇Γ ^ =往Ϊ子擴散步驟包括將矽烷擴散至該銅膜裡。 其中誃乾圍第8項所述之半導體裝置的製造方 /〇 ·如/驟^是在銅膜形成銅内連線後執行。 其中該曰明蘇胳利範圍第7項所述之半導體裝置的製造方 。/、 X日日、所包括的添加金屬的濃度為0 · 1〜1. 5
2133-609G-PF(N2).ptd 第18頁
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