CN1292472C - 用于调节半导体器件的载流子迁移率的结构和方法 - Google Patents

用于调节半导体器件的载流子迁移率的结构和方法 Download PDF

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CN1292472C
CN1292472C CN200410087007.8A CN200410087007A CN1292472C CN 1292472 C CN1292472 C CN 1292472C CN 200410087007 A CN200410087007 A CN 200410087007A CN 1292472 C CN1292472 C CN 1292472C
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transistor
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布鲁斯·B·多斯
杨海宁
朱慧珑
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GlobalFoundries Inc
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Abstract

在制造互补的金属氧化物半导体(CMOS)场效应晶体管(包括nMOS和pMOS晶体管)的过程中，根据层和隔离应力层相互的以及在选定位置具有附加层的其它结构的性能，通过将各种不同的应力膜涂覆到nMOS或pMOS晶体管(或其两者)上来提高或调节载流子迁移率。这样，可增大单一芯片或基片上的两种晶体管的载流子迁移率，从而改善CMOS器件和集成电路的性能。

Description

用于调节半导体器件的 载流子迁移率的结构和方法
【技术领域】
本发明涉及集成电路晶体管的制造，更具体地说，本发明涉及以非常小的规模生产增强性能场效应晶体管互补对。
【背景技术】
集成电路设计和制造中的性能和经济因素使集成电路元件(例如晶体管、电容器及类似元件)的规格大小急剧减小并且在芯片上的接近度增大。也就是，元件增大的集成度和接近度减小了信号传播路径的长度，并减小了信号传播的时间和对噪声的敏感度以及时钟频率可能的增大量，而增大集成度所必需的元件尺寸的减小则通过减小芯片之间和线路板之间所需的连接数目而增大了芯片所具有的功能度与每个芯片的生产成本(例如晶片/芯片的面积和工艺材料)以及潜在地与包含芯片的器件的成本的比。
但是，由于集成电路元件的规格减小，因此总要危及晶体管和其它元件发挥功效的材料性能和物理效应。因此，人们对晶体管的设计进行了很多的改进，以便将这些元件的性能保持在适当的水平上。例如，采用轻掺杂漏极(LDD)结构(由于在电流最小特征尺寸状态下需要重掺杂，因此，现在通常被称为延伸掺杂)、晕圈掺杂和分级的杂质分布以减小短沟道和击穿效应及类似的现象，特别是在已成为除最高频率器件之外选择的有源器件的场效应晶体管(FET)中。器件规格的减小还要求在减小的电压下工作，以保持适当的性能而不对器件造成损害，即使是减小工作范围，也是如此。
在场效应晶体管中保持适当性能的重要因素是载流子迁移率，在通过非常薄的电介质与沟道相绝缘的栅电极上的电压的控制下，载流子迁移率会影响可在掺杂半导体沟道中流动(作为电子或空穴)的电流或电荷量。在FET中减小的载流子迁移率不仅降低了给定晶体管的开关速度/转换速率，而且还减小了“接通”电阻与“断开”电阻之间的差。后者会增大噪声敏感度并减小可被激励的下游晶体管栅电极(电容性负载)的数目和/或速度，有时被称为输出端数。甚至在金属氧化物半导体(MOS)场效应晶体管和互补MOS(CMOS)器件(目前被广泛地用于集成电路中)的早期开发过程中，具体地说，载流子迁移率是设计所关心的，并通常需要将pMOS器件制成大约为互补nMOS器件的两倍大，它们配合成对，从而由于nMOS器件中的电子、主载流子与pMOS器件中的空穴、主载流子之间的载流子迁移率差而使CMOS对适当对称地进行工作。在最近关键的设计中，由于需要重掺杂来抑制短沟道效应和超薄氧化物效应，因此在大比例的基块MOS器件中载流子迁移率下降。
而且理论和相应的经验表明，根据应力的符号(例如拉伸或压缩)和载流子类型(例如电子或空穴)，FET沟道区域中的机械应力会显著地增大或降低载流子迁移率。在形成晶体管沟道的掺杂半导体晶格中，拉应力会增大电子迁移率并减小空穴迁移率，而压应力会增大空穴迁移率并减小电子迁移率。这种现象已为人熟知，且在任何情况下，发生该物理现象的有关理论对于其开发来说都是不重要的。就此，人们提出了多种结构和材料，以便在半导体材料中产生拉伸或压缩力，例如通常包含在集成电路结构中的浅沟槽隔离(STI)结构、栅电极隔离物、腐蚀阻断层和硅化物。而且，出于结构上的原因，还可在半导体中产生持久不变的应力。例如，US6069049和US6399976教导我们，在结构的周围涂覆一层膜，然后减小膜的体积以便对结构进行压缩，并因此而避免缺陷发生扩散。但是，在现有技术中，用于产生应力的结构通常可制成只产生唯一形式的应力，产生拉应力或压应力，而不是两者兼有。因此，在采用pFET和nFET晶体管和CMOS技术(其中，逻辑电路主要由互补的pMOS和nMOS晶体管对来实现)的集成电路设计中，具体地说，增大一种晶体管中的载流子迁移率就必须同时减小另外或互补的晶体管中的载流子迁移率；虽然理论上可改善操作的平衡，但即使有也只产生少量的纯性能增益。而且，由这种结构产生的单一形式的应力会使晶片或基片(特别是在较薄的情况下，按照电流方向)产生翘曲或挠曲，这会损害后面进行的平板印刷工艺过程例如触点和连接点的形成，或者，在恶劣或大应力情况下，芯片或晶片会发生破裂；从而降低了生产率或(偶尔)降低了使用后的可靠性。另外，这种结构所产生的应力水平通常难于进行控制，因为结构的尺寸通常由其它的有关设计考虑参数进行控制，例如绝缘和击穿电压。
【发明内容】
因此，本发明的目的是提供一种通过采用不同类型的应力膜在局部并同时分别施加拉应力或压应力来增强nFET和pFET的性能的结构和方法。
本发明的另一个目的是在集成电路晶体管中产生所需的应力而不使晶片或基片发生翘曲或挠曲。
为实现本发明的这些和其它的目的，提供一种调节CMOS器件中的载流子迁移率的方法，其包括以下的步骤：将第一应力膜淀积在包括一个互补晶体管对的晶片上，以便在晶体管的沟道中产生应力，局部去除第一应力膜以便消除掉其中一个晶体管的沟道中的应力，将第二应力膜淀积在第一和第二晶体管上，以便将第二应力施加到去除掉第一应力膜的晶体管的沟道上。
通过该方法，获得了一种可调节CMOS晶体管中的载流子迁移率的结构，其包括一个基片，一个形成在基片上的互补晶体管对，每个晶体管具有栅电极电介质、栅电极以及源极、漏极和栅电极硅化物区域，一个至少在其中一个晶体管的沟道中产生拉应力的第一膜，一个至少在另一个晶体管的沟道中产生压应力的第二膜，以及一个至少在一个区域将第一膜和第二膜分离开的剪力隔离层。
【附图说明】
本发明前述的和其它的目的、特点和优点可从下面结合附图对本发明优选实施例所进行的详细描述中得到更好的理解，其中：
图1是预制结构的横截面图，本发明可应用于该预制结构，以获得图6所示最终的这对典型的nMOS和pMOS晶体管。
图2是图6所示最终的这对典型的nMOS和pMOS晶体管的第一生产阶段的横截面图，其中，淀积有拉伸氮化膜，以便在器件的沟道中产生拉应力。
图3是图6所示最终的这对典型的nMOS和pMOS晶体管的第二生产阶段的横截面图，其中，直接淀积并深腐蚀有氧化物。
图4是图6所示最终的这对典型的nMOS和pMOS晶体管的第三生产阶段的横截面图，其中，通过湿式蚀刻法将有些区域的拉伸硝酸盐去除掉。
图5是图6所示最终的这对典型的nMOS和pMOS晶体管的第四生产阶段的横截面图，其中，将原始的电介质12去除掉，并用淀积在nMOS和pMOS晶体管上如图所示淀积在nMOS晶体管上的一个新的电介质层12来代替。然后，通过光致抗蚀剂将nMOS晶体管屏蔽，同时对覆盖pMOS晶体管的拉伸膜和电介质进行蚀刻。
图6是最终的这对典型的nMOS和pMOS晶体管的第五生产阶段的横截面图，其中，将光致抗蚀剂蚀刻掉，并淀积压缩膜，从而形成本发明最终的优选实施例。
图7是图6所示典型结构的横向应力测量值的图线。
图8a是在步骤1和2(分别如图2和3所示)完成之后用于形成图8c所示的本发明第二实施例的另一种第三阶段的横截面图，其中，光致抗蚀剂涂覆在芯片或晶片的nMOS晶体管侧。
图8b是用于形成图8c所示的本发明第二实施例的另一种第四阶段的横截面图，其中，将没有被光致抗蚀剂遮挡的膜区域去除掉，然后去除掉所述的光致抗蚀剂。
图8c是用于形成这里所示的本发明第二实施例的另一种第五阶段的横截面图，其中，压缩膜横跨nMOS和pMOS晶体管并淀积在其上。
【具体实施方式】
如图所示，图1示出了一对典型的互补nMOS和pMOS晶体管的横截面，这对晶体管可包括一个位于一部分集成电路中的CMOS对。通过在源极、漏极和栅电极区上形成硅化物来接通这些晶体管，从而减小后面所施加的接触电阻。这些晶体管的制造方法及其结构的详细情况对于理解本发明或其成功地进行应用是无关紧要的。应当理解，虽然图1示出的是在应用本发明之前的晶体管，但图示是为了更清楚地进行示意，而且，图1中没有一个部分被认为是本发明的现有技术。
在图1及其它的附图中，晶体管形成于基片14上(按照本发明最佳的应用情况，由于晶体管可能确定的比例很大，因此基片14可以比图示的厚)。晶体管20和21通过隔离氧化物16、例如也可用于确定基片14的n阱和p阱区域的浅沟槽隔离结构相互隔离开。在此情况下，晶体管20和21为导电性互补的结构形式，因此，位于这些相应晶体管下面的基片14的部分也是相反掺杂的。
另外，晶体管20和21的结构相似；每个晶体管都具有栅电极电介质205、215、栅电极208、218、侧壁隔离结构10以及源极、漏极和栅电极硅化物区域，正如对本领域技术人员所熟悉的那样，最好由相对于侧壁隔离结构10自定准的掺杂物形成。还可设置延伸和晕圈掺杂物、分级结及类似的结构。
应当理解，在下面对图1-6的讨论过程中，将要描述的实施例预计在大多数应用场合以及集成电路设计中是最佳的，且因此是优选的，而且是一个可使最完整估价的本发明得到转让的一个实施例。但是，本发明结合该实施例所描述的原理还可用于在任何的设计中将任何所需量的各种符号的应力提供给相邻的电子元件。
图2示出了在形成图6所示的本发明的过程中从图1所示的基本结构中截取出的第一步骤。该步骤包括将应力膜11(例如拉力)淀积在图1所示的其余结构上，以便于在晶体管20和21的沟道201、211中产生应力(例如拉力)。在淀积该膜之前，可选择去除掉侧壁隔离结构12。高应力膜最好是氮化硅(Si3N4)或氮氧化硅(Si3OxNy)或它们两者的混合物。根据特定的工艺参数例如等离子的功率和气体流速，这些材料可以高应力的方式进行淀积，以提供拉应力或压应力。例如，利用PECVD工艺，应力水平主要由等离子的功率进行控制，并且，通常会产生压应力。热CVD Si3N4在600℃以上的温度下进行淀积，并通常产生拉应力。施加这种拉应力会增强nMOS晶体管20的性能，同时降低pMOS晶体管21的性能。
图3示出了形成图6所示的最终典型结构的第二步骤。在该步骤中，电介质12(例如氧化物)通过高密度等离子淀积(HDP)和例如化学机械抛光淀积在图2所示的结构上，在氮化物11上停止CMP，然后对氧化物12进行深腐蚀，以形成图示的结构。本发明在实践中，对于氧化物层12的厚度并没有严格的要求，但层的厚度最好是50-100nm。电介质12最好是可用作深腐蚀的腐蚀阻断物和位于拉伸膜11和后面所施加的压缩膜13之间的中间隔离层的无应力氧化物或其它的无应力材料。
图4示出了形成图6所示的最终典型结构的第三步骤。在先前步骤中淀积的电介质12现在被用作掩模，通过湿式蚀刻形成一个应力膜11的去除区域的图案形状。如图所示，在该步骤中，在nMOS20和pMOS21晶体管上仍然作用相同的拉应力，以增强nMOS晶体管20的性能，同时降低pMOS晶体管21的性能。
图5示出了形成图6所示的最终典型结构的第四步骤。将现存的电介质材料12(如图4所示)去除掉，并且，如图所示在nMOS晶体管20上，在两个栅电极208和218上淀积一个新的电介质层120。该层120使后面施加的层的应力不会作用于基片。涂覆遮挡光致抗蚀剂22，并通过蚀刻将pMOS晶体管21周围的电介质和应力膜基本上除去。该步骤的结果是，nMOS晶体管20仍然受到拉伸膜11的影响，并仍保持增强的性能，而pMOS晶体管21不再承受降低的性能，而且由于去除了应力膜11所产生的拉应力，因此，重新取得了正常的电位性能。
图6示出了形成图示的最终典型结构的第五和最后的步骤。在该步骤中，首先从芯片的nMOS晶体管20侧将光致抗蚀剂22除去，然后，将另一个应力膜13涂覆到整个芯片上。该膜最好可向pMOS晶体管21提供压应力，从而提高其载流子迁移率，而且，如果对nMOS晶体管20的沟道中的力有任何的影响的话，也是很小的。由于nMOS晶体管20通过电介质层120与压缩膜13隔离开，因此，该步骤基本上不会影响nMOS晶体管20，nMOS晶体管20仍只受拉伸膜11的作用。由于存在这种特定的应力膜对晶体管的作用，因此，pMOS沟道211和nMOS沟道201具有增强的载流子迁移率。
图7是在模拟应用本发明的情况下作用于晶体管的最终横向应力值的图线。该图线是根据栅电极电介质205、215下方5nm位置处的晶体管应力值和将应力氮化物作为拉伸膜和压缩膜在50nm应力膜厚度的情况下得出的。根据所确定的情况，确定区域的应力结果是：在nMOS晶体管沟道201处大约为+190Mpa，在pMOS晶体管沟道211处大约为-300Mpa。因此，可以看出，拉伸和压缩应力基本上共同存在于同一基片14上的晶体管沟道201、211中。
另外，本发明用于制造晶体管的类似的有效方法包括与步骤一(图2)和步骤二(图3)相同的过程，但其它的步骤三、四和五分别如图8a、8b和8c所示。在图8a中，将光致抗蚀剂涂覆在CMOS的nMOS晶体管侧，以免将其膜去除掉，从而在整个nMOS晶体管栅电极208和沟道201周围保留一层拉伸膜。如图8b所示，没有被光致抗蚀剂覆盖的pMOS晶体管的氧化物和拉伸膜层都被去除掉。在去除掉膜之后，如图8b所示也去除掉光致抗蚀剂。然后，将压缩膜涂覆到nMOS和pMOS晶体管上，从而实现如图8c所示的本发明的第二实施例。
优选实施例和第二实施例虽然在形式上略有不同，但它们具有相同的功效。优选实施例(图6)具有将拉伸膜11与压缩膜13分离开的电介质层，而第二实施例(图8c)在栅电极208上方的膜之间不具有这样的层(虽然它存在于栅电极侧)。另外，在优选实施例(图6)中，拉伸膜不象在第二实施例(图8c)那样完全围绕nMOS晶体管20，而是拉伸膜只与一部分栅电极侧接触，并具有中性电介质120与栅电极208的其余部分接触。这可根据各种膜的厚度使得在第一和第二实施例之间产生较小的尺寸变化。而且，栅电极上相邻的压缩和拉伸膜13和11在栅电极208的区域上相互呈现反作用。
另外，对于pMOS晶体管，优选实施例(图6)包括电介质层120、17，除了留下与压缩膜13相接触的栅电极顶部之外，它们围绕栅电极218大部分的氧化物衬层19。第二实施例不包括前述的电介质层，因此，围绕栅电极218侧部的整个氧化物衬层19与压缩膜13相接触，压缩膜13直接与栅电极218的顶部相接触。第一和第二实施例之间的这些差别并不影响沟道201、211中的应力水平，因此，当进行比较时，所述第一和第二实施例在潜在的载流子迁移率方面并没有明显的差别。
鉴于上述情况，可以看出，本发明提供了一种在同一芯片的nMOS和pMOS晶体管中用于控制或改善载流子迁移率的方法和结构，并且不会损害生产效率或对先前所形成的结构或后面所进行的过程造成不利的影响，而且在不损害生产效率并只需很少额外而又有显著提高的工艺过程就可方便地进行控制。由于压缩和拉伸力可能基本上作用于相对较小的相应区域上(例如，与芯片的厚度相比较)，因此，芯片或晶片没有发生翘曲或挠曲的趋势。应当理解，虽然载流子迁移率的“改善”通常的意思就是提高，但载流子迁移率的降低也是需要的，并且根据晶体管的类型，只通过调换腐蚀阻断层的淀积工艺过程，从而针对相应的晶体管导电/掺杂类型，作用相反的拉伸或压缩力，就可利用同一工艺过程而降低载流子迁移率。由于通过淀积过程参数可控制拉伸或压缩应力量，因此，在拉伸和压缩力的作用范围内，而且还根据栅电极的几何结构，可使空穴和电子载流子迁移率增大、减小或调整到任何所需的程度。
虽然通过一个优选实施例对本发明进行了描述，但本领域技术人员应当认识到，在不脱离本发明权利要求书所体现的宗旨和范围的情况下，还可对本发明作出很多的变化。

Claims (19)

1.一种调节半导体器件中的载流子迁移率的方法，其包括以下的步骤：
将第一应力膜淀积在包括第一和第二晶体管的晶片上，以便在晶体管的沟道中产生应力，
局部去除掉所述第一应力膜，以便消除掉其中一个所述晶体管的沟道中的所述应力，
在剩余的所述第一应力膜的至少一个区域上淀积剪力隔离层，
将第二应力膜淀积在第一和第二晶体管上，以便将第二应力施加到已去除掉所述第一应力膜的晶体管的沟道上。
2.根据权利要求1所述的方法，其中，第一晶体管和第二晶体管是不同导电类型的晶体管。
3.根据权利要求2所述的方法，其中，第一膜和第二膜施加相反的应力。
4.根据权利要求3所述的方法，其中，通过将拉应力施加到所述第一晶体管上同时将压应力施加到所述第二晶体管上来调节载流子迁移率。
5.根据权利要求4所述的方法，其中，至少一个应力膜是通过等离子增强化学气相淀积(PECVD)来进行涂覆的。
6.根据权利要求4所述的方法，其中，至少一个应力膜是通过热化学气相淀积(CVD)来进行涂覆的。
7.根据权利要求5所述的方法，其中，至少一个应力膜是通过热CVD来进行涂覆的。
8.根据权利要求4所述的方法，其还包括以下的步骤：
局部或全部将第一应力膜从由氧化物层遮盖的第一和第二晶体管上去除掉；
去除所述的氧化物层，并将剪力隔离层淀积在整个CMOS对上；
将阻断层涂覆到第一晶体管和所述层/膜的相关部分上；
将与所述第二晶体管相关的层/膜部分去除掉；
从所述第一晶体管上去除掉所述阻断层；以及
将所述第二应力膜淀积在第一和第二晶体管上。
9.根据权利要求4所述的方法，其还包括以下的步骤：
将阻断层涂覆到所述第一晶体管上；
局部或全部地将所述第一应力膜从第二晶体管上去除掉；
从所述第一晶体管上去除掉所述阻断层；以及
将所述第二应力膜涂覆到第一和第二晶体管上。
10.一种可调节CMOS晶体管中的载流子迁移率的结构，其包括：
一个基片，
一个形成在所述基片上的第一晶体管，其具有栅电极电介质、栅电极以及源极、漏极和栅电极硅化物区域，
一个形成在所述基片上的第二晶体管，其具有栅电极电介质、栅电极以及源极、漏极和栅电极硅化物区域，
一个至少在第一晶体管的沟道中产生拉应力的第一膜，
一个至少在第二晶体管的沟道中产生压应力的第二膜，
以及一个至少在一个区域将所述第一膜和所述第二膜分离开的剪力隔离层。
11.根据权利要求10所述的结构，其中，第一和第二膜可由氮化物、氧化物或具有拉伸或压缩性能的其它材料构成。
12.根据权利要求11所述的结构，其中，第一和第二应力膜在所有的点处通过剪力隔离层分离开。
13.根据权利要求12所述的结构，其中，比第二应力膜更靠近基片的第一应力膜不完全围绕nMOS晶体管，而是只围绕在其侧面，而nMOS晶体管其余的表面与所述剪力隔离层接触。
14.根据权利要求13所述的结构，其中，所述剪力隔离层是nMOS晶体管和所述第二膜之间的唯一的隔离物。
15.根据权利要求13所述的结构，其中，除了直接与所述第二应力膜接触的栅电极的顶部之外，所述剪力隔离层围绕pMOS晶体管栅电极的大部分氧化物层。
16.根据权利要求11所述的结构，其中，第一和第二应力膜在选定的区域由剪力隔离层分离开。
17.根据权利要求16所述的结构，其中，比第二应力膜更靠近基片的第一应力膜完全包围nMOS晶体管。
18.根据权利要求17所述的结构，其中，所述第一应力膜是nMOS晶体管和所述第二应力膜之间的唯一隔离物。
19.根据权利要求17所述的结构，其中，所述第二应力膜包围位于pMOS晶体管栅电极侧面的氧化物衬层，该栅电极的顶部直接与所述第二应力膜接触。
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