CN1266771C - 具有氧扩散阻挡层的电容器和制造该电容器的方法 - Google Patents
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Abstract
本发明提供了一种具有双层氧扩散阻挡层的电容器，该电容器含有电极、在电极上含铝层的双层氧扩散阻挡层，在氧扩散阻挡层上的介电层，和介电层上的顶部电极。
Description
技术领域
本发明是关于半导体装置，尤其是关于半导体装置中具有氧化铝层作为氧扩散阻挡层的电容器，及制造该电容器的方法。
相关技术描述
当大大增加如DRAM半导体装置的集成度时，使用了具有高容量的介电材料。已经开发研制了诸如Ta2O5、TiO2、TaON、HfO2、Al2O3和ZrO2金属氧化物系的材料。作为电容器的介电材料。
氧化钽(Ta2O5)层，在超过256M DRAM的高集成半导体装置的电池中，已被用作电容器的介电层，具有约25的电容量(εr)，氧化钽层具有3或4倍于氮化硅(Si3N4，εr＝～7)/氧化硅(SiO2，εr＝～3.8)层的叠层介电层的电容量，一般用作电容器的介电层。
图1A是表示现有技术的柱状金属-氧化物-硅(MIS)电容器的截面视图。使用氧化钽层作电容器的介电层。
正如所示，在具有晶体管和位线(未示出)的半导体基质11上所形成内层绝缘层12和蚀刻阻挡层13。通过蚀刻阻挡层13和内层绝缘层12将存储节点接触14连接到半导体基质11。然后，在蚀刻阻挡层13上形成存储节点氧化物层15，然后有选择地蚀刻存储氧化物层15，以暴露出存储节点接触14。当蚀刻存储氧化物层15时，下切部分内层绝缘层12到蚀刻阻挡层13以下，以暴露出顶侧和部分存储节点接触14的侧面侧。
随后，形成连接到存储节点接触14的圆柱型的底部电极16，要装配在内层绝缘层12的下切口处。并在底部电极16的表面上形成半球状颗粒17。在半球状颗粒17的表面上形成氮化硅层18。此后，在氮化硅层18上依次形成氧化钽层19和顶部电极20。
图1B是图1A中“A”处的详细截面视图。
正如所示，在底部电极16上形成半球状颗粒18后，通过表面硝酸化过程而形成氮化硅层18。在氮化硅层18上形成氧化钽层19后，进行热处理过程，以使氧化钽层19结晶化并保证所要求的电容量。此后，在氧化钽层19上形成顶部电极20。
然而，根据现有技术，在对氧化钽层19进行后热处理过程期间，由于氮化硅层18不能有效地防止氧向底部电极16扩散，因此存在的问题是在底部电极的表面上厚厚地形成诸如氧化硅(SiO2，εr＝3.9)层这样的一种低-k的介电层。
由于低-k介电层降低了电容器的电特性，所以不可能期望半导体装置能稳定运行，即，降低了电容器的容量，并增加了漏电。
发明简要
因此，本发明的目的是在半导体装置中提供具有包括氧化铝层在内的双层氧扩散阻挡层的电容器，及制造该电容器的方法。
根据本发明的一个方面，提供的电容器包括：电极、电极上含铝的氧扩散阻挡层、氧扩散层上的介电层，和介电层上的顶部电极。
根据本发明的另一方面，提供制造电容器方法，包括如下步骤：a)形成底部电极，b)在底部电极上形成含铝的氧扩散阻挡层，c)在氧扩散阻挡层上形成介电层，和d)在介电层上形成顶部电极。
附图的简要描述
结合附图，从最佳实施方案的下述中，会更加清楚本发明的上述和其他目的及特征。
图1A是表示现有技术中圆柱形金属-氧化物-硅(MIS)电容器的截面视图。
图1B是图1A中“A”处的详细截面视图。
图2是表示本发明电容器结构的截面视图。和
图3A～3E是表示根据本发明制造图2所示电容器方法的截面视图。
发明的详细描述
下文将参照附图详细描述本发明的一种能够抑制在底部电极和介电层之间所形成的氧化物层的电容器，及制造该电容器的方法。
图2是表示本发明电容器结构的截面视图。
如图所示，在半导体基质21上形成内层绝缘层22，通过内层绝缘层22。形成要连接到半导体基质21的存储节点接触插头23，此后，在内层绝缘层22上形成具有开孔以暴露存储节点接触插头23的蚀刻阻挡层24和存储节点氧化物层25。蚀刻阻挡层24像片颚一样伸出，以在蚀刻阻挡层24的下面提供下切口。
随后，在要连接到存储节点接触插头23的所得结构上形成圆柱型的底部电极28A，该电极的底部部分由蚀刻阻挡层24所物理地支撑，即，它具有的形状是底部电极28A的底部部分装配到蚀刻阻挡层24下面提供的下切口内。为了增加底部电极的表面积，在底部电极28A上形成诸如半球状粒子29的不平整度，将不平整的表面进行硝化，以形成氮化硅层30，作为第一氧扩散阻挡层而起作用。
随后，在氮化硅层30上形成氧化铝层31，作为第二氧扩散阻挡层，随后在氧化铝层31上依次形成氧化钽层32和顶部电极33。
如图2所示，根据本发明，在沉积氧化钽层32作为电容器的介电层后，为防止在进行热处理过程期间氧向底部电极28A扩散，使用了氮化硅层30和氧化铝层31的双层氧扩散阻挡层。
与只使用氮化硅作氧扩散阻挡层相比，当使用氮化硅层30和氧化铝层31双层作为氧阻挡层时，由于在沉积氧化钽层32后进行热处理过程期间，氧化铝层31防止氧向底部电极28A扩散的优良能力，所以能有效地防止氧扩散，氧化铝层31防止氧扩散的优良能力，意思是氧不可能通过氧化铝层31而扩散，这是因为铝和氧(Al-O)之间的结合能非常高。
由于形成半球状的颗粒29，所以能增加电容器的容量。而且，由于底部电极28A牢固地由蚀刻阻挡层24下面所提供的下切口支撑，所以当底部电极破裂时，能防止底部电极之间产生的跨接和底部电极的提升。
图3A-3E是表示根据本发明制造图2所示电容器方法的截面视图。
参照图3A，在半导体基质21上形成内层绝缘层22，然后，通过蚀刻内层绝缘层22形成接触孔，以暴露部分半导体基质21。沉积作为传导层的聚硅层，以填充接触孔，并进行覆盖蚀刻过程，由此形成存储节点接触插头栓23。在内层绝缘层22和存储节点接触插头23上依次沉积蚀刻阻挡层24和存储节点氧化物层25。用原硅酸四乙酯(TEOS)形成存储节点氧化物层25，用氮化硅形成蚀刻阻挡层24。使用聚硅层作为硬掩膜层26。正如所知道的，只使用光致抗蚀剂，是难以蚀刻高厚度的存储节点氧化物层25，因此使用像聚硅层一类的硬掩膜层26。
通过掩膜层和蚀刻过程蚀刻硬掩膜层26之后，再通过利用硬掩膜层26作蚀刻掩膜层，使存储节点氧化物层25蚀刻到蚀刻阻挡层。随后，蚀刻蚀刻阻挡层24，由此形成凹面图样，而形成底部电极。这时，由于内层绝缘层在蚀刻阻挡层的下面受到深度蚀刻，所以暴露出接触插头23的顶表面和部分侧面。
此后，另外再进行湿式蚀刻过程，以扩大由蚀刻存储节点氧化物层所形成的凹面图样27的宽度。利用稀释HF的湿式化学剂、混合HF系的化学剂或混合氨系的化学剂，通过浸渍过程而进行湿式-蚀刻过程。进行湿式-蚀刻浸渍过程的理由是加宽底部电极的表面积，并物理性地牢固地支撑底部电极的底部部分。
在湿式-蚀刻过程期间，由于蚀刻阻挡层24和具有不同于存储节点氧化物层25的蚀刻选择性的硬掩膜层26不被蚀刻，所以分别在硬掩膜层26和蚀刻阻挡层24下面产生下切口。即，硬掩膜层26和蚀刻阻挡层24像片颚一样伸出。接着，在得到的结构上沉积无定形硅层28。
参照图3B，对无定形硅层28进行化学机械的抛光(CMP)过程，直到暴露出存储节点氧化物层25的表面为止，以致结晶化无定形硅层28的底部电极28A从相邻的底部电极中分离。此时，进行CMP过程期间硬掩膜层26也被去除。
随后，进行湿式-蚀刻过程，使存储节点氧化物层25的顶侧位于底部电极28A的顶侧下面，以在形成半球状颗粒(HSGs)时，可防止相邻底部电极彼此连接。使HSGs生长，以增加底部电极28A的表面积。
参照图3C，通过底部电极28A表面的硝酸化过程，在底部电极28A上形成氮化硅层30。通过利用一种用等离子体处理进行的等离子体硝酸化过程或者在高温下利用NH3气体进行快速热硝酸化(RTN)过程，而进行上述硝酸化过程。RTN过程的实施是在约500～850℃下，NH3气体流速为约1s/m(每分钟标准升)～20s/m，环境压力下进行60秒～180秒。等离子体硝酸化过程的实施是在NH3气流速为约10～1000sccm，用于产生等离子体的RF功率为50～400W，压力为0.1-2乇，进行30-300秒。
参照图3D，在氮化硅层30上形成厚度为10～30的氧化铝(Al2O3)层31。利用氧化铝层31作为底部电极28A表面上的钝化层。氧化铝层可利用ALD法或MOCVD法沉积。
此后，将描述用于形成氧化铝层的ALD方法。将在其中形成底部电极28A的半导体基质21装入沉积室后，将TMA源气体引入具有350～500℃的基质的沉积室内，以使TMA源气体吸附在氮化硅层30的表面上。此后，为了清洗未反应的TMA源气体和付产物，向室内通入N2气或Ar气，或者利用真空泵除去剩余的气体。随后，向室内引入反应气体，H2O气或O3气体，以诱发与吸收的TMA源进行表面反应，以便沉积氧化铝层31。为了去除未反应的反应气体和付产物，向室内通入N2气或Ar气，或者利用真空泵。如上面所提到的，提供TMA源、通入反应气体和净化室内的步骤可重复进行，可沉积出厚度为10-30的具有良好分步覆盖的氧化铝层31。
当利用MOCVD法沉积氧化铝层31时，可向温度约为350～500℃的沉积室内供入Al(OC2H5)3源和O2气。此时，如果在低于300℃的温度下进行沉积过程时，则由于氧化铝源中所含的碳杂质会保留下来，保留的杂质使得介电层的杂质浓度增加，以致于不能防止漏电。如果在高于500℃的温度下进行沉积过程，会伴随底部电极28A的氧化。
参照图3E，通过使用金属有机化学蒸气沉积(MOCVD)法或ALD法，沉积氧化钽层32。当通过使用MOCVD法沉积氧化钽层32时，利用N2气作为载气，以350～450sccm的气体流速使乙醇钽(Ta(OC2H5)5)送入沉积室内。用氧气作为反应气体(或氧化剂)，以10-1000sccm的气体流速通入，通过热分解乙醇钽，使氧化钽层32沉积在150～200℃下加热的半导体基质上。此时，反应室内的压力保持在0.2～10乇。通常用作形成氧化钽层32源的乙醇钽，室温下为液态，145℃下进行蒸发。为了易于使乙醇钽反应，优选使乙醇钽蒸发。因此，在保持170～190℃的蒸发室内，蒸发乙醇钽后，再利用N2气体载气将蒸发的乙醇钽送入反应室内。
此后，通过使氧化钽层32结晶化和还原杂质并耗尽氧，而进行热处理过程。使氧化钽层21结晶化，并去除含在氧化钽层21中的碳杂质。为了补偿氧的耗尽，可在600-750℃下的N2O气体或O2气体的环境中进行热处理过程。由于高温热处理过程期间，在同一时间，氧化铝层31进行结晶化，并不需要另外的热处理过程以使氧化铝层31结晶化。尤其是，由于氧化铝层31是在350-500℃温度下进行沉积，杂质不会存在于氧化铝层31中，以致于不需要低温的热处理过程以去除杂质。
在氧化钽层32上形成顶部电极33。在热处理的氧化钽层32上形成氮化钛(TiN)层或氮化钛层和聚硅层的叠层(聚硅/TiN)，从而最终完成MIS电容器。
正如以上所述，由于在底部电极28A和氧化钽层32之间形成氮化物层30和氧化铝层31，以双层作为氧扩散阻挡层，所以在后热处理过程期间，能抑制氧向底部电极28A扩散，以致能防止在底部电极28A和氧化钽层32之间形成低-k介电层。
由于铝与氧(Al-O)的结合能高于氧化钽的结合能，所以能抑制底部电极28A的氧化。还由于氧化铝的分子结构比氧化钽更坚固且杂质更少，以致能有效地防止氧化剂(O2，N2O)中所含氧的扩散。
还由于使用了氧化铝层，所以能获得增高的击穿电压，和低的漏电量。
就特定的实施方案已描述了本发明，但是本技术领域中的人员应当清楚，在不偏离如下权利要求中限定的本发明精神和范围下可以进行各种变化和改进。
Claims (9)
1.一种电容器，它含有：
底部电极，
在底部电极上形成的含铝的氧扩散阻挡层，
在氧扩散阻挡层上形成的介电层，和
在介电层上形成的顶部电极，
其中，在底部电极和含铝的氧扩散层之间，还具有含氮的氧扩散层。
2.根据权利要求1的电容器，特征是，底部电极在其表面上含有半球状颗粒。
3.根据权利要求1的电容器，特征是，氧扩散阻挡层是氧化铝层。
4.一种制造电容器的方法，它包括如下步骤：
a)形成底部电极，
b)在底部电极上形成含氮的氧扩散层，
c)在氧扩散层上形成含铝的氧扩散阻挡层，
d)在氧扩散阻挡层上形成介电层，和
e)在介电层上形成顶部电极。
5.根据权利要求4的方法，特征是，步骤a)包括如下步骤：
a1)在底部电极表面上形成半球状颗粒。
6.根据权利要求5的方法，特征是，通过使用快速热处理过程或等离子体氮化物过程，形成含氮的氧扩散阻挡层。
7.根据权利要求4的方法，特征是，氧扩散阻挡层是氧化铝层。
8.根据权利要求7的方法，特征是，通过使用低压化学蒸气沉积技术或原子层沉积技术形成氧化铝层。
9.根据权利要求7的方法，特征是，在350～500℃的温度下形成氧化铝层。
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| KR1020020086263A KR100540474B1 (ko) | 2002-12-30 | 2002-12-30 | 산소확산방지막을 구비한 캐패시터 및 그의 제조 방법 |
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| US20060219157A1 (en) * | 2001-06-28 | 2006-10-05 | Antti Rahtu | Oxide films containing titanium |
| US7112503B1 (en) * | 2000-08-31 | 2006-09-26 | Micron Technology, Inc. | Enhanced surface area capacitor fabrication methods |
| US6420230B1 (en) * | 2000-08-31 | 2002-07-16 | Micron Technology, Inc. | Capacitor fabrication methods and capacitor constructions |
| US7217615B1 (en) * | 2000-08-31 | 2007-05-15 | Micron Technology, Inc. | Capacitor fabrication methods including forming a conductive layer |
| KR100536030B1 (ko) * | 2003-02-25 | 2005-12-12 | 삼성전자주식회사 | 반도체 장치의 커패시터 형성 방법 |
| US7440255B2 (en) * | 2003-07-21 | 2008-10-21 | Micron Technology, Inc. | Capacitor constructions and methods of forming |
| US7285312B2 (en) * | 2004-01-16 | 2007-10-23 | Honeywell International, Inc. | Atomic layer deposition for turbine components |
| KR100728962B1 (ko) * | 2004-11-08 | 2007-06-15 | 주식회사 하이닉스반도체 | 지르코늄산화막을 갖는 반도체소자의 캐패시터 및 그 제조방법 |
| JP4949644B2 (ja) * | 2005-06-15 | 2012-06-13 | 株式会社アルバック | ジョセフソン素子の製造方法 |
| KR100712525B1 (ko) * | 2005-08-16 | 2007-04-30 | 삼성전자주식회사 | 반도체 소자의 커패시터 및 그 제조방법 |
| KR100722772B1 (ko) * | 2006-05-03 | 2007-05-30 | 삼성전자주식회사 | 박막 구조물 및 이의 박막 구조물 형성 방법과, 커패시터및 이의 커패시터 형성 방법 |
| US8383525B2 (en) | 2008-04-25 | 2013-02-26 | Asm America, Inc. | Plasma-enhanced deposition process for forming a metal oxide thin film and related structures |
| US20110293830A1 (en) | 2010-02-25 | 2011-12-01 | Timo Hatanpaa | Precursors and methods for atomic layer deposition of transition metal oxides |
| US9062390B2 (en) | 2011-09-12 | 2015-06-23 | Asm International N.V. | Crystalline strontium titanate and methods of forming the same |
| US9705466B2 (en) * | 2015-02-25 | 2017-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with guard ring coupled resonant circuit |
| CN109950134B (zh) * | 2019-03-19 | 2022-01-21 | 中国科学院上海高等研究院 | 具有氧化物薄膜的结构及其制备方法 |
| US11251261B2 (en) * | 2019-05-17 | 2022-02-15 | Micron Technology, Inc. | Forming a barrier material on an electrode |
| US11605704B1 (en) * | 2021-10-08 | 2023-03-14 | Nanya Technology Corporation | Capacitor array and method for forming the same |
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| US6458645B2 (en) * | 1998-02-26 | 2002-10-01 | Micron Technology, Inc. | Capacitor having tantalum oxynitride film and method for making same |
| US6207561B1 (en) * | 1998-09-29 | 2001-03-27 | Texas Instruments Incorporated | Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication |
| KR100371142B1 (ko) * | 1998-12-30 | 2003-03-31 | 주식회사 하이닉스반도체 | 반도체소자의캐패시터형성방법 |
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| US6194265B1 (en) * | 1999-07-22 | 2001-02-27 | Vanguard International Semiconductor Corporation | Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure |
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| KR20040059761A (ko) | 2004-07-06 |
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