CN1244972A - 发送和接收链接码数据的方法和装置 - Google Patents
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
Abstract
链接码数据中,采用来自分组译码器的经正确译码的码字来提高卷积译码器的性能。在接收到该码字的所有码元之前,有时可以对码字进行正确译码。早期对码字进行译码使得即使还没有接收到码元也可以正确地重新产生整个码字。整个纠正码字可以由卷积译码器用来去除格网的分支,从而改进格网中先前数据位和未来数据位的译码。根据某些接收码字已被正确译码的知识,还可以使卷积译码器的回链距离较短。最后,可以免除发送还未被接收到用以正确译码码字的奇偶码元,以提高整个传输速率。
Description
I.发明领域
本发明涉及数据通信。更确切地说,本发明涉及采用链接编码的改进的新颖通信系统。
II.相关技术的描述
由于数字通信的出现和通过减损且限带信道发送大量数据的需要,使得需要对数字数据进行编码以便正确地进行数据接收具有重要的意义。数据传输通常因传输信道的减损即传输带宽内的加性噪声和寄生信号而受阻。发射功率因实际考虑而受到限制,传输的信号因路径损耗而衰减并且在到达接收机前因其他的现象如多径而失真。数字通信系统的设计要求判断接收机所能工作的较差状态下的信号质量。测量该信号质量,按每位能量对噪声的比值(Eb/No)衡量,并通过发射功率、路径损耗以及噪声和干扰来进行判断。将产生所要求的性能水平的Eb/No作为系统阈值电平。
根据该阈值电平,可以计算任何一个数字传输方案(如二相移相键控(BPSK)、四相移相键控(QPSK)或正交振幅调制(QAM))的误差几率(PE)。通常,所选传输方案的PE是不适用的。PE的提高通过在发送前对数字数据进行编码以及在接收机处对数据进行译码来实现。编码方案由应用要求和信道特性确定。编码要考虑到可以用有效数据速率下降较少的代价进行传输数据的检错和纠错。
采用分组编码和卷积编码等两种编码来提高PE。卷积编码提供良好的纠错能力,但通常输出相关的突发差错。同时,维特比译码器支持软判决的使用,以在使硬件复杂程度的增加最小的情况下改进性能。分组码在与恰当程度的交错组合时已加入突发差错处理能力。事实上,单独的纠错Reed-Solomon分组码可以处理一个码元内的任何突发差错。当仅有卷积编码不能产生所要求的编码增益时,可以采用含有卷积码和分组码的链接码。
Reed-Solomon码是一种强有力的非二进制循环线性分组码,它对任何具有相同输入(k)和输出(n)分组长度的线性码实现值最大的最小距离(dmin)。本申请文件中,采用高端码元来表示分组码的变量,而用低端码元来表示卷积码的变量。Reed-Solomon编码在本领域中是人们所熟知的,该专题的讨论见一些参考文献,包括S.Lin和D.Costello的“Error Control Coding:Fundamental andApplications”(Prentice Hall,1985,第171-176页)。在非二进制码中,将m个位组合起来形成一个码元。对于一个(n,k)Reed-Solomon码,将k个数据码元的分组编码成n个编码码元的分组,称为Reed-Solomon码字。(n,k)Reed-Solomon码能够校正n个码元中多达(n-k)/2个码元的差错。由于n个编码码元是对k个数据码元传送的,所以编码率(或数据速率的减小)是k/n。
在一种系统分组码中,k个数据码元形成码字的开头k个编码码元。按照生成多项式g(x)通过k个数据码元的线性组合形成n-k个奇偶码元。由于Reed-Solomon码的线性、系统性和循环性,可以用简单的移位寄存器和组合逻辑来实现编码处理。译码处理中的第一个步骤是根据接收的n个编码码元计算一组校正子。校正子表示码元差错的位置和值。具体而言,用这些校正子计算差错位置多项式的系数σ(x),并且由该系数计算差错定位值Xi和差错值Yi。由差错定位值和差错值,确定和纠正有差错的码元。
1/N比率的卷积编码器将每一输入的位按照一组N个生成多项式编码成N个编码位,称为编码分支。每一生成多项式G(x)计算一个编码位。将N个编码位组合成一个N位的编码分支。编码器的约束长度K是编码处理中使用的数据位的数目,并确定编码的纠错能力。长的约束长度K具有较好的性能,但硬件和计算复杂。一个状态用K-1个先前输入二进制位表示,因而有2K-1种状态。对于2K-1个状态中的每一个状态,一个‘0’或‘1’输入编码位会产生两个编码分支中的一个分支。由于每一输入为被编码成N个编码位,所以卷积编码器的编码率是1/N。其他的编码率可以通过减缩编码位从1/N码中得到。收缩码的完全处理见J.Cain、G.Clark和J.Geist的论文“Punctured Convolutional Codes ofRate(n-1)/nand Simplified Maximun Likelihood Decoding”(IEEE Transaction on InformationTheory,IT-25,pgs 97-100,Jan 1979)。
采用维特比算法在接收机处对发送编码分支进行译码。有关维特比译码器的理论和操作的讨论见A.Viterbi在IEEE Transaction on Communication Technology,Vol COM19,no.5,Oct 1971,pgs 821-835中的论文:“Convolutional Codes andTheir Performance in Communication System”。在有关信道噪声的某些假设下,维特比算法执行发送数据路径的最大似然译码。对于每一接收编码分支,计算进入每一状态的所有分支的分支度量,并加到相应的先前路径度量上。选择进入每一状态的最佳路径,并存储作为新的度量。将选择的路径存储在路径存储器中。1983年9月在Phoenic AZ举行的第六届数字卫星通信的国际会议上发表的“Development of Variable Rate Viterbi Decoder and its PerformanceCharacteristics”中Y.Yasuda等人指出,具有最低路径度量的幸存路径都在某一回链深度以后汇聚到相同的路径。因此,通过对路径反向跟踪至少一段回链距离就得到经维特比译码的位。
采用交错器和解交错器来对付信道特性,并使编码有效性最大。在非无记忆信道的系统中,接收机处的位差错是突发发生的。当维特比译码器输入含有非突发类型的差错时,维特比译码器的性能较好。维特比译码器之前的解交错器扩展信道突发差错并‘白化’这些差错。同时,维特比译码器具有在译码过程中输出突发的相关差错的趋势。所以,维特比译码器以后的解交错器将来自维特比译码器的突发差错扩展到各Reed-Solomon码字。解交错器的深度确定将由系统成功处理的突发差错的长度。
通常,在设计了通信系统以后,按照链接码对数据进行编码和发送,对所有的数据位进行编码,并发送所有的编码位。
发明概述
本发明是一种用于反馈链接编码的改进的新颖传输方案。按照本发明,数据用由分组码和卷积码组成的链接码进行编码和译码。编码后的数据经调制、发送、接收和解调。当判断一部分的接收数据是正确的时候,将这些接收数据应用于其他部分的接收数据的译码,以提高整个性能。
本发明的目的是采用已被成功译码的Reed-Solomon码字来提高维特比译码器的性能。Reed-Solomon码字的译码经常可以用填充删除码元译码在接收到所有该码字的奇偶码元之前完成。下文详细讨论这种译码。实质上,还未被接收的每一奇偶码元中填有删除码元,最好是全零码元0,并采用标准Reed-Solomon译码算法来纠证差错和删除码元。随后用译码所得Reed-Solomon码字中的码元去除维特比译码器所用译码格网中的路径。
采用早译码的Reed-Solomon码字来产生该码字还未被接收的丢失的其余奇偶码元。产生的奇偶码元可以由维特比译码器用来去除从译码格网产生的某些未来分支。所以,维特比译码器的某些未来的相加/比较/选择(ACS)操作就不需要了。免除ACS操作在对其他Reed-Solomon码字中一部分码元的未来二进制数字进行译码时提高了维特比译码器的可靠性。另外,Reed-Solomon译码器可以纠正由维特比译码器提供给它的先前接收的码元。该信息可以随后用来去除译码格网以前的分支,以提高对其他Reed-Solomon码字中部分码元的其他以前的二进制数字译码中维特比译码器的可靠性。
本发明的另一个目的是通过消除来自Reed-Solomon编码器的不必要奇偶码元的传输,提高有效传输数据速率。通过接收的Reed-Solomon码字的早期译码,接收机可以将信号发送到发射机,确认正确接收到了码字,并请求从发送中去除该码字的未来的奇偶码元。发射机可以通过从进一步的编码中去除奇偶码元来为该请求服务,或继续对奇偶码元进行卷积编码,但阻止相应于那些奇偶码元的编码位的发送。另外,发射机也可以在相应于这些奇偶码元的时间内关断。动作的选择取决于系统的要求和实施的复杂性。
参阅以下的说明、描述权利要求书和附图,将会更清楚地理解本发明的上述及其他目的、特征和优点。
附图简述
下面通过附图对本发明的详细描述,读者将会更清楚地理解本发明的特征、目的和优点,图中,相同的标号表示的意义相同。其中:
图1是数字传输系统的方框图;
图2是编码器的方框图;
图3是可变速率Reed-Solomon编码器的方框图;
图4是可变速率Reed-Solomon编码器后的第一个交错器的图;
图5是译码器的方框图;
图6是可变速率Reed-Solomon译码器前的第二个解交错器的图;
图7是可变速率Reed-Solomon译码器的方框图;
图8是Reed-Solomon译码器的方框图;
图9是比率(7,3),GF(23)Reed-Solomon编码器的图;
图10是Reed-Solomon校正子计算器的图;
图11是比率1/2,K=3卷积编码器的图;
图12是比率1/2,K=3卷积编码器的格网图;
图13是维特比译码器的方框图;
图14是速率1/2,K=3维特比译码器的格网图;
图15是维特比译码器的路径存储器的图。
较佳实施例的详细描述
将要用在本发明中的Reed-Solomon的特点是有时即使是在已经接收到相应于码字的所有码元前可以完成译码。下面的讨论显示这样的情况是怎么会发生的。尽管讨论中采用的是特定类型的译码器,但只要译码器具有相同的特性并且是在本发明的范围内,就可以采用其他类型的译码器。该典型实施例中,首先接收到的是相应于该数据的k个码元,相应于奇偶码元的n-k个码元是最后接收到的。
在本领域中人们知道,具有n-k个奇偶码元的Reed-Solomon码只要满足(2t+f)≤(n-k)可以纠正t个差错码元,并同时填充f个删除(或丢失)码元。另外,为了确保防止不正确的译码,按照坚持使(2t+f)≤(n-k-c),在此不等式设置“安全因子”,其中,c为正整数。c值较大,则不正确译码的可能性就较小。这样,我们将假设所选择的c值足够大,使得从系统的目标考虑,不正确译码的几率是能够接受的。
现在,假设接收到k个信息码元加上c’个奇偶码元,这里,c’是以后面要讲的方式与C相关的另一个正整数。译码器可以将尚未被接收的其余(n-k-c’)个奇偶码元当作删除,并试图对删除加上差错进行译码。还假设译算法则表示在具有(n-k-c’)个删除以外还有t个差错。如果(2t+n-k-c’)≤(n-k-c),则停止译码。在该式两端去掉(n-k)项得到不等式(2t+c)≤c’。如果对于严格小于(n-k)的c’值满足这一条件,则可以在接收到码字的所有奇偶码元之前完成译码。具体说来,假设在传输中出现了t个差错,并且译码器指示正确的传输差错数,则当已经接收到2t+c个奇偶码元时,译码器可以停止。
举例来说,假设选择安全因子是c=3,并且该码字中已经出现t个差错。译码可以在接收到2t+3个奇偶码元以后终断。这一数目可以远小于编码中的实际奇偶码元数。例如,如果在传输过程中没有出现差错,则可以在仅接收到n-k个奇偶码元中的3个以后完成译码。
采用已被成功译码的Reed-Solomon码字可以提高维特比译码器的性能。如上所述,经常可以在接收到该码字的所有奇偶码元之前完成Reed-Solomon码字的译码。经译码的Reed-Solomon码字中的码元可以用来去除维特比译码器使用的译码格中的路径。具体说来,在格网内的每一深度处,2K-1个状态中的每一个状态有两个从其开始的分支,一个分支相应于取1值的二进制数字,而另一个相应于取0值的二进制值。如果Reed-Solomon译码器判断该二进制数字等于1,则可以从格网中去掉相应于等于0的二进制数字的所有分支。相反,如果Reed-Solomon译码器判断该二进制数字等于0,则可以从格网中去掉相应于等于1的二进制数字的所有分支。由于这是发生在Reed-Solomon码字的所有奇偶码元已被维特比译码器作用之前的,所以该信息可以由维特比译码既用来修改以前的计算,又用来简化以后的计算。这可以被看作是Reed-Solomon译码器对维特比译码器进行的粗略纠正。粗略纠正有助于导引维特比译码器指向格网中的正确路径。另外,格网中分支的消除可以被看作是“修剪格网”。
具体说来,维特比译码器的导引能以两个途径来进行。如果早期将Reed-Solomon码字译码,则知道该码字的所有丢失的剩余(未来的)奇偶码元。所以,维特比译码器可以用译码码字的正确未来奇偶码元的知识从格网修剪未来分支。不需要维特比译码器的未来相加/比较/选择操作。修剪将来分支提高了在作为其他Reed-Solomon码字中一部分码元的未来二进制数字译码中维特比译码器的可靠性。另外,Reed-Solomon译码器可能已经纠正了由维特比译码器提供给它的一些先前接收的码元。所以,可以用译码码字的正确先前码元的知识从格网修剪的以前的分支。修剪过去的分支提高了在作为其他Reed-Solomon码字中一部分码元的其他过去二进制数字译码中维特比译码器的可靠性。
图1描绘的是本发明的数字传输系统的方框图。一种这样的系统是码分多址(CDMA)通信系统。该典型的实施例中,数据源2含有大量要传送到移动站16的信息,如计算机程序等。数据源2将数据发送到基站4。基站4对数据进行编码,并调制译码数据用于发送。在该典型实施例中,调制是按照CDMA调制格式进行的,见下述转让给本发明的受让人的美国专利中的描述:标题为“SpreadSpectrum Multiple Access Communication System Satellite or TerrestrialRepeaters”的美国专利4,901,307和标题为“System and Mothod for GeneratingSignal Waveforms in a CDMA Cellular Telephone System”的美国专利5,103,459。二专利在此按参考文献编入。经调制的信号由天线6在前向信道10发送。经传送的信号由与移动站16相连的天线14接收。移动站16解调该信号并对数据进行译码。本典型实施例中,CDMA系统是全双工的通信系统。移动站16可以在独立的后向信道12上向基站4发送数据和请求。
图2是编码器系统的方框图。数据源2将数据发送到可变码率Reed-Solomon编码器24,而该编码器24将k个数据码元的分组编码成n个编码码元的分组。由于Reed-Solomon码是系统性的,所以开头的k个编码码元是k个数据码元,而其余的n-k个编码码元是奇偶码元。本典型实施例中,k个数据码元的预定长度可变,但输出码字具有固定长度n。将可变码率Reed-Solomon编码器4输出的码字提供给第一交错器26。本典型实施例中,第一交错器26是分组交错器,其中的码字码元按行存储,而按列读出。第一交错器26将码字新排序,使码元串行化成位流,并将位流发送到卷积编码器28。
卷积编码器的设计和实施在本领域中是人们熟知的。卷积编码器28将每一输入位编码成N个编码位。编码率(1/N)和约束长度K由系统设计选择,并且不会影响本发明的操作。从卷积编码器28输出的码位被提供到第二交错器30。第二交错器30将这些码位重新排序,并将这些位送到发射机32。发射机32执行滤波、放大和上变频。通过双工器38提供来自发射机32的信号,并由天线发射出去。
可变码率Reed-Solomon编码器24如图3中所示。一组Reed-Solomon编码器1、1b、1c至1L用不同的Reed-Solomom编码率对输入数据进行编码。所要求的Reed-Solomon编码器输出由控制MUX 40选择。再参见图2,控制处理器36判断数据要如何分组编码,命令数据源2将需要量的数据提供给可变码率Reed-Solomon编码器24,并通过控制MUX 40选择恰当的Rd-Solomon编码器1的输出。例如,控制处理器36可以命令Reed-Solomon编码器1处理第一组k1个数据码元,命令Reed-Solomon编码器1b处理下一个分组k2个数据码元,等等,直到第一个交错器26被填满。
图4绘出的是第一交错器26在被填满以后的内容。将来自可变码率Reed-Solomon编码器24的码字按行写入第一交错器26,先写入数据码元,最后写入奇偶码元。本较佳实施例中,将连续的码字写入连续的行中。在填满了第一个交错器26以后,按列读出数据,首先读出数据码元。在图4所示的典型的第一交错器中,从第一个交错器中读出的码元依次是a1、b1、c1等,读出的最后码元是pd9、pe4和pf6。
移动站16中的译码器系统的方框图如图5所示。发射的信号由天线14接收,并通过双工器102转接到接收机104的路由。接收机104对接收的信号进行下变频、放大、调制和滤波。从接收机104输出的数字数据被送到第一解交错器106。第一解交错器106执行第二交错器30的逆操作。可使第一解交错器106的规模大于第二交错器30的规模,以适应来自接收机104的软判决。第一解交错器106将数据提供到维特比译码器108。
卷积译码在本领域中是人们所熟知的,并且任何格状译码器都可执行卷积编码数据的译码。本较佳实施例中,利用维特比译码器进行卷积译码。维特比译码器108的输出被发送到第二解交错器110。第二解交错器110执行第一交错器26的逆运算,即,将来自维特比译码器108的数据位组合成编码码元,将码元按列写入第二解交错器110,并按行读出码元。第二解交错器110将编码码元送到可变码率Reed-Solomon译码器112。可变速率Reed-Solomon译码器112一接收到编码码元即开始对接收的码字进行译码。
图6中示出的是部分填充的第二解交错器110的典型结构。将来自维特比译码器108的数据位组合成码元,并按列写入第二解交错器110。所以,行1列1接收第一个被接收的码元a1,行2列1接收第二个被接收的码元b1,等等。来自第二解交错器110的数据按行读出。本较佳实施例中,数据是在填满一行以后立即从第二解交错器110读出的。可变码率Reed-Solomon译码器112在开头的编码码元被发送到该译码器以后立即开始进行译码。
如图7所示,可变码率Reed-Solomon译码器112包含一组Reed-Solomon译码器1 01、101b、101c至101L。可变码率Reed-Solomon译码器112具有每一发射码字编码率(n,k)的先验知识。由控制MUX122选择恰当的Reed-Solomon译码器101。
如图8所示,每一Reed-Solomon译码器101由缓冲器124、校正子计算器126、差错定位值-差错值计算器128、码元纠正电路130和差错检测电路132。接收的码元存放在缓冲器124内,并进入校正子计算器126。当接收到所有的k个信息码元和m(m=c,c+1,c+2,…,n-k)个奇偶码元时,由差错定位值-差错值计算器128处理校正子计算器的内容。一旦差错定位值-差错值计算器128表示的差错不超过(m-c)/2时,就将还未接收的这些差错的位置和值以及n-k-m个奇偶码元的值传送到码元纠正电路130。码元纠正电路130接着校正被判断已经发生的差错、填入丢失的奇偶码元,并输出经纠正的码字。如果接收到了所有的n-k个码元,并且差错数被认为是大于(n-k-c)/2,则差错检测电路132输出表示不可纠错的信号。
在第一个实施例中,在判断码字已被正确译码以后,Reed-Solomon译码器101产生该码字的其余奇偶码元。正象在基站4处执行的那样,通过用Reed-Solomon编码器对该码字经纠正的数据码元进行编码,可以产生还未被接收的奇偶码元。将产生的奇偶码元提供到维特比译码器108。维特比译码器108去除与这些产生的奇偶码元相应的格网分支。也可以侧重加权分支度量,使有利于产生的奇偶码元,并反应在路径度量中。这就迫使回链路径通过这些已知的正常码元。所以,正确译码码字的知识有助于其他码字的译码。
在第二个实施例中,正确译码的码字也由维特比译码器108用来对先前的数据进行再译码。再译码是通过确定已知的译码码元在维特比译码器108的路径存储器228中的位置并去除格网中的某些分支来执行的。另外,通过对相应于译码位的分支侧重加权,维特比译码器108还可以替换相应于这些已知译码码元的位的路径度量。这就迫使回链通过这些已知的正常码元。
在第三个实施例中,可变码率Reed-Solomon译码器112将正确译码的码字通知消息发生器114(见图5)。消息发生器114向基站4发送确认信号,并请求终断正确译码码字的奇偶码元的发送。消息发生器114向发射机116发送命令。发射机116对命令进行调制,放大调制后的信号,并通过双工器102转接到天线14。天线14发射该信号。
在如图2所示的基站一侧,移动站16发射的信号由天线8接收,并选择通过双工器38转接到接收机子系统34。接收机子系统34对信号进行滤波、放大和解调,以检索来自消息发生器114的请求。接收机子系统34以几种方式中的一种方式服务于来自消息发生器114的请求。接收机子系统34可从第一交错器26清除正确译码码字的未发送Reed-Solomon奇偶码元,从卷积编码器28去除相应于非必要奇偶码元的卷积编码编码位,或在相应于非必要奇偶码元发送的时间内关断发射机32。预计可以采取前述步骤的任何一种组合。因为移动站16中的译码器能够产生正确译码码字的奇偶码元,所以,这些奇偶码元的发送将是多余的。
Reed-Solomon编码的理论和操作在本领域中是人们熟知的,其描述见前述参考文献。下面简述Reed-Solomon编码器和译码器,以帮助理解本发明。
对于在GF(23)上定义的比率(7,3)码,一种典型的Reed-Solomon编码器1如图9所示,其中,数据和编码码元用集合{0,1,α,α2,α3,α4,α5,α6}和生成多项式g(x)=x4+g3x3+g2x2+g1x+g0=x4+α3x3+x2+αx+α3定义。开始时,n-k个寄存器152、156、160和164复位到0,开关SW1 148闭合,并选择MUX1 168,使得数据码元可转接到输出。在移入了k个数据码元以后,SW1148打开,并且触发MUX1 168,使得可从寄存器152、156、160和164中读出n-k个奇偶码元。生成多项式g(x)的系数由GF乘法器140、142、144和146给出。GF加法器150、154、158和162和166是伽罗瓦域加法器。
在本较佳实施例中,一次从第一交错器26发送T码元的分组到卷积编码器28。为了对数据进行编码、发送和译码,确认正确的码字检测,并发送、接收和处理该确认,需要一段时间。也许逐位或者甚至逐码元对正确的码字检测作出反应是既不可能也是不切实际的。少量递增的改进要花费大量的开销。一次处理一组T个码元,使开销为最小,同时仅传送少量的过冗余。
Reed-Solomon早期译码的基本原理是将未接收到的码元看作是“删除”,而且用标准的Reed-Solomon译码算法纠正差错和删除。从原理上讲,伽罗瓦域中的任何一个码元可以代替还未接收到的每一码元。实际上,最早的进行填充删除码元译码的方法用全零码元来代替每一删除码元。替换以后,以普通的方法计算校正子、差错定位多项式、差错位置和差错值和删除值。下面通过一个具体的例子说明在全部接收到所有码元之前进行的Reed-Solomon码字的译码。
考虑一个在GF(8)上的(7,3)Reed-Solomon码。假设码字被表示成7个码元C6,C5,C4,C3,C2,C2,C1,或者表示成多项式C(x)=C6x6+C5x5+C4x4+C3x3+C2x2+C1x+C0。假设α是GF(8)的本原元素。并且假设码字满足四个等式:C(α)=0,C(α2)=0,C(α3)=0和C(α4)=0。
现在假设所接收的码元是R6,R5,R4,R3,R2,R1,R0,也可以用多项式R(x)=R6x6+R5x5+R4x4+R3x3+R2x2+R1x+R0来表示。对于这一(7,3)Reed-Solomon码,码元R6、R5、R4是三个信息码元,而R3、R2、R1、R0是四个奇偶码元。这一接收的多项式的校正子是:
S(αi)=R(αi),i=1,2,3,4。
计算这些校正子的一种方法是将S(αi)记为:
S(αi)=R(αi)=R6(αi)6+R5(αi)5+R4(αi)4+R3(αi)3+R2(αi)2+R1(αi)+R0
=(((((R6αi+R5)αi+R4)αi+R3)αi+R2)αi+R1)αi+R0
这一代数等式表明图10中所示的电路结构可以用来计算S(αi)。本例中四个校正子每一个都需要一个校正子计算器180。校正子计算器180中,乘法器182是伽罗瓦域乘法器,该乘法器将输入码元乘以域元素αi,GF加法器184是伽罗瓦域加法器,而寄存器186是可以存储来自GF(8)的任何元素的存储元件。
如果所有7个接收的码元都提供给Reed-Solomon译码器101,则接收的码元可定时输入到校正子计算器180内,并且以下面的顺序进行校正子计算。首先,将R6定时输入到校正子计算器180内,随后,时间寄存器186就含有R6。接着,将R5定时输入到校正子计算器180内,随后,时间寄存器186就含有(R6αi+R5)。接着,将R4定时输入到校正子计算器180内,随后,时间寄存器186就含有((R6αi+R5)αi+R4)。接着,将R3定时输入到校正子计算器180内,接着,时间寄存器186就含有(((R6αi+R5)αi+R4)αi+R3)。接着,将R2定时输入到校正子计算器180内,随后,时间寄存器186就含有((((R6αi+R5)αi+R4)αi+R3)αi+R2)。接着,将R1定时输入到校正子计算器180内,随后,时间寄存器186就含有(((((R6αi+R5)αi+R4)αi+R3)αi+R2)αi+R1)。最后,将R0定时输入到校正子计算器180内,随后,时间寄存器186就含有((((((R6αi+R5)αi+R4) αi+R3)αi+R2)αi+R1)αi+R0),这就是第i个校正子S(αi)。
现在假设只有四个码元R6,R5,R4,R3是已经被接收到的,并且丢失的三个码元被当作是删除。最明显的解决方案是用0来代替丢失的码元,从而R6,R5,R4,R3,0,0,0代表要被译码的码字。将该码字传送到校正子计算器180,并且如上所述对填有删除码元的码字进行相同的校正子计算。然而,这种方案有两个缺点。第一,尽管只有四个码元被处理,但校正子计算器180进行校正子计算需要7个时钟循环。第二,计算麻烦,取得用四个接收的码元R6,R5,R4,R3计算的校正子后,修改该校正子以得到用五个接收的码元R6,R5,R4,R3,R2产生的校正子。较简单的一种方法是校正子计算器180在处理了四个接收的码元R6,R5,R4,R3以后含有量(((R6αi+R5)αi+R4)αi+R3)。如果将接收的码元重新排序成0,0,0,R6,R5,R4,R3,则这一量是与其相称的校正子。所以,该部分校正子可以用作重新排序码字0,0,0,R6,R5,R4,R3的真实校正子。可用该部分校正子按标准Reed-Solomon译码算法求得差错位置和差错值,记住,接收的码元已在码字内重新排序。采用这种计算部分校正子的方法的优点是当接收下一个接收的码元(本例中为R2)时,该码元进入相同的校正子计算器180,以获得重新排序码字0,0,R6,R5,R4,R3,R2的校正子。因此,每一附加接收的奇偶码元可以递增更新该码字的四个校正子,从而在接收到该码字的所有码元之前,能够对Reed-Solomon码字进行填充删除码元的译码。
卷积编码在本领域中是人们所熟知的,并且卷积编码和维特比译码的理论和操作可以通过参考现有技术的对比文献来得知。下面简述卷积编码和维特比译码的实施,以便理解本发明。
典型的比率1/2,K=3卷积编码器28如图11所示。输入数据位是按照生成多项式G(x)来编码的,其中G0=7,而G1=5。每一输入位产生两个编码位C0和C1。该编码位对形成一个编码分支。
图12描述的是卷积编码器28的格网图。2K-1个状态是由图11中所示分别标为S0、S1和S2的K位寄存器202、204和206的K-1个最左侧位指定的。对于每一个状态,‘0’或‘1’输入位产生新的状态和相应的输出编码分支。
维特比译码器108的方框图如图13中所示,而译码器格网图212如图14中所示。由于每一位被编码成N位的编码分支,需要同步状态机220来正确地将输入位组成编码分支。对于每一编码分支,分支度量计算222计算接收的编码分支和进入每一状态的两个路径的分支之间的分支度量214。对于每一个状态,ACS阵列224通过将老的路径度量与分支度量214相加来计算进入该状态的两个路径的路径度量216。ACS阵列224随后比较进入该状态的两个路径的路径度量,并用最小路径度量216选择路径。用于每一状态的选择路径存储在路径存储器226中,而新的路径度量216存储在路径度量存储器228中。
图15代表维特比译码器路径存储器226。通过路径存储器226中对路径反向跟踪一段回链距离得到有效维特比译码器输出。回链距离是发送位序列。在本发明的一个实施例中,由于Reed-Solomon码提供检错,所以,可使回链距离比通常使用的短。
码字的Reed-Solomon译码可以在接收到第一个奇偶码元以后立即开始。对于k短的Reed-Solomon码字,如图6中所示的码字D,Reed-Solomon检测过程开始较早。在检测到一个正确译码的码字以后,该码字由维特比译码器108用来对其他的码字进行译码和再译码。例如,如果在接收到第三个奇偶码元pd3以后断言码字D被正确译码,那么Reed-Solomon编码器124可以产生后面的奇偶码元pd4、pd5、pd6等,并将这些产生的奇偶码元传送到维特比译码器108。所产生的奇偶码元在图15中用路径存储器226中的X标记表示。维特比译码器108在路径度量中对这些码元进行侧重加权,从而回链路径总是通过这些已知的正常码元。
类似地,Reed-Solomon编码器124可以将正确译码码字D的码元pd3、d2、pd1、d5等传送到维特比译码器108,用于进行再译码。已知的正常码元在图15中用路径存储器226中的Y标记表示。维特比译码器108在路径度量中对这些码元进行侧重加权,从而回链路径总是通过这些已知的正常码元。用经再译码的维特比译码器输出更新第二解交错器110。
前述较佳实施例的描述使得本领域中的技术人员能够制造或使用本发明。在没有发明专门人员的帮助下,本领域中的技术人员能够对这些实施例进行各种修改,而且可以将其中的基本原理用于其他的实施例。所以,本发明并非仅限于这些实施例,读者应当从最大的范围来理解所揭示的原理和新特征。
Claims (18)
1.一种接收链接码数据的装置,其特征在于,它包含:
第一译码器,用来接收信号并按照第一译码格式对所述信号进行译码,以提供第一译码数据;
分组译码器装置,用来接收所述第一译码数据、检测所述第一译码数据中不存在差错,并且在检测到没有差错存在时将纠正信号提供到所述第一译码器;
其中,所述第一译码器按照所述纠正信号对所述信号的其余部分进行译码。
2.如权利要求1所述的装置,其特征在于,所述第一译码器是格状译码器。
3.如权利要求2所述的装置,其特征在于,所述格状译码器是维特比译码器。
4.如权利要求1所述的装置,其特征在于,所述分组译码器是Reed-Solomon译码器。
5.如权利要求1所述的装置,其特征在于,所述分组译码器是可变码率Reed-Solomon译码器。
6.如权利要求1所述的装置,其特征在于,它还包含一个介于所述第一译码器装置和所述分组译码器装置之间用于重新对所述第一译码数据的码元进行排序的的解交错器装置。
7.如权利要求2所述的装置,其特征在于,所述格子结构译码器具有是所述纠正信号的函数的回链距离。
8.一种从远端站接收链接码数据的装置,其特征在于,它包含:
第一译码器,用来接收信号并按照第一译码格式对所述信号进行译码,以提供第一译码数据;
分组译码器装置,用来接收所述第一译码数据、检测所述第一译码数据中的差错,并提供表示所述译码数据中不存在差错的信号;
发射机装置,用来接收表示是否存在差错的信号,并根据所述表示不存在差错的信号,向所述远端站提供控制信号。
9.一种接收链接码数据的装置,其特征在于,它包含:
第一译码器,用来接收信号并按照第一译码格式对所述信号进行译码,以提供第一译码数据;
分组译码器装置,用来接收所述第一译码数据、检测所述第一译码数据中不存在差错,并且在检测到没有差错存在时将纠正信号提供到所述第一译码器;
其中,所述第一译码器按照所述纠正信号对所述信号的先前部分进行再译码。
10.一种接收链接码数据的方法,其特征在于,它包含:
首先按照第一译码格式对接收的信号进行译码,以提供第一译码数据;
对所述译码数据进行分组译码;
检测在所述第一译码数据中不存在差错;
在检测到不存在差错时向所述第一译码步骤提供纠正信号;
按照所述纠正信号对所述接收信号的其余部分进行译码。
11.如权利要求10所述的方法,其特征在于,所述第一译码步骤是格状译码步骤。
12.如权利要求11所述的方法,其特征在于,所述格状译码步骤是维特比译码步骤。
13.如权利要求10所述的方法,其特征在于,所述分组译码步骤是Reed-Solomon译码步骤。
14.如权利要求10所述的方法,其特征在于,所述分组译码步骤是可变码率Reed-Solomon译码步骤。
15.如权利要求10所述的方法,其特征在于,它还包含:介于所述第一译码步骤和所述分组译码步骤之间用以对所述第一译码数据的码元进行重新排序的解交错步骤。
16.如权利要求11所述的方法,其特征在于,所述格状译码步骤具有是所述纠正信号的函数的回链距离。
17.一种从远端站接收链接码数据的方法,其特征在于,它包含:
按照第一译码格式对接收信号进行译码,以提供第一译码数据;
对所述第一译码数据进行分组译码;
检测所述第一译码数据中的差错;
提供表示所述第一译码数据中不存在差错的信号;
根据所述表示不存在差错的信号,向所述远端站发送控制信号。
18.一种接收链接码数据的方法,其特征在于,它包含:首先按照第一译码格式对接收的信号进行译码,以提供第一译码数据;对所述第一译码数据进行分组译码;检测所述第一译码数据中不存在差错;在检测到不存在差错时向所述第一译码步骤提供纠正信号;按照所述纠正信号对一部分所述第一接收信号进行再译码。
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