CN1236978A - 形成平坦内金属介电层的方法 - Google Patents

形成平坦内金属介电层的方法 Download PDF

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CN1236978A
CN1236978A CN98116059A CN98116059A CN1236978A CN 1236978 A CN1236978 A CN 1236978A CN 98116059 A CN98116059 A CN 98116059A CN 98116059 A CN98116059 A CN 98116059A CN 1236978 A CN1236978 A CN 1236978A
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罗吉进
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Abstract

一种在导电金属结构上形成平坦内金属介电层的方法包括:在导电金属结构上形成衬氧化层;低介电材料层;未固化低介电材料层;未固化硅氧烷层;在未固化硅氧烷层与未固化低介电材料层上实施CMP,CMP停止于固化低介电材料层的表面,因此在导电金属结构的间隔中残留部分未固化低介电材料层;将未固化低介电材料层的残留部分固化;以及在固化低介电材料层与固化后的残留部分上方形成帽盖氧化层。

Description

形成平坦内金属 介电层的方法
本发明涉及一种半导体的制造方法，特别是涉及一种形成平坦内金属介电层(intermetal dielectric layer)的方法。
内金属介电层一般被使用来将如金属层的导体结构与之后沉积的导电层隔离。内金属介电层也被用来作为平坦化用途。通常现有形成内金属介电层的工艺包含将多层绝缘层沉积于底下的金属层的上方。
在一现有工艺中，由二氧化硅所组成的一厚衬氧化物(thick liner oxide)先覆盖金属层，接着再覆盖经烘烤(baked)与固化(cured)的一低介电(lowdielectric)材料层。在固化的低介电材料层上实施一化学机械研磨(chemicalmechanical polishing,CMP)。最后覆盖一第二氧化硅层，以完成内金属介电层。一平坦化工艺，如CMP，被用以改善内金属介电层的全面性平坦化。之后，多层绝缘层被限定图案，蚀刻形成直通至下层金属层的介层洞(viaholes)。
现有形成内金属介电层的方法有很多问题。在CMP工艺中，固化的低介电材料层的移除率非常低；而且无法有效使用终点侦测(endpointdetection)。另外，由于使用厚衬氧化物的缘故，内金属间的电容量(capacitance)偏高。
其它现有工艺采用与如上述讨论的第一现有工艺相同的步骤，除了省略在固化的低介电材料层上的CMP步骤并改采用在第二氧化硅层上实施CMP步骤以外。此现有工艺也有很多问题。与上述第一现有工艺相似，此工艺也不能有效利用终点侦测。另外，此现有工艺引起污染介层洞(poisoned via)的问题。再者，因为没有在固化低介电材料层上实施CMP，所以有一厚的低介电材料层存在于导体结构的上方，使得低介电材料层的热传导性(thermalconductivity)非常低，此将造成金属层的可靠性(reliability)问题。
形成平坦内金属介电层的方法需要消除前述的问题。
揭露一种在导电金属结构上形成平坦内金属介电层的方法。此方法包括下列步骤：在导电金属结构上形成一衬氧化层；在衬氧化层上方形成一固化低介电材料层；在固化低介电材料层上方形成一未固化低介电材料层；在未固化低介电材料层上方形成一未固化硅氧烷层；在未固化硅氧烷层与未固化低介电材料层上实施一化学机械研磨，化学机械研磨停止于固化低介电材料层的表面，因此在导电金属结构的间隔中残留部分未固化低介电材料层；将未固化低介电材料层的残留部分固化；以及，在固化低介电材料层与固化后的残留部分上方形成一帽盖氧化层。
本发明的前述和其它目的、特征和优点，经由以下优选实施例的详细叙述并配合附图将更为显而易懂。附图中：
图1-3是用以说明本发明的步骤的一种半导体基底剖面视图。
参照图1，一基底(substrate)100，其上形成多个导电结构(conductivestructure)102。可以理解，此“基底”术语可能包括一半导体晶圆、形成于晶圆之中的主动与被动元件、以及形成在晶圆表面上的薄膜层。因此，此“基底”术语表示包括在一半导体晶圆内所形成的元件，以及晶圆表面的薄膜层。
导电结构102通常为金属连线(metal interconnects)或任何其它导电结构。另外，导电结构102具有一位于导电结构102上的薄抗反射层(anti-reflective coating,ARC)104，此ARC104可以是氮化钛。再者，所示的导电结构102仅为示范，并不用以限制本发明。
依照本发明，首先在基底100与导电结构102上方沉积一薄衬氧化层106。衬氧化层106优选为厚度在300至800埃的二氧化硅，且优选是为以现有等离子增强化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)技术形成。衬氧化层106被作为提供高品质绝缘层之用，其与导体结构直接接触。
接着，以如旋涂式玻璃(spin on glass,SOG)涂布法的现有技术，在衬氧化层106上涂布一第一低介电材料层108。此第一低介电材料层108的厚度优选约为800至2000埃。固化第一低介电材料层108以降低在后续工艺中光致抗蚀剂层剥除(stripping)期间所造成SOG薄膜吸收水气，并且移除SOG薄膜中的溶剂(solvent)，此固化工艺是众所周知的，因此，于此不再赘述。
再来，以旋涂式玻璃涂布法的现有技术，在第一低介电材料层108上涂布一第二低介电材料层110，第二低介电材料层110优选厚度约为2000至8000埃，此时，不固化第二低介电层料层110。
接着，以旋涂式玻璃涂布法的现有技术，在第二低介电材料层110上涂布一硅氧烷层112，硅氧烷层112是不固化的且其优选厚度约为1000至2000埃，硅氧烷层112可以降低后续化学机械研磨(CMP)的碟形凹状效应(dishingeffect)。
参照图2，实施一氧化物CMP，且控制使停止于第一低介电材料层108的表面，在CMP工艺中未固化的低介电材料层的移除率为3900埃/分钟，而固化的低介电材料层的移除率为200埃/分钟，因为未固化的低介电材料层对固化的低介电材料层的移除率比几乎为20比1，因此可有效应用终点侦测，在结束CMP之后，以现有技术将未固化的低介电材料层的残留部分110a固化。
参照图3，沉积一帽盖氧化层114，优选的是利用PECVD技术沉积，帽盖氧化层114优选是二氧化硅且厚度约为2000至8000埃，帽盖氧化层114提供一高品质绝缘体且直接与后续沉积的导体结构接触，因此形成平坦内金属介电层。
除了可以有效利用终点侦测的优点以外，依照本发明形成内金属介电层的方法尚有许多优点，由于本发明的薄衬氧化物的缘故，内金属间电容量较低，而如上所述的第一现有方法，因为将衬氧化物作为CMP的停止层，因此其必须具足够厚度以保护导电结构102，因此，造成内金属间的电容量较高。另外，未固化的低介电材料层的移除率非常高(为3900埃/分钟)，可有效改善生产量(throughput)。再者，因为未固化的硅氧烷层的移除率为2000埃/分钟，因此硅氧烷层112可以改善CMP的碟形凹状效应，此外，藉由低介电材料层的CMP，可降低污染介层洞，另外，由于在CMP之后才沉积帽状氧化层，内金属介电层表面上不会有刮痕。
虽然本发明已结合优选实施例揭露如上，但是其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作出各种更动与润饰，因此本发明的保护范围应当由后附的权利要求界定。

Claims (5)

1．一种在导电金属结构上形成平坦内金属介电层的方法，该方法包括下列步骤：
在该导电金属结构上形成一衬氧化层；
在该衬氧化层上方形成一固化低介电材料层；
在该固化低介电材料层上方形成一未固化低介电材料层；
在该未固化低介电材料层上方形成一未固化硅氧烷层；
在该未固化硅氧烷层与该未固化低介电材料层上实施一化学机械研磨，该化学机械研磨停止于该固化低介电材料层的表面，因此在该导电金属结构的间隔中残留部分该未固化低介电材料层；
将该未固化低介电材料层的残留部分固化；以及
在该固化低介电材料层与固化后的残留部分上方形成一帽盖氧化层。
2．如权利要求1所述的方法，其中，该衬氧化层的厚度约为300至800埃。
3．如权利要求1所述的方法，其中，该固化低介电材料层的厚度约为800至2000埃。
4．如权利要求1所述的方法，其中，该未固化低介电材料层的厚度约为2000至8000埃。
5．如权利要求1所述的方法，其中，该未固化硅氧烷层的厚度约为1000至2000埃。
CN98116059A 1998-05-26 1998-07-15 形成平坦内金属介电层的方法 Expired - Lifetime CN1103492C (zh)

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CN1302524C (zh) * 2002-09-27 2007-02-28 上海华虹（集团）有限公司 有机聚合物低介电材料刻蚀后的湿法去胶工艺
CN103094194A (zh) * 2011-11-01 2013-05-08 无锡华润上华科技有限公司 金属层间介质的形成方法及金属层间介质结构

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US6200901B1 (en) 1998-06-10 2001-03-13 Micron Technology, Inc. Polishing polymer surfaces on non-porous CMP pads
US6384466B1 (en) * 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
US6284560B1 (en) 1998-12-18 2001-09-04 Eastman Kodak Company Method for producing co-planar surface structures
US6211050B1 (en) * 1999-03-03 2001-04-03 Chartered Semiconductor Manufacturing Ltd. Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates
TW428248B (en) * 1999-09-30 2001-04-01 Taiwan Semiconductor Mfg Structure and method of metal conductive layer and dielectric layer
DE10134099A1 (de) * 2001-07-13 2002-10-17 Infineon Technologies Ag Bedeckung von Leiterbahnen einer integrierten Halbleiterschaltung durch zwei Deckschichten
KR100675895B1 (ko) * 2005-06-29 2007-02-02 주식회사 하이닉스반도체 반도체소자의 금속배선구조 및 그 제조방법
US8802569B2 (en) * 2012-03-13 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device
US10522365B2 (en) * 2016-01-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for reducing scratch defects in chemical mechanical planarization

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US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1302524C (zh) * 2002-09-27 2007-02-28 上海华虹（集团）有限公司 有机聚合物低介电材料刻蚀后的湿法去胶工艺
CN103094194A (zh) * 2011-11-01 2013-05-08 无锡华润上华科技有限公司 金属层间介质的形成方法及金属层间介质结构
CN103094194B (zh) * 2011-11-01 2016-01-13 无锡华润上华科技有限公司 金属层间介质的形成方法及金属层间介质结构

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