CN1250947A - 制造双重镶嵌接触窗的方法 - Google Patents

制造双重镶嵌接触窗的方法 Download PDF

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CN1250947A
CN1250947A CN98126568A CN98126568A CN1250947A CN 1250947 A CN1250947 A CN 1250947A CN 98126568 A CN98126568 A CN 98126568A CN 98126568 A CN98126568 A CN 98126568A CN 1250947 A CN1250947 A CN 1250947A
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罗吉进
杜友伦
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SHIDA INTEGRATED CIRCUIT CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers

Abstract

一种在基底上制造双重镶嵌金属内连线以及接触窗开口结构的方法包括:在基底上依次形成第一氧化层、第一氮化物层;图案化并蚀刻第一氮化物层以形成接触窗开口;在接触窗开口及第一氮化物层上形成第二氧化层、光刻胶层;图案化并显影以暴露出与接触窗开口具有不同尺寸的沟渠开口;以光刻胶层为掩模,蚀刻第二氧化层,以第一氮化物层为掩模,蚀刻第一氧化层,形成双重镶嵌开口;移除光刻胶层;形成氧化物间隙壁、沉积导电层。

Description

制造双重镶嵌接触窗的方法
本发明涉及一种金属内连线(Metal Interconnects)与介层窗(Vias)的制造方法，且特别是涉及一种双重镶嵌接触窗(Dual Damascene Contacts)的制造方法。
镶嵌是一种在绝缘层中形成凹槽(Grooves)，并将金属填入凹槽中以形成导线的内连线工艺。双重镶嵌是除了形成单一金属镶嵌的凹槽外，并且形成导电接触窗或介层窗开口的一种多层内连线工艺。
标准的双重镶嵌工艺是在导电结构上沉积第一氧化层。之后，在第一氧化层上方形成一层阻挡层。在阻挡层上形成第一图案化光致抗蚀剂层。接着，以第一图案化光致抗蚀剂层作为图案限定阻挡层，并且移除第一光致抗蚀剂层。
接着，形成一第二氧化层覆盖于阻挡层。于第二氧化层上形成一层第二图案化光致抗蚀剂层。蚀刻第一氧化层与第二氧化层以形成一个双重镶嵌开口。蚀刻第一氧化层是以阻挡层为图案，并以导电结构为蚀刻终止层。蚀刻第二氧化层则是以第二图案化光致抗蚀剂层为图案，并以硬掩模为蚀刻终止层。以氧等离子移除第二光致抗蚀剂层。然而，氧等离子会损坏在双重镶嵌开口中第一氧化层与第二氧化层暴露出来的表面。
因此，需要一种优良的形成双重镶嵌接触窗的方法。
根据本发明的一个方面，提供一种在基底上制造双重镶嵌金属内连线以及接触窗开口结构的方法，其步骤包括：在该基底上形成一第一氧化层；在该第一氧化层上形成一第一氮化物层；图案化并蚀刻该第一氮化物层以形成一接触窗开口；在该接触窗开口及该第一氮化物层上形成一第二氧化层；在该第二氧化层上形成一光致抗蚀剂层；图案化并显影该光致抗蚀剂层以暴露出与该接触窗开口具有不同尺寸的一沟渠开口；以该光致抗蚀剂层为掩模，蚀刻该第二氧化层，并且以该第一氮化物层为掩模，蚀刻该第一氧化层，以形成一双重镶嵌开口；移除该光致抗蚀剂层；在该双重镶嵌开口中形成一氧化物间隙壁；以及在该双重镶嵌开口中沉积一导电层。
根据本发明的另一方面，提供一种在一基底上形成双重镶嵌结构的方法，包括下列步骤：在该基底上形成一衬氧化层；在该衬氧化层上形成一第一低介电常数介电层；在该第一低介电常数介电层上形成一盖氧化层；在该盖氧化层上形成一第一氮化物层；图案化并蚀刻该第一氮化物层以形成一接触窗开口；形成一第二低介电常数介电层至该接触窗开口及覆盖于该第一氮化物层；在该第二低介电常数介电层上形成一光致抗蚀剂层；图案化并显影该光致抗蚀剂层以暴露出与该接触窗开口具有不同尺寸的一沟渠开口；以该光致抗蚀剂层为掩模，蚀刻该第二低介电常数介电层，并且以该第一氮化物层为掩模，蚀刻该盖氧化层，该第一低介电常数介电层以及该衬氧化层，以形成一双重镶嵌开口；移除该光致抗蚀剂层；在该双重镶嵌开口中形成一氧化物间隙壁；以及在该双重镶嵌开口中沉积一导电层。
为使本发明的上述和其他目的、特征和优点能更明显易懂，下文特举一优选实施例，并配合附图作详细说明，其中：
图1至图6绘示根据本发明的一种在半导体基底上形成以重镶嵌开口的剖面示意图。
本发明将配合附图做详细说明。本发明提供一种形成双重镶嵌开口的方法。
请参照图1，在基底100上方已形成有导电结构102。“基底”一词应了解可能包括一个半导体晶圆，形成于晶圆上的有源元件与无源元件以及晶圆表面的薄膜层。因此，“基底”一词代表包括形成于半导体晶圆上的元件以及覆盖晶圆上的薄膜层。
导电结构102通常可为金属内连线或其他的导体结构。图中显示的导电结构102仅为例示，而非用以限制。
根据本发明，沉积一层衬氧化层104覆盖于基底100与导电结构102上。衬氧化层104的材质以二氧化硅为优选，其厚度大约为300埃至800埃，而且以现有的等离子加强化学气相沉积法(Plasma-Enhanced ChemicalVapor Deposition)形成为优选。衬氧化层104的作用为提供直接覆盖在导电结构102上的高品质绝缘体。
接着，以现有的技术在衬氧化层104上涂布一层第一低介电常数介电层106，低介电常数材质比如为旋涂式玻璃(Spin-On-Glass；SOG)。第一低介电常数介电层106的厚度以大约2000埃至8000埃为优选。之后，对第一低介电常数介电层106进行固化(Curing)步骤，以减少在后续步骤中移除光致抗蚀剂层时，第一低介电常数介电层106之水气吸收，并去除旋涂式玻璃薄膜中的溶剂，其中，光致抗蚀剂层是在后续掩模及蚀刻氧化层时使用。由于固化的步骤为现有方法，因此本文不再详加讨论。
在第一低介电常数介电层106上方形成一层绝缘层108(即为盖氧化层)。盖氧化层108的材质以二氧化硅为优选，而其形成的方法比如为等离子加强化学气相沉积技术。盖氧化层的厚度以大约4000埃至7000埃为优选。此外，对盖氧化层108作平坦化工艺以达到全面平坦的效果。平坦化的方法优选为使用化学机械研磨法(Chemical-Mechanical Polishing)。
之后，在盖氧化层108上形成一层第一氮化物层110。第一氮化物层110的厚度优选约500至1500埃，且优选为以等离子加强化学气相沉积法形成。另外，此第一氮化物层基本上由氮化硅(Si3N4)形成。
接着，在第一氮化物层110上涂布一层第一光致抗蚀剂层112，并进行显影，以形成接触窗开口114。此光致抗蚀剂层112具有的图案与欲形成接触窗114的位置一致。
请参照图2，在第一氮化物层110中形成一接触窗开口116。接触窗开口116虽然可为任意形状，但是以圆柱形为优选。光致抗蚀剂层112在蚀刻第一氮化物层110时作为掩模。
请参照图3，移除第一光致抗蚀剂层112。利用现有的技术，比如为旋涂式玻璃涂布法，沉积一层第二低介电常数介电层118至接触窗开口116及在第一氮化物层110上。第二低介电常数介电层118的厚度以2000埃至8000埃为优选。之后，对第二低介电常数介电层118进行固化(Curing)步骤，以减少在后续步骤中移除在蚀刻氧化层时作为掩模的光致抗蚀剂层时，第二低介电常数介电层118之水气吸收，并去除旋涂式玻璃薄膜中的溶剂。
接着，在第二低介电常数介电层118上形成一层第二氮化物层120。形成此第二氮化物层120的优选厚度约为500埃至1500埃，且优选为以等离子加强化学气相沉积法所沉积的氮化硅。
接着，在第二低电常数介电层120上涂布一层第二光致抗蚀剂层122。将此第二光致抗蚀剂层122进行图案化以及显影的步骤，以使沟渠开口124暴露出来。
请参照图4，蚀刻衬氧化层104、第一低介电常数介电层106、盖氧化层108、第二低介电常数介电层118以及第二氮化物层120，以形成一个双重镶嵌窗口126。其中，第二氮化硅层118与第二氮化物层120是以第二光致抗蚀剂层122为掩模，并以第一氮化物层110为蚀刻终止层进行蚀刻。而蚀刻第一低介电常数介电层106、衬氧化层104以及盖氧化层108的步骤则是以第一氮化物层110为掩模，并以导电结构102作为蚀刻终止层进行。
请参照图5，移除第二光致抗蚀剂层122。以化学气相沉积(CVD)法，沉积一层氧化层128至双重镶嵌开口126中并覆盖于第二氮化物层120上。其中，CVD氧化层128的形成以高密度氧等离子化学气相沉积法(HDPCVD)为优选。此CVD氧化层128厚度则以介于大约300埃至1000埃之间为优选。
请参照图6，蚀刻CVD氧化层128如以反应性离子蚀刻法，以在沿着双重镶嵌开口126的侧壁形成氧化物间隙壁128a。间隙壁128a防止第一低介电常数介电层106与第二低介电常数介电层118的出气(Outgassing)现象。
如此就完成了双重镶嵌开口。之后，沉积一层导电层以形成金属内连线结构，这个步骤为现有的方法，因此不再赘述。
虽然本发明已以一优选实施例说明如上，可了解任何在不脱离本发明之精神和范围内可作各种更动与润饰。

Claims (11)

1.一种在基底上制造双重镶嵌金属内连线以及接触窗开口结构的方法，其步骤包括：
在该基底上形成一第一氧化层；
在该第一氧化层上形成一第一氮化物层；
图案化并蚀刻该第一氮化物层以形成一接触窗开口；
在该接触窗开口及该第一氮化物层上形成一第二氧化层；
在该第二氧化层上形成一光致抗蚀剂层；
图案化并显影该光致抗蚀剂层以暴露出与该接触窗开口具有不同尺寸的一沟渠开口；
以该光致抗蚀剂层为掩模，蚀刻该第二氧化层，并且以该第一氮化物层为掩模，蚀刻该第一氧化层，以形成一双重镶嵌开口；
移除该光致抗蚀剂层；
在该双重镶嵌开口中形成一氧化物间隙壁；以及
在该双重镶嵌开口中沉积一导电层。
2.如权利要求1的方法，其中，该形成氧化物间隙壁的步骤包括：
在该双重镶嵌开口中沉积一第三氧化层；以及
回蚀刻该第三氧化层。
3.如权利要求1的方法，其中还包括在该第二氧化层以及该光致抗蚀剂层之间形成一第二氮化物层的步骤。
4.如权利要求3的方法，其中该第一氮化物层与该第二氮化物层是由氮化硅所形成。
5.如权利要求1的方法，其中该第一氧化层包括由一衬氧化层、一低介电常数介电层以及一盖氧化层所组成。
6.一种在一基底上形成双重镶嵌结构的方法，包括下列步骤：
在该基底上形成一衬氧化层；
在该衬氧化层上形成一第一低介电常数介电层；
在该第一低介电常数介电层上形成一盖氧化层；
在该盖氧化层上形成一第一氮化物层；
图案化并蚀刻该第一氮化物层以形成一接触窗开口；
形成一第二低介电常数介电层至该接触窗开口及覆盖于该第一氮化物层；
在该第二低介电常数介电层上形成一光致抗蚀剂层；
图案化并显影该光致抗蚀剂层以暴露出与该接触窗开口具有不同尺寸的一沟渠开口；
以该光致抗蚀剂层为掩模，蚀刻该第二低介电常数介电层，并且以该第一氮化物层为掩模，蚀刻该盖氧化层，该第一低介电常数介电层以及该衬氧化层，以形成一双重镶嵌开口；
移除该光致抗蚀剂层；
在该双重镶嵌开口中形成一氧化物间隙壁；以及
在该双重镶嵌开口中沉积一导电层。
7.如权利要求6的方法，其中该方法还包括一固化该第一以及该第二低介电常数介电层的步骤。
8.如权利要求6的方法，其中该方法还包括在该第二低介电常数介电层以及该光致抗蚀剂层之间形成一第二氮化物层的步骤。
9.如权利要求8的方法，其中该第一以及该第二氮化物层由氮化硅所形成。
10.如权利要求6的方法，其中该盖氧化层是由二氧化硅所形成。
11.如权利要求6的方法，其中该氧化物间隙壁是以一高密度等离子化学气相沉积法所形成的二氧化硅。
CN98126568A 1998-10-13 1998-12-30 制造双重镶嵌接触窗的方法 Expired - Lifetime CN1123920C (zh)

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