TW410425B - Method for forming dual damascene contacts - Google Patents
Method for forming dual damascene contacts Download PDFInfo
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- TW410425B TW410425B TW087121149A TW87121149A TW410425B TW 410425 B TW410425 B TW 410425B TW 087121149 A TW087121149 A TW 087121149A TW 87121149 A TW87121149 A TW 87121149A TW 410425 B TW410425 B TW 410425B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
410425 4 t 49t wf,d〇c:/006 A7 B7 五、發明説明(/) 本發明是有關於一種金屬內連線(Metal Interconnects) 與介層窗(Vias)的製造方法,且特別是有關於一種雙重鑲 嵌接觸窗(Dual Damascene Contacts)的製造方法。 鑲嵌是一種在絕緣層中形成凹槽(Grooves),並將金屬 塡入凹槽中以形成導線的內連線製程。雙重鑲嵌是除了形 成單一金屬鑲嵌的凹槽外,並且形成導電接觸窗或介層窗 開口的一種多層內連線製程。 標準的雙重鑲嵌製程是在導電結構上沉積第一氧化 層。之後,在第一氧化層上方形成一層阻障層。在阻障層 上形成第一圖案化光阻層。接著,以第一圖案化光阻層作 爲圖案定義阻障層,並且移除第一光阻層。 接著,形成一第二氧化層覆蓋於阻障層。於第二氧化 層上形成一層第二圖案化光阻層。鋪刻第一氧化層與第二 氧化層以形成一個雙重鑲嵌開口。蝕刻第一氧化層是以阻 障層爲圖案,並以導電結構爲蝕刻終止層。蝕刻第二氧化 層則是以第二圖案化光阻層爲圖案,並以硬罩幕爲蝕刻終 止層。以氧電漿移除第二光阻層。然而,氧電漿會損壞在 雙重鑲嵌開口中第一氧化層與第二氧化層暴露出來的表 面° 因此,需要一種較佳的形成雙重鑲嵌接觸窗的方法° 本發明揭露一種在基底上形成雙重鑲嵌結構的方 法。此方法包含的步驟有:形成一層襯k化層於基底上; 形成一層第一低介電常數介電層於襯氧化層上;形成一層 蓋氧化層於第一低介電常數層上;形成第一氮化物層於該 5 本紙乐尺度iiU]中固函家榀彳() Λ4現格(2〗0\ 297公釐1 " (誚先閣讀背面之注意事'^填寫本頁) .裝,. 410425 4 I 49tw f.doc/006 Β7 五、發明说明(2) 蓋氧化層上;圖案化並蝕刻第一氮化物層以形成一個接觸 窗開口;形成一層第二低介電常數介電層覆蓋第一氮化物 層並塡滿接觸窗開口;形成一層第二氮化物層於第二低介 電常數介電層上;於第二氮化物層上形成一層光阻層;定 義並顯影光阻層以暴露出與接觸窗開口具有不同尺寸的一 個溝渠開口;以光阻層爲罩幕,蝕刻第二氮化物層與第二 低介電常數介電層,並且以第一氮化物層爲罩幕,蝕刻蓋 氧化層、第一低介電常數介電層以及襯氧化層,以形成一 個雙重鑲嵌開口;移除光阻層;在雙重鑲嵌開口中形成氧 化物間隙壁;以及沉積一層導電層於雙重鑲嵌開口中。 圖式之簡單說明= 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明,其中: 第1圖至第6圖係繪示根據本發明之一種在半導體基 底上形成雙重鑲嵌開口的剖面示意圖。 圖式之標記說明: 100 :基底 102 :導電結構 104 :襯氧化層 106 :第一低介電常數介電層 10 8 :蓋氧化層 110 :第一氮化物層 112 :第一光阻層 η 先? 閱 讀' 背, 注 f >裝 if 腺 本紙張尺度適扪中困戌家#埤(<’NS ) Λ4現格(2】〇X25>7公釐) 4]49twf.doc/006 410425 A7 ^浸奵屮"^^^^-1·^扎合 M^ _____B7 五、發明説明()) 114、116 :接觸窗開口 118 :第二低介電常數介電層 1叩:第二氮化物層 122 :第二光阻層 124 :溝渠開口 126 :雙重鑲嵌接觸窗開口 128 :氧化層 128a:氧化物間隙壁 實施例 本發明將配合下列圖示做一詳細說明。本發明提供一 種形成雙重鑲嵌開口的方法。 請參照第1圖’在基底100上方已形成有導電結構 102。“基底”一詞應瞭解可能包括一個半導體晶圓,形成 於晶圓上的主動元件與被動元件以及晶圓表面的薄膜層^ 因此,“基底” 一詞代表包括形成於半導體晶圓上的元件 以及覆蓋晶圓上的薄膜層。 導電結構102通常可爲金屬內連線或是其他的導體結 構。圖中顯示的導電結構102僅爲例示,而非用以限制。 根據本發明’沉積一層襯氧化層104覆蓋於基底100 與導電結構102上。襯氧化層HM的材質以二氧化矽爲較 佳,其厚度大約爲300埃至800埃,而且以習知的電漿加 強化學氣相沉積法(Plasma-Enhanced Chemical Vapor Deposition)形成爲較佳。襯氧化層104的作用爲提供直接 覆蓋在導電結構102上的高品質絕緣體。 7 本紙張尺度適川中阐BS家榡蜱{ ('NS ) Λ4说格(2丨0X297公策1 ~~ ("先閲讀背面之注意事填寫本頁) 裝;
-1T 410425 4 l 49twf.doc/006 五、發明説明(子) 接著,以習知的技術在襯氧化層104上塗佈一層第一 低介電常數介電層106,低介電常數材質比如爲旋塗式玻 璃(Spirj-On-Glass ; SOG)。第一低介電常數介電層106的厚 度以大約2000埃至8000埃爲較佳。之後,對第一低介電 常數介電層丨06進行固化(Curing)步驟,以減少在後續步驟 中移除光阻層時,第一低介電常數介電層106之水氣吸收, 並去除旋塗式玻璃薄膜中的溶劑,其中,光阻層是在後續 罩幕及蝕刻氧化層時使用。由於固化的步驟爲習知方法, 因此本文不再詳加討論。 在第一低介電常數介電層106上方形成一層絕緣層 1〇8(即爲蓋氧化層)。蓋氧化層108的材質以二氧化矽爲較 佳,而其形成的方法比如爲電漿加強化學氣相沉積技術。 蓋氧化層的厚度以大約4000埃至7000埃爲較佳。此外, 對蓋氧化層108作平坦化製程以達到全面平坦的效果。平 坦化的方法較佳爲使用化學機械硏磨法(Chemical-Mechanical Polishing) 〇 之後,在蓋氧化層108上形成一層第一氮化物層110。 第一氮化物層110的厚度較佳約500至1500埃,且較佳爲 以電漿加強化學氣相沉積法彤成。再者,此第一氮化物層 基本上由氮化砂(Si3N4)形成。 接著,塗佈一層第一光阻層112於第一氮化物層110 上,並進行顯影,以形成接觸窗開口 Γΐ4。此光阻層112 具有的圖案與欲形成接觸窗114的位置一致。 請參照第2圖,在第一氮化物層110中形成一接觸窗 8 <讀先閱讀背面之注意事巧再填寫本頁} -裝_ ,π 系紙张尺度ϋ 中囡 ϋϋ { C'NS ) ( 210X 297^1 ~ 410425 4|49lwf.doc/006 A7 B7 五、發明説明(夂) 開口 116。接觸窗開口 116雖然可爲任意形狀,但是以圓 柱形爲較佳。光阻層112在蝕刻第一氮化物層11〇時作爲 罩幕。! 請參照第3圖,移除第一光阻層112。利用習知的技 術,比如爲旋塗式玻璃塗佈法,沉積一層第二低介電常數 介電層118至接觸窗開口 116及在第一氮化物層110上。 第二低介電常數介電層118的厚度以2000埃至8000埃爲 較佳。之後,對第二低介電常數介電層118進行固化(Curing) 步驟,以減少在後續步驟中移除在蝕刻氧化層時作爲罩幕 的光阻層時,第二低介電常數介電層118之水氣吸收,並 去除旋塗式玻璃薄膜中的溶劑。 接著,在第二低介電常數介電層118上形成一層第二 氮化物層120。形成此第二氮化物層120的較佳約爲500 埃至1500埃,且較佳爲以電漿加強化學氣相沉積法所沉 積的氮化矽。 接著,在第二低電常數介電層120上塗佈一層第二光 阻層122。將此第二光阻層122進行圖案化以及顯影的步 驟+,以使溝渠開口 124暴露出來。 請參照第4圖,蝕刻襯氧化層104、第一低介電常數 介電層106、蓋氧化層108、第二低介電常數介電層118以 及第二氮化物層120,以形成一個雙重鑲嵌開口 126。其 中,第二氮化砂層118與第二氮化物層120是以第二光阻 層m爲罩幕,並以第一氮化物層no爲蝕刻終止層進行 蝕刻。而蝕刻第一低介電常數介電層106、襯氧化層104 9 屮固拽家摞肀{ (、NS ) Λ4規淋(210X297公釐) I I I I 裝 I 1^1 I J* I 線 ,乂 · ,°J (¾先閱讀背面之注意事填寫本頁) 410425 4 I 49twf.doc/006 A7 B7 —M- ' ~~ ^ ~ -— 五、發明説明(6 ) 以及蓋氧化層108的步驟則是以第一氮化物層110爲罩 幕,旅以導電結構102作爲蝕刻終止層進行。 請|參照第5圖,移除第二光阻層122。以化學氣相沉 積(CVD)法,沉積一層氧化層128至雙重鑲嵌開口 126中 並覆蓋於第二氮化物層120上。其中,CVD氧化層128的 形成以高密度氧電漿化學氣相沉積法(HDP CVD)爲較佳。 此CVD氧化層128厚度則以介於大約300埃至1000埃之 間爲較佳。 請參照第6圖,蝕刻CVD氧化層128如以反應性離子 蝕刻法,以在沿著雙重鑲嵌開口 126的側壁形成氧化物間 隙壁128a。間隙壁128a防止第一低介電常數介電層1〇6 與第二低介電常數介電層118的出氣(Outgassing)現象。 如此就完成了雙重鑲嵌開口。之後,沉積一層導電層 以形成金屬內連線結構,這個步驟爲習知的方法,因此不 再贅述。 雖然本發明已以一較佳實施例說明如上,可瞭解任何 在不脫離本發明之精神和範圍內可作各種之更動與潤飾。 (对先閱讀背面之注意事填寫本頁} 裝· 線 本纸张尺度珀A屮B3 K家標彳{ (、NS > Λ4規格(210X 297公釐)
Claims (1)
- £). 410425 4 l 49twf.doc/006 AS B8 C8 D8 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 1. 一種在基底上製造雙重鑲嵌金屬內連線以及接觸窗 開口結構的方法,其步驟包括: 形成一第一氧化層於該基底上; 形成一第一氮化物層於該第一氧化層上; 圖案化並触刻該第一氮化物層以形成一接觸窗開口; 形成一第二氧化層於該接觸窗開口及該第一氮化物層 上; 形成一光阻層於該第二氧化層上; 圖案化並顯影該光阻層以暴露出與該接觸窗開口具有 不同尺寸之一溝渠開口; 以該光阻層爲罩幕,蝕刻該第二氧化層,並且以該第 一氮化物層爲罩幕,鈾刻該第一氧化層,以形成一雙重鑲 嵌開口; 移除該光阻層; 形成一氧化物間隙壁於該雙重鑲嵌開口中:以及 沉積一導電層於該雙重鑲嵌開口中。 2. 如申請專利範圍第1項之方法,其中,該形成氧化 物間隙壁的步驟包括: 沉積一第三氧化層於該雙重鑲嵌開口中;以及 回蝕刻該第三氧化層。 3. 如申請專利範圍第1項之方法,其中更包括形成一 第二氮化物層介於該第二氧化層以及該光阻層之間的步 驟。 4. 如申請專利範圍第3項之方法,其中該第一氮化物 請 先 閱 意 I t 裝 訂. 線 本紙張尺度適用中國國家標準(CNS ) A4规格(210 X 297公釐) 經濟部中央標準局員Η消費合作社印製 410426 A8 4 I 49twf.doc/006 B8 C8 D8 六、申請專利範圍 層與該第二氮化物層是由氮化矽所形成。 5. 如申請專利範圍第1項之方法,其中該第一氧化層 包括由一襯氧化層、一低介電常數介電層以及一蓋氧化層 所組成。 6. —種在一基底上形成雙重鑲嵌結構的方法,包括下 列步驟: 形成一襯氧化層於該基底上; 形成一第一低介電常數介電層於該襯氧化層上: 形成一蓋氧化層於該第一低介電常數介電層上: 形成一第一氮化物層於該蓋氧化層上; 圖案化並蝕刻該第一氮化物層以形成一接觸窗開口; 形成一第二低介電常數介電層至該接觸窗開口及覆蓋 於該第一氮化物層; 形成一光阻層於該第二低介電常數介電層上; 圖案化並顯影該光阻層以暴露出與該接觸窗開口具有 不同尺寸之一溝渠開口; 以該光阻層爲罩幕,蝕刻該第二低介電常數介電層, 並且以該第一氮化物層爲罩幕,蝕刻該蓋氧化層,該第一 低介電常數介電層以及該襯氧化層,以形成一雙重鑲嵌開 □; 移除該光阻層; 形成一氧化物間隙壁於該雙重鑲嵌開口中;以及 沉積一導電層於該雙重鑲嵌開口中。 7. 如申請專利範圍第6項之方法,其中該方法更包括 {請先閱讀背面之注意事填寫本頁) P .裝. 訂 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 4 I 49twf'.d〇c/006 410425 A8 B8 CS D8 六、申請專利範圍 一固化該第一以及該第二低介電常數介電層之步驟。 8. 如申請專利範圍第6項之方法,其中該方法更包括 形成一第二氮化物層於該第二低介電常數介電層以及該光 阻層之間的步驟。 9. 如申請專利範圍第8項之方法,其中該第一以及該 第二氮化物層係由氮化矽所彤成。 10. 如申請專利範圍第6項之方法,其中該蓋氧化層是 由二氧化矽所形成。 11. 如申請專利範圍第6.項之方法,其中該氧化物間隙 壁是以一高密度電漿化學氣相沉積法所形成的二氧化矽。 |~I JJi--'@1 裝—I (請先閱讀背面之注意事項再填寫本頁) 訂------線 經濟部中央橾隼局員工消費合作社印製 本紙浪尺度適用中國國家揉準(CNS ) A4规格(210X297公釐)
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US09/170,859 US5916823A (en) | 1998-10-13 | 1998-10-13 | Method for making dual damascene contact |
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TW410425B true TW410425B (en) | 2000-11-01 |
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TW087121149A TW410425B (en) | 1998-10-13 | 1998-12-18 | Method for forming dual damascene contacts |
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US5916823A (en) | 1999-06-29 |
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