CN1093688C - 介层窗的制造方法 - Google Patents

介层窗的制造方法 Download PDF

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CN1093688C
CN1093688C CN98115219A CN98115219A CN1093688C CN 1093688 C CN1093688 C CN 1093688C CN 98115219 A CN98115219 A CN 98115219A CN 98115219 A CN98115219 A CN 98115219A CN 1093688 C CN1093688 C CN 1093688C
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barrier layer
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metal
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罗吉进
杜友伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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Abstract

一种介层窗的制造方法，利用阻挡层做为介层窗的蚀刻掩模，进行介层窗的蚀刻步骤之前，利用等离子氧将光致抗蚀剂剥除，做为内金属介电层的SOG材料，不会暴露在等离子氧的环境中，因此可以有效避免介层窗污染。此外所选用的阻挡层并非高介电常数材料，完成介层窗的蚀刻后，不须将做为蚀刻掩模用的阻挡层剥除，因此可以简化制造工艺，并降低成本。

Description

介层窗的制造方法
本发明涉及一种介层窗的制造方法，特别是涉及一种不易污染介层窗的制造方法。
在超大型集成电路(VLSI)的制造工艺中，可以在1～2平方公分面积的硅表面上配置数量多达数十万的晶体管。并且，为了增加集成电路的集成度，须提高连接各个晶体管或是其他元件的金属线的密度。因此，以往单一金属层的设计，已无法完成整个集成电路的连线工作，两层以上的金属层设计逐渐成为许多集成电路所必需采用的方式。因此在金属层之间须以内金属介电层(Inter-metal Dielectric)加以隔离，以避免元件之间产生非预期性的导通，并在内金属介电层中形成介层窗(Via)，接着覆盖导电材料以形成导线，在半导体工业上称之为插塞(Plug)，用来连接上下两层金属层。
然而多重金属层的制作需要非常平坦的介电层，而旋涂式玻璃(Spin-On-Glass-SOG)制造工艺是一种常用的平坦化技术，此外SOG的沟填能力(Gap Fill)也非常好。
图1A至图1B为现有介层窗的制造流程剖视图.
请参照图1A，首先提供一半导体基底10，并在其上形成一已限定的金属层12，金属层12以下的MOS元件未示出。金属层12的限定比如以传统的微影蚀刻制程进行，并同时形成开口13，接着在整个半导体基底10表面形成一层与金属层12共形的衬氧化层15。之后，例如使用涂布法(Coating)形成一层SOG层16填入开口13并覆盖衬氧化层15。
其后在SOG层16上形成一层覆顶氧化层(Cap Oxide Layer)18，其形成方法是等离子增强化学气相沉积(PECVD)法，当沉积覆顶氧化层18后，须经平坦化工艺，比如化学机械研磨(CMP)法，以提供全面性平坦的覆顶氧化层18。
当进行完平坦化制程后，在覆顶氧化层18上形成一层光致抗蚀剂层20，此光致抗蚀剂层20已限定出开口14，此开口14用来后续形成介层窗。
接着请参照图1B，利用完成限定的光致抗蚀剂层20当掩模(Mask)，依序蚀刻覆顶氧化层18、SOG层16和衬氧化层15，并以金属层12为蚀刻终止层(Etching Stop Layer)，使形成覆顶氧化层18a、SOG层16a和衬氧化层15a，以及介层窗24。
之后须将光致抗蚀剂层20去除，但现有技术利用等离子氧(OxygenP1asma)进行蚀刻(Ashing)，用以移除光致抗蚀剂的过程中，SOG的有机官能基(Organic Functional Group)部分会被氧化(Oxidize)，所发生的反应如下：
    (未平衡)Si-R代表SOG的结构，R代表SOG的有机官能基，因此CO2的散逸会使SOG层16a变得具有多孔性(Porous)，且会造成SOG层16a体积的缩减，另外，反应产生的水气也会容易滞留于SOG层16a中。因而在后续金属化工艺(Metallization Process)中，SOG层16a所吸收水气会被释放，导致介层窗污染(Poisoned Via)，使得金属的沉积不易进行，会造成非预期的断路。
为了改善介层窗污染的情形，现有改善介层窗污染的方法有Furusawa等人在“Extended Abstracts of the 1996 International Conference on SolidState Devices and Materials”pp.145-147中发表的“Reliability of Low-Parasitic-Capacitance Multievel Interconnection Using Surface-Densified Low-ε Organic Spin-on Glass”，提出在低压下利用氧反应离子蚀刻(Oxygen-Reactive-Ion-Etching)，在介层窗所暴露出SOG的表面形成一薄且致密的保护层。
1997年Kwon等人在“Planar 97”pp.1-5中发表的“Prevention of O2Plasma Damage on Siloxane SOG by Applying E-beam Curing”，提出利用电子束固化(E-beam Curing)，来降低等离子氧对介层窗的污染。1994年Wang等人于“VMIC”pp.101-107中发表的“A Study of Plasma Treatments onSiloxane SOG”，提出利用等离子氩(Ar)来强化(Strengthen)SOG薄膜。这些改善的方法是降低等离子氧对介层窗污染的影响，但仅能减轻介层窗的污染。
本发明的第一个目的在于提供一种介层窗的制造方法，以避免介层窗污染及其衍生的问题。
本发明的另一目的在于提供一种介层窗的制造方法，以简化制造工艺，并降低成本。
本发明还提供一种介层窗的制造方法，该方法包括下列步骤：形成一金属层覆盖一半导体基底；对该金属层构图以形成一第一开口；形成一旋涂式玻璃层填入该第一开口；形成一介电层覆盖该旋涂式玻璃层；形成一阻挡层覆盖该介电层；形成已构图的一光致抗蚀剂覆盖该阻挡层；利用该光致抗蚀剂对该阻挡层构图；剥除该光致抗蚀剂层；以该阻挡层为掩模，继续对该介电层和该旋涂式玻璃层构图，直至暴露出该金属层并形成一介层窗。
本发明方法的优点在于，其可以避免介层窗的污染，简化制造工艺，并降低成本。
以下结合附图，描述本发明的实施例，其中：
图1A至图1B为现有介层窗的制造流程剖视图；
图2A至图2C为本发明实施例介层窗的制造流程剖视图。
图2A至图2C为根据本发明一优选实施例介层窗制造流程的剖视图。
首先请参照图2A，其先提供一半导体基底100，并在其上形成一已限定的金属层102，金属层102以下的MOS元件未绘示出。金属层102的限定比如以传统的微影蚀刻工艺进行，并同时形成开口105。金属层102的材料比如是铝铜(AlCu)。此外，金属层102的上方还包括形成一薄层抗反射涂布(Anti-reflection Coating-ARC)层101，其材料比如是氮化钛(TiN)。
其后在整个半导体基底100结构的表面形成一层衬氧化(Liner Oxide)层104，其适合的材料是氧化硅，厚度约为500～1500埃，优选的形成方法是等离子增强化学气相沉积法。衬氧化层104直接覆盖于金属层102和抗反射涂布层101的表面，其目的是为了提供高品质的附着性(Adhesion)及绝缘性。
接着在衬氧化层104上方利用现有方法涂布一层SOG层106，其优选的厚度约为4,000～8,000埃。之后在SOG层106上形成一层覆顶氧化层108，优选的材料是氧化硅，优选的形成方法是等离子增强化学气相沉积法。当沉积完覆顶氧化层108后，须经平坦化工艺，优选的平坦化方法是化学机械研磨法，以提供全面性平坦的覆顶氧化层108，经平坦化工艺后的覆顶氧化层108的优选厚度约为2,000～6,000埃。覆顶氧化层108的目的是为了提供好的附着性并确保后续沉积的金属层与金属层102之间的绝缘性。
当进行完平坦化工艺后，在覆顶氧化层108上形成一层阻挡层(BarrierLayer)110，优选的材料是氮化钛或钛，优选的厚度是300～1,500埃，其形成方法可以是化学气相沉积法或是物理气相沉积法。阻挡层110是在后续介层窗的蚀刻制程中做为蚀刻掩模。接着于阻挡层110上形成一光致抗蚀剂层112，此光致抗蚀剂层112已限定出开口103，此开口103用来形成后续的介层窗。
接着请参照图2B，利用完成限定的光致抗蚀剂层112当掩模，继续限定阻挡层110，使阻挡层110形成阻挡层110a，其方法比如是各向异性反应离子蚀刻(Anisotropic Reactive Ion Etching)工艺，并以覆顶氧化层108为蚀刻终止层。当完成阻挡层110a蚀刻后，接着利用等离子氧将光致抗蚀剂112剥除。由于此时尚未进行覆顶氧化层108、SOG层106和衬氧化层104的蚀刻，所以SOG层106未暴露在等离子氧的环境下，因此可以避免SOG层106与氧反应，可以有效避免现有技术中介层窗的污染。
接着请参照图2C，利用阻挡层110a当蚀刻掩模，进行蚀刻覆顶氧化层108、SOG层106和衬氧化层104，形成覆顶氧化层108a、SOG层106a和衬氧化层104a，其方法比如是各向异性反应离子蚀刻法，并以抗反射涂布层101为蚀刻终止层，于是形成如图2C中的介层窗114，介层窗114是用作后续的导电插塞。在某些特定的蚀刻条件下，金属层102上的抗反射涂布层101也会被去除，此时金属层102便会直接暴露在介层窗114中。
最后，继续现有技术形成导电插塞的制程。而做为蚀刻掩模用的阻挡层110埃可以不用剥除，因此可以简化制程，并节省成本。接着比如先于整个半导体基底100结构表面再形成一层薄薄的氮化钛，之后填入导电材料比如钨金属于介层窗114中，最后利用化学机械研磨法使介层窗114处形成金属插塞。
本发明的特点如下所述：
(1)本发明提供一种介层窗的制造方法，利用阻挡层做为蚀刻掩模，并在进行介层窗的蚀刻工艺前，利用等离子氧将光致抗蚀剂剥除，以避免SOG暴露于等离子氧的环境中，可以避免介层窗污染及其衍生的问题。
(2)本发明于利用阻挡层做为蚀刻掩模完成蚀刻制程后，因所选用阻挡层为金属材料，不须将阻挡层剥除，因此可以简化制程，并降低成本。
以上结合实施例对本发明加以描述，但其是非限定性的，不脱离本发明精神和范围，本领域技术人员可作各种更动与润饰，而本发明的保护范围由后附的权利要求书限定。

Claims (10)

1、一种介层窗的制造方法，其特征在于，所述方法包括下列步骤：
形成一金属层覆盖一半导体基底；
对所述金属层构图以形成一第一开口；
形成一旋涂式玻璃层填入所述第一开口；
形成一介电层覆盖所述旋涂式玻璃层；
形成一阻挡层覆盖所述介电层；
形成已构图的一光致抗蚀剂覆盖所述阻挡层；
利用所述光致抗蚀剂对所述阻挡层构图；
剥除所述光致抗蚀剂层；
以所述阻挡层为掩模，继续对所述介电层和所述旋涂式玻璃层构图，直至暴露出所述金属层并形成一介层窗。
2、如权利要求1所述介层窗的制造方法，其特征在于，形成一旋涂式玻璃层填入所述第一开口之前，还形成一衬垫氧化层覆盖所述金属层和所述半导体基底。
3、如权利要求1所述介层窗的制造方法，其特征在于，所述介电层的材料包括氧化物。
4、如权利要求3所述介层窗的制造方法，其特征在于，形成所述介电层覆盖所述旋涂式玻璃层的方法包括利用等离子增强化学气相沉积法。
5、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层为非高介电常数材料。
6、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层为金属材料。
7、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层为非高介电常数的金属材料。
8、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层的材料包括钛金属。
9、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层的材料包括氮化钛。
10、如权利要求1所述介层窗的制造方法，其特征在于，所述阻挡层的厚度约为300～1500埃。
CN98115219A 1998-03-12 1998-06-24 介层窗的制造方法 Expired - Lifetime CN1093688C (zh)

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US09/041,864 US5932487A (en) 1998-03-12 1998-03-12 Method for forming a planar intermetal dielectric layer
US041864 1998-03-12

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US5932487A (en) 1999-08-03

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