CN1226999A - 具有一种贵金属层的半导体装置及其制造方法 - Google Patents
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- 229910052763 palladium Inorganic materials 0.000 claims description 3
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Abstract
本发明是关于一种半导体装置,在这种装置中一个氮化硅层(4)被用作为在一个贵金属层,特别是铂层(6)和一个衬底之间的粘接介质。此时氮化硅层(4)本身可以作为衬底。依照本发明的方法其显著特征在于,为了提高贵金属层(6)在氮化硅层(4)上的粘接能力在氮化硅层(4)与阳极(5)之间被加上一个约为250V的衬底偏压。
Description
本发明涉及按照权利要求1前序部分的具有一种贵金属层，特别是铂系金属(Platinmetall)的一种半导体装置，以及制造一种这样的半导体装置的方法。
铂层被广泛地用作为电极并且也被用作为半导体装置的导电电路。在近一段时间里也被用于电容器，其电介质是铁电的或者具有100或大于100的一个高介电常数。
但是目前也表明，铂在一层二氧化硅作为衬底上的粘接能力是有问题的。同样情况也出现在和二氧化硅具有相同特性的其他衬底上。
试验表明，通过选择一种特殊的二氧化硅是不可能改善粘接能力的。不论是用热的二氧化硅还是用TEOS二氧化硅(TEOS=Tetraethy-lorthosilikat四乙基硅酸盐)：一个薄的铂层在两种二氧化硅品种上都是粘不好的。
现在为了克服这些困难，到目前为止为了薄的铂层使用专用的粘接剂。例如常用的有，在一种二氧化硅衬底和一个薄的铂层之间加上钛、二氧化钛、氧化铝或铬的一层膜作为粘接剂。由于它在薄的铂层和氧化硅衬底之间的可靠的粘接能力而不得不被使用的一种这样的附加粘接剂层，当然意味着至今毫无疑问地被忍受的一笔花费。
和一般趋势相反，即对薄的铂层使用粘接剂层，发明人考虑，如何不需要一种粘接剂层的很多花费就有可能提高在一个薄的铂层和一种衬底之间的粘接能力。
本发明的任务在于给出一种半导体装置及其制作方法，在本任务中用简单的方法可以改善在一种薄的贵金属层，特别是铂系金属和一种衬底之间的粘结能力。
按照本发明此任务是通过其特征为权利要求1的一种半导体装置以及通过其特征为权利要求3的一种方法解决的。
在发明中氮化硅被用作为在一种贵金属层，特别是铂系金属和一种衬底之间的粘接剂。这里衬底可以由氮化硅本身构成。也就是说，氮化硅在这里作为衬底并且同时也是它自己的粘接剂。Ru、Os、Ir、Pd或Pt可以被作为铂系金属使用。本发明也可以普遍地应用于贵金属，例如金、银及其有关合金。
在依照本发明的方法中在氮化硅衬底作为阴极和一个在一定距离内放置的阴极之间当例如铂溅射时被加上一个100至1000V，常用的是250V的衬底偏压。一个在这种条件下产生的薄的铂层显示了在其下为氮化硅衬底上具有一种特别优异的粘接能力，即使在氮化硅与铂层之间没有任何粘接介质。由于节省了一个粘接介质层制作一个半导体装置，例如制作一个DRAM或一个FeRAM(铁电RAM)的工序就可以变得非常简单。此外使用氮化硅衬底的优越性在于，如众所周知近几十年来在半导体技术中已经引入了氮化硅，因而关于它的制造、处理和特性有了很多经验。
如果在铂层上再附加一层电介质，则铂层与一个下面为氮化硅衬底的粘接能力即使在高温过程为700℃至800℃时也是足够的。用另外一种说法，一个在偏压作用下涂在一个氮化硅衬底上的铂层本身可以被用于具有一种铁电介质的或者一种具有高介电常数电介质的电容器，即使如果这种电容器必须考虑在高温下制造时。例如(Ba,Sr)TiO2或SrBi2Ta2O9或SrBi2(Ta,Nb)2O9或绝缘橡胶或铁电层在这里可以被用作为电介质。
当铂层溅射时，例如在5分钟之内在压力为0.66Pa(5mTorr)的氩气氛中使用一个300W的高频功率。此时衬底偏压为250V。这样在一个层厚约为550nm的氮化硅衬底上可以产生一个层厚约为40nm的能很好粘接的铂层。
下面借助附图详细地叙述本发明。如：
附图．1用来实施本发明方法的一个反应器的简图和
附图．2在一个DRAM以及FeRAM内一个电容器的结构图。
在一个反应器1内在一个作为底板的阴极2上面根据设备型式有一个或几个硅片3，在它的顶面上有氮化硅层4。在阴极的对面安置了一个作为溅射靶的阳极5，当在阳极5和阴极2之间被加上一个偏压时，从这里一种贵金属，例如铂Pt被溅射出来。也可以用一个环8代替阴极5被用来加电压。
氮化硅涂层4可以用等离子CVD(CVD化学气相沉积)制成并且其层厚约为550nm。
在反应器1内通过溅射在氮化硅层4上被涂上一层铂6。此时溅射是在高频功率300W压力约为0,66Pa(5mTorr)的氩气氛中进行的。在5分钟时间内铂层的层厚达到约40nm。这些数值仅仅是一些例子并且随着设备不同而改变。
现在重要的是，在阴极2和阳极5之间加上100V和1000V之间的，最好是250V的一个电压。试验表明，这样产生的铂层6毫无问题地能够通过一种粘带试验，在粘带试验时例如将一个粘带膜粘在涂层6上然后在高速运动情况下被撕下。铂层6可以多次地抵抗住一种这样的撕断粘带试验。
如果在铂层上再涂上一层例如(Ba,Sr)TiO3或SrBi2Ta2O9，或SrBi2(Ta,Nb)2O9或一个绝缘橡胶或铁电层的电介质，那么下面的铂层6在氮化硅层4上的粘接能力在高温500°和800℃之间并且特别是在700℃和800℃之间可以得到进一步的改善。按照本发明的方法也特别适用于制造电容器，其电介质为铁电体或者具有50至100或更高的一个高介电常数。一个这样的电介质7在附图上是用虚线表示的。
这里需要说明的是，附图只是简单地表示了每个涂层3、4、6和7。实际上这些涂层的结构可以是用不同的方法构成的。而且电介质7也不是在反应器1中涂上的。
本发明使采用简单的方法制造铂层成为可能，这种铂层以其与下层的氮化硅层的高粘接能力而著称。可以使用一种铂系金属，例如Ru、Os、Rh、Ir或Pd代替铂。但是也可以使用普通的贵金属。
附图．2表示了在一个DRAM以及FeRAM中的一个电容器。电容器9有一个表层铂层10，一个例如(Ba,Sr)TiO3(BST)或SrBi2Ta2O9(SBT)的电介质11和一个下层铂层12。可以用SrBi2(Ta,Nb)2O9或者一种绝缘橡胶或铁电层代替BST或SBT。下层铂层12位于氮化硅13之上并且在这个例子中是用反应器1涂上的。因此铂层12能很好地粘接在氮化硅层13上。氮化硅层13位于一个具有一个半导体结构15的硅衬底14上并且包括位和字导线16。
Claims (6)
1．用于制造一个半导体装置的方法，该装置具有一个衬底(3)和一个由贵金属，特别是铂系金属构成的层(6)，在衬底与贵金属层之间是一个氮化硅层或者衬底本身是由氮化硅层构成的，当层(6)是由贵金属，特别是由铂系金属通过溅射构成时，其特征为，当溅射时在作为阴极(2)的衬底和在一定距离上安置的阳极(5)之间被加上一个由100V至1000V的衬底偏压。
2．依照权利要求1的方法，其特征为，被加上的衬底偏压约为250V。
3．依照权利要求1或2的方法，其特征为，当溅射时在压力为0.5至1.0Pa的氩气氛中作用一个约为300W的高频功率。
4．依照权利要求1至3之一的方法，其特征为，在贵金属层(6)上涂上一层电介质(7)。
5．依照权利要求4的方法，其特征为，(Ba,Sr)TiO3、SrBi2Ta2O9或SrBi2(Ta,Nb)2O9或绝缘橡胶或铁电层被用作为电介质(7)。
6．依照权利要求1至5之一的方法，其特征为，Ru、Os、Rh、Ir、Pd或Pt被用作为铂系金属。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19640240.9 | 1996-09-30 | ||
| DE19640240A DE19640240A1 (de) | 1996-09-30 | 1996-09-30 | Halbleiteranordnung mit einer Schicht aus einem Edelmetall und Verfahren zum Herstellen derselben |
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| CN1226999A true CN1226999A (zh) | 1999-08-25 |
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| CN97196961A Pending CN1226999A (zh) | 1996-09-30 | 1997-09-11 | 具有一种贵金属层的半导体装置及其制造方法 |
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| EP (1) | EP0931334A1 (zh) |
| JP (1) | JP2001501374A (zh) |
| KR (1) | KR20000029581A (zh) |
| CN (1) | CN1226999A (zh) |
| DE (1) | DE19640240A1 (zh) |
| TW (1) | TW398027B (zh) |
| WO (1) | WO1998014991A1 (zh) |
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| EP0986095A3 (de) | 1998-09-08 | 2005-08-17 | Infineon Technologies AG | Schichtanordnung mit einer Materialschicht und einer im Bereich der Korngrenzen der Materialschicht angeordneten Diffusionsbarrierenschicht, und Verfahren zur Herstellung derselben |
| DE19845033A1 (de) * | 1998-09-30 | 2000-04-20 | Siemens Ag | Halbleiterbauelement |
| JP4539844B2 (ja) * | 2004-04-15 | 2010-09-08 | セイコーエプソン株式会社 | 誘電体キャパシタおよびその製造方法ならびに半導体装置 |
| DE102009019524B4 (de) * | 2009-04-30 | 2023-07-06 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterkörper mit einem reflektierenden Schichtsystem |
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| US4129848A (en) * | 1975-09-03 | 1978-12-12 | Raytheon Company | Platinum film resistor device |
| US4507851A (en) * | 1982-04-30 | 1985-04-02 | Texas Instruments Incorporated | Process for forming an electrical interconnection system on a semiconductor |
| US4756810A (en) * | 1986-12-04 | 1988-07-12 | Machine Technology, Inc. | Deposition and planarizing methods and apparatus |
| NL9000602A (nl) * | 1990-03-16 | 1991-10-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met geheugenelementen vormende condensatoren met een ferroelectrisch dielectricum. |
| JP3131982B2 (ja) * | 1990-08-21 | 2001-02-05 | セイコーエプソン株式会社 | 半導体装置、半導体メモリ及び半導体装置の製造方法 |
| JP3407409B2 (ja) * | 1994-07-27 | 2003-05-19 | 富士通株式会社 | 高誘電率薄膜の製造方法 |
| US5573979A (en) * | 1995-02-13 | 1996-11-12 | Texas Instruments Incorporated | Sloped storage node for a 3-D dram cell structure |
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-
1997
- 1997-09-11 WO PCT/DE1997/002036 patent/WO1998014991A1/de not_active Application Discontinuation
- 1997-09-11 KR KR1019997000642A patent/KR20000029581A/ko not_active Application Discontinuation
- 1997-09-11 JP JP10516110A patent/JP2001501374A/ja active Pending
- 1997-09-11 EP EP97943753A patent/EP0931334A1/de not_active Ceased
- 1997-09-11 TW TW086113182A patent/TW398027B/zh not_active IP Right Cessation
- 1997-09-11 CN CN97196961A patent/CN1226999A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO1998014991A1 (de) | 1998-04-09 |
| EP0931334A1 (de) | 1999-07-28 |
| JP2001501374A (ja) | 2001-01-30 |
| KR20000029581A (ko) | 2000-05-25 |
| TW398027B (en) | 2000-07-11 |
| DE19640240A1 (de) | 1998-04-02 |
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