CN1193814A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1193814A CN1193814A CN98100729A CN98100729A CN1193814A CN 1193814 A CN1193814 A CN 1193814A CN 98100729 A CN98100729 A CN 98100729A CN 98100729 A CN98100729 A CN 98100729A CN 1193814 A CN1193814 A CN 1193814A
- Authority
- CN
- China
- Prior art keywords
- wiring layer
- contact hole
- semiconductor substrate
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (13)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP060752/97 | 1997-03-14 | ||
JP060752/1997 | 1997-03-14 | ||
JP09060752A JP3120750B2 (ja) | 1997-03-14 | 1997-03-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1193814A true CN1193814A (zh) | 1998-09-23 |
CN1100348C CN1100348C (zh) | 2003-01-29 |
Family
ID=13151327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN98100729A Expired - Fee Related CN1100348C (zh) | 1997-03-14 | 1998-03-12 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6258708B1 (zh) |
JP (1) | JP3120750B2 (zh) |
KR (1) | KR100265271B1 (zh) |
CN (1) | CN1100348C (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10239843B4 (de) * | 2002-08-29 | 2008-12-18 | Promos Technologies, Inc. | Verfahren zur Ausbildung eines Kontaktes |
JP4786126B2 (ja) * | 2003-06-04 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5108941A (en) * | 1986-12-05 | 1992-04-28 | Texas Instrument Incorporated | Method of making metal-to-polysilicon capacitor |
US4753709A (en) * | 1987-02-05 | 1988-06-28 | Texas Instuments Incorporated | Method for etching contact vias in a semiconductor device |
DE69031543T2 (de) * | 1989-02-17 | 1998-04-09 | Matsushita Electronics Corp | Verfahren zum Herstellen einer Halbleitervorrichtung |
US5010039A (en) * | 1989-05-15 | 1991-04-23 | Ku San Mei | Method of forming contacts to a semiconductor device |
JPH03147364A (ja) | 1989-11-01 | 1991-06-24 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
JPH04179269A (ja) | 1990-11-14 | 1992-06-25 | Nec Corp | 半導体記憶装置 |
KR950009741B1 (ko) * | 1991-10-10 | 1995-08-26 | 금성일렉트론주식회사 | 반도체 메모리 셀의 제조방법 및 그 구조 |
JPH06140396A (ja) * | 1992-10-23 | 1994-05-20 | Yamaha Corp | 半導体装置とその製法 |
JPH06163535A (ja) | 1992-11-26 | 1994-06-10 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JPH07115130A (ja) * | 1993-10-14 | 1995-05-02 | Toshiba Corp | 半導体装置の製造方法 |
JPH07142597A (ja) * | 1993-11-12 | 1995-06-02 | Mitsubishi Electric Corp | 半導体記憶装置およびその製造方法 |
JP3022744B2 (ja) * | 1995-02-21 | 2000-03-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH08316430A (ja) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | 半導体メモリとその製造方法、スタックドキャパシタ |
US5943598A (en) * | 1995-10-19 | 1999-08-24 | Stmicroelectronics, Inc. | Integrated circuit with planarized dielectric layer between successive polysilicon layers |
US5563088A (en) * | 1996-02-02 | 1996-10-08 | Vanguard International Semiconductor Corporation | Method for fabricating a stacked capacitor in a DRAM cell |
US5792703A (en) * | 1996-03-20 | 1998-08-11 | International Business Machines Corporation | Self-aligned contact wiring process for SI devices |
GB2322733A (en) * | 1997-02-27 | 1998-09-02 | Nec Corp | Polysilicon electrodes for DRAM cells |
-
1997
- 1997-03-14 JP JP09060752A patent/JP3120750B2/ja not_active Expired - Fee Related
-
1998
- 1998-03-12 CN CN98100729A patent/CN1100348C/zh not_active Expired - Fee Related
- 1998-03-13 KR KR1019980008594A patent/KR100265271B1/ko not_active IP Right Cessation
- 1998-03-16 US US09/039,768 patent/US6258708B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100265271B1 (ko) | 2000-09-15 |
JP3120750B2 (ja) | 2000-12-25 |
US6258708B1 (en) | 2001-07-10 |
JPH10256396A (ja) | 1998-09-25 |
CN1100348C (zh) | 2003-01-29 |
KR19980080254A (ko) | 1998-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5466971A (en) | Semiconductor device having a multilayer interconnection layer | |
US4676866A (en) | Process to increase tin thickness | |
US4746219A (en) | Local interconnect | |
US5010032A (en) | Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects | |
US6369430B1 (en) | Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same | |
US4657628A (en) | Process for patterning local interconnects | |
US6451664B1 (en) | Method of making a MIM capacitor with self-passivating plates | |
JP2006511965A (ja) | 高密度不揮発性メモリを製作するための改良された方法 | |
US6611061B2 (en) | Tantalum-aluminum-nitrogen material for semiconductor devices | |
US5285102A (en) | Method of forming a planarized insulation layer | |
KR100306202B1 (ko) | 반도체장치 및 그의 제조방법 | |
CN1230780A (zh) | 改进的多晶硅-硅化物 | |
CN1050448C (zh) | 具有高集成度布线结构的半导体器件及其制造方法 | |
US20030157788A1 (en) | Method of suppressing void formation in a metal line | |
KR0138308B1 (ko) | 층간접촉구조 및 그 방법 | |
CN1100348C (zh) | 半导体器件及其制造方法 | |
KR0161379B1 (ko) | 반도체 소자의 다층배선 및 그 제조방법 | |
US6133628A (en) | Metal layer interconnects with improved performance characteristics | |
US6011289A (en) | Metal oxide stack for flash memory application | |
KR100231669B1 (ko) | 층간 절연막에 형성된 기체절연층을 갖는 반도체장치및그제조방법 | |
CN1049765C (zh) | 在集成电路上互连的接触及其制造方法 | |
CN1155758A (zh) | 形成半导体器件金属引线的方法 | |
US20040150108A1 (en) | Low resistance barrier for a microelectronic component and method for fabricating the same | |
US20220320329A1 (en) | Semiconductor device | |
KR960004078B1 (ko) | 금속박막 적층구조를 사용한 콘택 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030425 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20030425 Address after: Kanagawa, Japan Patentee after: NEC Corp. Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
C56 | Change in the name or address of the patentee |
Owner name: RENESAS ELECTRONICS CO., LTD. Free format text: FORMER NAME: NEC CORP. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: NEC Corp. |
|
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030129 Termination date: 20140312 |