CN1230780A - 改进的多晶硅-硅化物 - Google Patents
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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Abstract
一种用于形成一动态随机存取存储器(DRAM)的方法,该DRAM包括一具有多晶硅-硅化物栅的晶体管,此方法包括:在衬底上形成一氧化物层;在氧化物层之上形成一多晶硅层;和在多晶硅层之上沉积一金属硅化物层,该金属硅化物层是用掺杂剂就地掺杂的,以减少多晶硅和金属硅化物层之间的富金属界面;和给氧化物,多晶硅和金属硅化物层构图以形成栅。
Description
本发明总体上涉及半导体制造,更具体地说,涉及具有多晶硅-硅化物(polycide)栅极的晶体管。
在器件制造中,绝缘,半导电和导电层形成于一衬底上。这些层被构图以产生图形(features)和间隔(spaces)。这些图形和间隔被构图以形成器件,诸如晶体管,电容和电阻。然后将这些器件内部连接以实现一个期望的电子功能,产生一个集成电路(IC)。
为减小表面电阻,一金属氧化物半导体(MOS)晶体管采用一多晶硅-硅化物栅。该多晶硅-硅化物栅包括在重掺杂多晶硅(poly)之上的金属硅化物,比如钨硅化物(WSix)。典型地,该多晶硅掺杂有磷(P)。该多晶硅应包括一高度掺杂浓度以降低其表面电阻。
然而,重掺杂多晶硅之上的金属硅化物存在化学配化的控制问题,表现出一富金属的界面。富金属界面是不期望的,因为它不耐受后续的热过程。结果,该界面被氧化。氧化引起表面粗糙,而且,在某些情况下会引起硅化物薄膜的脱层。传统地,富金属界面的不利影响是通过在重掺杂多晶硅和金属硅化物之间提供一本征(无掺杂)层来避免的。无掺杂多晶硅层的添加增大了栅堆积的高度,增大了栅堆积的高宽比(aspect ratio)。降低基本图形尺寸(groundrule)进一步增大高宽比,会导致工艺(生产)问题。而且,添加无掺杂多晶硅层也会增大栅电阻,它使器件性能降低。避免富金属界面的另一技术是降低多晶硅的掺杂浓度。典型地,多晶硅层磷的浓度应保持在1020原子/立方厘米以下。这一技术也会不希望地增大栅电阻。
从上面的描述中可知,希望提供一种具有减小的表面电阻的可靠的多晶硅-硅化物栅。
本发明的目的是提供可形成具有减小的厚度和较低的表面电阻的可靠的栅极导体的一种用于形成DRAM的方法、一种包括多晶硅-硅化物栅的晶体管和一种制造半导体器件的方法。
为实现上述目的,本发明一方面提供一种用于形成一动态随机存取存储器(DRAM)的方法,该DRAM包括一具有多晶硅-硅化物栅的晶体管,此方法包括以下步骤:在衬底上形成一氧化物层;在氧化物层之上形成一多晶硅层;和在多晶硅层之上沉积一金属硅化物层,该金属硅化物层是用掺杂剂就地掺杂的,以减少多晶硅和金属硅化物层之间的富金属界面;和给氧化物,多晶硅和金属硅化物层构图以形成栅。
本发明另一方面提供一种包括一多晶硅-硅化物栅的晶体管,包括:一栅极氧化物层;一多晶硅层;和一就地掺杂的金属硅化物,金属硅化物中的掺杂剂减少了多晶硅和金属硅化物层之间的富金属界面。
本发明在一方面提供一种制造半导体器件的方法,包括:在一衬底上形成一多晶硅层;和在多晶硅层上沉积一金属硅化物层,该金属硅化物层是用掺杂剂就地掺杂的,以减少多晶硅和金属硅化物层之间的富金属界面。
根据本发明,减小的厚度和较低的表面电阻是通过在一掺杂多晶硅层之上沉积一就地(insitu)掺杂金属硅化物层来实现的。金属硅化物层中的掺杂剂减少了伴随富金属界面的问题。这允许沉积一金属硅化物层,而不需要一本征罩帽多晶硅层或要求多晶硅具有一较低的掺杂浓度。
通过以下结合附图对优选实施例的详细描述,本发明的上述以及其他目的、特征和优点会更清楚。附图中:
图1示出了一说明性的DRAM单元;
图2a-c显示了本发明的用于形成一多晶硅-硅化物栅叠层的一个实施例。
本发明涉及一种可靠的多晶硅-硅化物栅,它具有减小的表面电阻。为简化本发明的讨论,在上下文中结合一个存储器集成电路(IC)来描述,然而,本发明的覆盖面是很宽的,它适用于一般的集成电路。下面提供了对一DRAM单元的描述。
参考图1,显示了一沟槽电容型DRAM单元100。这样的沟槽电容DRAM单元,例如,在Nesbit等人的“A0.6μm2 256Mb Trench DRAM CellWith Self-Aligned Buried Strap(BEST),IEDM 93-627”中描述过,在此参考它来进行描述。尽管显示了一沟槽电容DRAM单元,本发明并不局限于此。例如,也可使用一堆积电容DRAM单元。典型地,这样的单元的矩阵是通过字线和位线内部连接以形成一DRAMIC。
例如,DRAM单元100包括一沟槽电容160,它形成于一衬底101中。沟槽典型地是由多晶硅161填充的,多晶硅161重(高度)掺杂有具有一第一导电率(如n型)的掺杂剂。掺杂的多晶硅用作电容器的一个电极,被称为一“存储节点”。可选择地,一掺杂有第一导电率的掺杂剂的掩埋极板165围绕沟槽的底部。掩埋板用作电容器的另一电极。在沟槽的上部是一环状物168,以减小寄生泄漏。一节点介质163将电容的两极板隔开。一包括有第一导电率的掺杂剂的掩埋阱170提供来连接矩阵中的DRAM单元的掩埋极板。在该掩埋阱之上是一阱173,它包括有具有一第二导电率的掺杂剂,如P型。该P型阱包括的掺杂剂浓度足以形成一相反的导电率连接,以降低晶体管110的垂直泄漏。
晶体管包括一多晶硅-硅化物栅叠层112。该栅叠层,有时称之为一“栅导体”(GC),用作DRAM矩阵中的字线。由于字线被连接到电容上,它又被称作“活动字线”。如图所示,该栅叠层包括一多晶硅层120,它重度掺杂有掺杂剂。在一个实施例中,多晶硅层120重度掺杂有磷掺杂剂。也可使用硼(B)或砷(As)掺杂剂。为保持低表面电阻,多晶硅的掺杂剂浓度应足够高。在重掺杂的多晶硅120之上提供了一本征多晶硅层121和一金属硅化物层122。本征多晶硅层用作一缓冲层,以避免在硅化物和重掺杂的多晶硅层之间的富金属界面。尽管在后续的热工序中,掺杂剂从重掺杂的多晶硅层扩散到本征多晶硅,在最初的金属硅化物层的沉积期间多晶硅是本征的。在金属硅化物层之上是,例如,一用作刻蚀阻挡层的氮化物层。
与栅极相邻提供有重掺杂扩散区113和114。扩散区包括具有与多晶硅层相同并与阱173相反的导电率的掺杂剂。扩散区,例如,重掺杂有n型掺杂剂。根据电流流动的方向,扩散区113和114分别称作“漏极”或“源极”。用在这里,术语“漏极”和“源极”是可互换的。晶体管和电容间的连接是通过一扩散区125来实现的,称之为“节点扩散”。
一浅沟槽隔离(STI)180被提供来将DRAM单元从其它单元或器件中隔离开。如图所示,一字线120,形成于沟槽之上并由STI与其隔开。字线120被称作“传输字线”,因为它没有与DRAM单元电连接。这种结构被称为一折叠位线结构。其它结构,包括打开和打开折叠结构也是可用的。
一层间介质层189形成于字线之上。一导电层,代替一位线,形成于层间介质层之上。在层间介质层中提供了一位线接触开口186,以使源极113与位线190接触。
如前所述,在重掺杂多晶硅和硅化物层间使用多晶硅缓冲层增加了栅叠层的厚度。这个增加的厚度是不希望的,因为它产生了较高的高宽比图形,产生了工艺困难。
图2a-c显示了根据本发明形成一多晶硅-硅化物栅叠层的工艺。参考图2a,显示了代表一IC的一部分的衬底的横截面。这样一个IC,例如,是一存储器IC,它包括一随机存取存储器(RAM),一动态RAM(DRAM),一同步DRAM(SDRAM),一静态RAM(SRAM)和一只读存储器(ROMS)。该IC可以是一逻辑器件,如一可编程逻辑矩阵(PLA),一专用IC(ASIC),一合并DRAM逻辑IC(嵌入DRAM)或任何其它逻辑器件。
典型地,多个IC并行制造一个半导体衬底之上,如一硅片。处理之后,该片被切割成小片以便将IC分成多个独立的芯片。这些芯片接着被包装成最终产品以便使用,例如,用户产品诸如计算机系统,办公设备包括复印机,打印机,以及传真系统,峰窝电话,个人数字辅助器(PDA)和其它电子产品。
衬底201是,例如,一硅片。其它衬底如硅位于绝缘体之上(SOI),硅位于蓝宝石之上(SOS),锗,砷化镓,和Ⅲ-Ⅴ族化合物也可采用。在一个实施例中,衬底轻度掺杂有具有一第一导电率的掺杂剂。尽管所示衬底没有包括其它器件层器件图形,这里所用术语“衬底”可理解为包括一衬底,其上具有一个或更多个器件层和器件图形。在一个实施例中,衬底轻掺杂有P型掺杂剂(p-),如硼。硼的浓度约为1.5×1016原子/立方厘米。
衬底,例如,包括多个形成于其中的沟槽电容(未显示)。沟槽电容,例如,为图1中所描述的。在一个实施例中,沟槽电容用作n沟道DRAM单元的存储电容。掩埋的n阱提供来将电容的n型掩埋极板连接在一起。p阱提供来用于n沟道DRAM存取晶体管。p阱的浓度约为5×1017-8×1017cm-3。另外,n型阱提供来用于P沟道晶体管,如那些包括在支持电路中的。如有必要,其它扩散区可能提供在衬底中。
在此工序中,衬底包括一平面表面210。一牺牲氧化物层(未显示)形成于该表面之上。该牺牲氧化物层用作一屏蔽氧化物,用于注入离子以调整后续形成的晶体管的栅极域值电压(Vt)。Vt调整注入物,例如,采用传统的光刻与掩模技术以有选择地将掺杂剂注入栅极的沟道区域。这种技术包括在屏蔽氧化物层之上沉积一光致抗蚀剂层,并用一暴光源和掩模有选择地暴露它。根据所用的是正或负抗蚀剂,在有选择地暴露衬底以下区域的过程中,或是暴露或是未暴露的抗蚀剂层被移去。接着暴露区被注入离子以实现期望的Vt。
在Vt注入之后,抗蚀剂和屏蔽氧化物层被,例如,湿腐蚀移去。接着一薄氧化物层220形成于衬底表面之上。氧化物层用作栅极氧化物。在一个实施例中,栅极氧化物是通过热氧化产生的。栅极氧化物的厚度是,例如,约6-10nm。
一多晶硅层230沉积于栅氧化物之上。多晶硅层是通过,例如,化学气相沉积(CVD)来沉积的。另外,一非晶硅层可用于替代多晶硅。典型地,多晶硅层包括掺杂剂以降低它的电阻率。这样的掺杂剂,例如,包括磷(P),砷(As)或硼(B)。此多晶硅层可在它形成中或之后掺杂。在CVD工序中混合掺杂剂称为就地掺杂。
在一个实施例中,多晶硅层掺杂有P掺杂剂。多晶硅是就地掺杂。P掺杂剂的浓度约为1019-5×1021原子/立方厘米,最好约为1020-1021原子/立方厘米,更好约为5×1020。多晶硅在一CVD反应器中沉积,温度约为600-650℃,压力约为100-180乇,使用SiH4作为硅先质,PH3作为一P掺杂剂源。掺杂的多晶硅的厚度约为10-200nm,最好为40-150nm,更好为50-100nm。当然,实际厚度可随各种因素而变化。例如,对工作功能目标要求一最小厚度,这取决于设计要求。这个最小厚度,在某些情况下,可低于10nm。
参考图2b,一金属硅化物层240沉积于多晶硅层230之上。该金属硅化物包括,例如,硅化钨(WSix),硅化钼(MoSix),硅化钽(TaSix),硅化钛(TiSix),硅化钴(CoSix)或其它金属硅化物。根据一个实施例,该金属硅化物包括掺杂剂,它是p-或n-型。这种掺杂剂包括,例如P、As或B。在此例中,掺杂剂类型与用作掺杂多晶硅层230的掺杂剂相同。典型的金属硅化物层的浓度约为1019-5×1021原子/厘米3,最好为1020-1021原子/厘米3,更好为5×1020原子/厘米3。就地掺杂的金属硅化物潜在地增加了它以其非晶(不定形)态沉积的趋势。以其非晶态沉积金属硅化物增加了薄膜的晶粒尺寸,从而降低了它的电阻。
就地掺杂的金属硅化物是通过用于沉积一无掺杂金属硅化物薄膜的传统CVD技术沉积的。一掺杂剂源被包括在CVD工序中以提供沉积的膜的就地掺杂。
在一个实施例中,掺杂的金属硅化物层包括有P掺杂的WSix。WSix是就地掺杂的。P掺杂剂的浓度约为1019-5×1021原子/厘米3,最好为1020-1021原子/厘米3,更好约为5×1020原子/厘米3。沉积的金属硅化物的厚度约为50-200nm,最好约为80nm。当然,实际厚度可依据设计和参数而变化。
传统的W,Si和掺杂剂先驱物被采用来形成掺杂的WSix膜。传统的硅先驱物包括,例如,硅烷(SiH4),乙硅烷(Si2H6)或二氯甲硅烷(SiH2Cl2);W先驱物包括六氟化钨(WF6),六氯化钨(WCl6),或六羰基化钨(W[CO]6)。磷化氢(PH3或POCl4),例如,用于提供P掺杂剂源。在一个实施例中,PH3被加入到WF6和SiH4以形成掺杂有P的WSix膜。先驱物被引入一CVD反应器,如由位于Santa Clara,CA的Applied Materials制造的一Centura CVD反应器。CVD工序的典型的温度和压力分别约为450-600℃和1-5乇。最好温度约为550℃,压力约为1.5乇。
在沉积过程中向金属硅化物膜添加掺杂剂减少了富金属界面的形成。尽管用于减少富金属界面的机理并不表楚,但可以相信掺杂剂能提高金属的反应率。例如,WF6反应率被提高。由于掺杂剂是在沉积工序中加入的,在整个沉积过程(工序)中WF6反应的效率被提高。因此,W被相对均匀地分布于整个WSix膜,避免了一富金属界面。
在一重掺杂层之上一沉积-金属硅化物薄膜而没有富金属界面的能力允许在一重掺杂层上沉积金属硅化物薄膜,而不需要本征盖帽多晶硅层。这在当生产具有较低高宽比的栅叠层时极为有利,特别是基本图形尺寸(groundrule)较小时。而且,可实现较低的电阻,增大器件性能。
而且,由于使用了一掺杂的硅化物层,多晶硅层可以是无掺杂的。一无掺杂非晶硅可用来替代多晶硅。无掺杂多晶硅或非晶硅的厚度可以是,例如,约20-50nm。
在后续工序中的热暴露引起金属硅化物或多晶硅层中的掺杂剂的扩散。可选择地,进行退火以扩散各层中的掺杂剂。退火被设计来提高或优化薄膜特性。该退火,例如,是在约1000℃的温度,大气压下进行的。退火的环境包括,例如,氧(O2),氩(Ar),或氮(N2)。在多晶硅层包括的掺杂剂浓度低于硅化物层的情况下,退火增大了多晶硅层中的掺杂剂的掺杂浓度。通过提供一用作掺杂剂源的掺杂的硅化物层,多晶硅层的掺杂剂浓度可低于引起富金属界面的掺杂剂浓度。栅叠层的多晶硅层可包括一较高的掺杂剂浓度而不会增加它的厚度,以避免一富金属界面。结果,提供了一种具有低表面电阻的栅叠层。
在金属硅化物之上形成了一刻蚀阻挡层,用于后续的处理。该蚀刻阻挡层,例如,包括氮化硅。
参考图2c,栅堆积层被构图以形成栅极导体280。栅极导体的构图是使用传统的光刻和腐蚀技术实现的。这种技术包括沉积一抗蚀剂层并用暴光源和掩模有选择地暴露该抗蚀剂层。显影之后部分抗蚀剂被移去,剩下部分栅叠层未保护。栅堆叠层的未保护部分是通过,例如,一活性离子刻蚀移去。
间隔层(未显示)可被选择形成于栅极导体的侧壁。在间隔层形成之后,注入掺杂剂以形成与晶体管的栅极相邻的扩散区。间隔层限定了扩散区的层下扩散,降低了覆盖电容。
一氮化物层288被沉积于衬底的表面,用作一迁移离子阻挡层和用于形成无边界的字线接触的蚀刻停止层。一介质层290形成于器件结构之上,以提供导电层293和栅极导体之间的绝缘。介质层也用作一保护层以使器件结构与杂质,潮湿和擦伤绝缘。介质层,例如,包括掺杂磷的二氧化硅,如磷硅化物玻璃(PSG,phosphosilicate glass)或硼磷硅化物琉璃(BPSG,borophosphosilicate glass)。
接触点291形成于介质层中,在导电层和一下层导电区285间进行内部连接。导电层,例如,表示DRAM芯片的一位线。
参考各种实施例对本发明进行了特别的显示和描述,对本领域的技术人员来说可不脱离本发明范畴地对本发明进行改进和变化。因此本发明的范畴不应由以上描述确定,而应参考所附权利要求及它们的等同物范畴确定。
Claims (17)
1.一种用于形成一动态随机存取存储器(DRAM)的方法,该DRAM包括一具有多晶硅-硅化物栅的晶体管,此方法包括以下步骤:
在衬底上形成一氧化物层;
在氧化物层之上形成一多晶硅层;和
在多晶硅层之上沉积一金属硅化物层,该金属硅化物层是用掺杂剂就地掺杂的,以减少多晶硅和金属硅化物层之间的富金属界面;和
给氧化物,多晶硅和金属硅化物层构图以形成栅。
2.一种包括一多晶硅-硅化物栅的晶体管,包括:
一栅极氧化物层;
一多晶硅层;和
一就地掺杂的金属硅化物,金属硅化物中的掺杂剂减少了多晶硅和金属硅化物层之间的富金属界面。
3.一种制造半导体器件的方法,包括:
在一衬底上形成一多晶硅层;和
在多晶硅层上沉积一金属硅化物层,该金属硅化物层是用掺杂剂就地掺杂的,以减少多晶硅和金属硅化物层之间的富金属界面。
4.如权利要求3所述的方法,其中掺杂剂是从由n-型或p-型掺杂剂组成的组中选择的。
5.如权利要求4所述的方法,其中n型掺杂剂是从由砷或磷组成的组中选择的,p型掺杂剂包括硼。
6.如权利要求5所述的方法,其中多晶硅层包括掺杂剂。
7.如权利要求6所述的方法,其中,多晶硅层中的掺杂剂与金属硅化物层中的掺杂剂属于同一类型。
8.如权利要求7所述的方法,其中,金属硅化物和多晶硅层包括n型掺杂剂。
9.如权利要求8所述的方法,其中,n型掺杂剂包括磷。
10.如权利要求9所述的方法,其中金属硅化物层中的掺杂剂浓度约为1019-5×1021。
11.如权利要求10所述的方法,其中多晶硅层中的掺杂剂的浓度约为1019-5×1021。
12.如权利要求11所述的方法,其中金属硅化物是从包括钨,钼,钽,钛和钴的组中选择的。
13.如权利要求12所述的方法,其中,金属硅化物包括钨。
14.如权利要求13所述的方法,其中,金属硅化物是通过化学气相沉积法(CVD)沉积的。
15.如权利要求14所述的方法,其中,一硅先驱物,一钨先驱物和一掺杂剂先驱物被用于CVD。
16.如权利要求15所述的方法,其中,硅先驱物是从包括SiH4,Si2H6或SiH2Cl2的组中选择的,钨先驱物是从包括WF6,WCl6或W[CO]6的组中选择的,磷先驱物是从包括PH3或POCl4的组中选择的。
17.如权利要求16所述的方法,其中硅化物的沉积是在温度为450-600℃,压力约为1-5乇下进行的。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106558474A (zh) * | 2015-09-25 | 2017-04-05 | 应用材料公司 | 通过约束来进行的硅化物相控制 |
CN108701711A (zh) * | 2016-02-17 | 2018-10-23 | 通用电气公司 | 用于宽带隙半导体功率器件的原位掺杂的半导体栅电极的系统和方法 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037620A (en) * | 1998-06-08 | 2000-03-14 | International Business Machines Corporation | DRAM cell with transfer device extending along perimeter of trench storage capacitor |
US6639264B1 (en) * | 1998-12-11 | 2003-10-28 | International Business Machines Corporation | Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures |
US6614082B1 (en) * | 1999-01-29 | 2003-09-02 | Micron Technology, Inc. | Fabrication of semiconductor devices with transition metal boride films as diffusion barriers |
US6797601B2 (en) * | 1999-06-11 | 2004-09-28 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects |
US6730584B2 (en) * | 1999-06-15 | 2004-05-04 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
US6630718B1 (en) * | 1999-07-26 | 2003-10-07 | Micron Technology, Inc. | Transistor gate and local interconnect |
US6396121B1 (en) * | 2000-05-31 | 2002-05-28 | International Business Machines Corporation | Structures and methods of anti-fuse formation in SOI |
US6392922B1 (en) * | 2000-08-14 | 2002-05-21 | Micron Technology, Inc. | Passivated magneto-resistive bit structure and passivation method therefor |
KR100447031B1 (ko) * | 2001-03-23 | 2004-09-07 | 삼성전자주식회사 | 텅스텐 실리사이드막의 형성방법 |
US6607976B2 (en) | 2001-09-25 | 2003-08-19 | Applied Materials, Inc. | Copper interconnect barrier layer structure and formation method |
US6528367B1 (en) | 2001-11-30 | 2003-03-04 | Promos Technologies, Inc. | Self-aligned active array along the length direction to form un-biased buried strap formation for sub-150 NM BEST DRAM devices |
DE10217610B4 (de) * | 2002-04-19 | 2005-11-03 | Infineon Technologies Ag | Metall-Halbleiter-Kontakt, Halbleiterbauelement, integrierte Schaltungsanordnung und Verfahren |
US6783995B2 (en) * | 2002-04-30 | 2004-08-31 | Micron Technology, Inc. | Protective layers for MRAM devices |
US6670682B1 (en) * | 2002-08-29 | 2003-12-30 | Micron Technology, Inc. | Multilayered doped conductor |
US6982214B2 (en) * | 2002-10-01 | 2006-01-03 | Applied Materials, Inc. | Method of forming a controlled and uniform lightly phosphorous doped silicon film |
US20040132245A1 (en) * | 2003-01-06 | 2004-07-08 | Pi-Chun Juan | Method of fabricating a dram cell |
JP2005217176A (ja) | 2004-01-29 | 2005-08-11 | Tokyo Electron Ltd | 半導体装置および積層膜の形成方法 |
TWI278069B (en) * | 2005-08-23 | 2007-04-01 | Nanya Technology Corp | Method of fabricating a trench capacitor having increased capacitance |
US20120205727A1 (en) | 2011-02-11 | 2012-08-16 | International Business Machines Corporation | Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer |
US10971366B2 (en) * | 2018-07-06 | 2021-04-06 | Applied Materials, Inc. | Methods for silicide deposition |
KR102568706B1 (ko) | 2018-09-18 | 2023-08-21 | 어플라이드 머티어리얼스, 인코포레이티드 | 인-시튜 통합 챔버들 |
WO2020131296A1 (en) | 2018-12-21 | 2020-06-25 | Applied Materials, Inc. | Processing system and method of forming a contact |
US11195923B2 (en) | 2018-12-21 | 2021-12-07 | Applied Materials, Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
CN113678260A (zh) | 2019-02-08 | 2021-11-19 | 应用材料公司 | 半导体器件、制作半导体器件的方法及处理系统 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4443930A (en) * | 1982-11-30 | 1984-04-24 | Ncr Corporation | Manufacturing method of silicide gates and interconnects for integrated circuits |
JPS61251170A (ja) * | 1985-04-30 | 1986-11-08 | Fujitsu Ltd | Mis型半導体装置の製造方法 |
JPS6476759A (en) * | 1987-09-17 | 1989-03-22 | Seiko Instr & Electronics | Tungsten silicide film and manufacture thereof |
JP2740722B2 (ja) * | 1992-06-29 | 1998-04-15 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US5428244A (en) * | 1992-06-29 | 1995-06-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a silicon rich dielectric layer |
JPH09205152A (ja) * | 1996-01-25 | 1997-08-05 | Sony Corp | 2層ゲート電極構造を有するcmos半導体装置及びその製造方法 |
JP2785810B2 (ja) * | 1996-06-27 | 1998-08-13 | 日本電気株式会社 | 半導体装置の製造方法 |
US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
JP3635843B2 (ja) * | 1997-02-25 | 2005-04-06 | 東京エレクトロン株式会社 | 膜積層構造及びその形成方法 |
US5827762A (en) * | 1997-05-02 | 1998-10-27 | National Semiconductor Corporation | Method for forming buried interconnect structue having stability at high temperatures |
-
1998
- 1998-01-21 US US09/010,081 patent/US6130145A/en not_active Expired - Lifetime
-
1999
- 1999-01-07 TW TW088100188A patent/TW409296B/zh not_active IP Right Cessation
- 1999-01-16 EP EP99100773A patent/EP0932186A3/en not_active Withdrawn
- 1999-01-19 JP JP11010404A patent/JPH11265992A/ja active Pending
- 1999-01-19 CN CN99101316A patent/CN1230780A/zh active Pending
- 1999-01-21 KR KR1019990001722A patent/KR100571356B1/ko not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106558474A (zh) * | 2015-09-25 | 2017-04-05 | 应用材料公司 | 通过约束来进行的硅化物相控制 |
CN106558474B (zh) * | 2015-09-25 | 2022-02-01 | 应用材料公司 | 通过约束来进行的硅化物相控制 |
CN108701711A (zh) * | 2016-02-17 | 2018-10-23 | 通用电气公司 | 用于宽带隙半导体功率器件的原位掺杂的半导体栅电极的系统和方法 |
Also Published As
Publication number | Publication date |
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JPH11265992A (ja) | 1999-09-28 |
US6130145A (en) | 2000-10-10 |
KR100571356B1 (ko) | 2006-04-17 |
TW409296B (en) | 2000-10-21 |
EP0932186A3 (en) | 1999-08-18 |
KR19990068032A (ko) | 1999-08-25 |
EP0932186A2 (en) | 1999-07-28 |
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