CN118696378A - 使用半导体元件的内存装置 - Google Patents
使用半导体元件的内存装置 Download PDFInfo
- Publication number
- CN118696378A CN118696378A CN202180105433.1A CN202180105433A CN118696378A CN 118696378 A CN118696378 A CN 118696378A CN 202180105433 A CN202180105433 A CN 202180105433A CN 118696378 A CN118696378 A CN 118696378A
- Authority
- CN
- China
- Prior art keywords
- layer
- line
- voltage
- gate
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/693—Vertical IGFETs having charge trapping gate insulators
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/045965 WO2023112122A1 (ja) | 2021-12-14 | 2021-12-14 | 半導体素子を用いたメモリ装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118696378A true CN118696378A (zh) | 2024-09-24 |
Family
ID=86694850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180105433.1A Pending CN118696378A (zh) | 2021-12-14 | 2021-12-14 | 使用半导体元件的内存装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US12277962B2 (https=) |
| JP (1) | JPWO2023112122A1 (https=) |
| KR (1) | KR20240113970A (https=) |
| CN (1) | CN118696378A (https=) |
| WO (1) | WO2023112122A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118235532A (zh) * | 2021-11-09 | 2024-06-21 | 新加坡优尼山帝斯电子私人有限公司 | 半导体内存装置及半导体内存装置的制造方法 |
| WO2024042609A1 (ja) * | 2022-08-23 | 2024-02-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2024079816A1 (ja) * | 2022-10-12 | 2024-04-18 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2024134761A1 (ja) * | 2022-12-20 | 2024-06-27 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| JPWO2025013138A1 (https=) | 2023-07-07 | 2025-01-16 | ||
| WO2025074607A1 (ja) * | 2023-10-06 | 2025-04-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2025088683A1 (ja) * | 2023-10-24 | 2025-05-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2703970B2 (ja) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | Mos型半導体装置 |
| JPH03171768A (ja) | 1989-11-30 | 1991-07-25 | Toshiba Corp | 半導体記憶装置 |
| JP3957774B2 (ja) | 1995-06-23 | 2007-08-15 | 株式会社東芝 | 半導体装置 |
| JP3808763B2 (ja) | 2001-12-14 | 2006-08-16 | 株式会社東芝 | 半導体メモリ装置およびその製造方法 |
| JP2004326864A (ja) * | 2003-04-22 | 2004-11-18 | Toshiba Corp | 不揮発性半導体メモリ |
| JP3898715B2 (ja) | 2004-09-09 | 2007-03-28 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP4083160B2 (ja) * | 2004-10-04 | 2008-04-30 | 株式会社東芝 | 半導体記憶装置およびfbcメモリセルの駆動方法 |
| JP5078338B2 (ja) | 2006-12-12 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4791986B2 (ja) | 2007-03-01 | 2011-10-12 | 株式会社東芝 | 半導体記憶装置 |
| US8654592B2 (en) * | 2007-06-12 | 2014-02-18 | Micron Technology, Inc. | Memory devices with isolation structures |
| JP2009252264A (ja) * | 2008-04-02 | 2009-10-29 | Toshiba Corp | 半導体記憶装置およびその駆動方法 |
| US8441053B2 (en) * | 2010-10-15 | 2013-05-14 | Powerchip Technology Corporation | Vertical capacitor-less DRAM cell, DRAM array and operation of the same |
| US8902663B1 (en) * | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
| US9548119B2 (en) * | 2014-01-15 | 2017-01-17 | Zeno Semiconductor, Inc | Memory device comprising an electrically floating body transistor |
| US10074438B2 (en) * | 2016-06-10 | 2018-09-11 | Cypress Semiconductor Corporation | Methods and devices for reducing program disturb in non-volatile memory cell arrays |
| EP4193181A4 (en) * | 2020-09-11 | 2024-08-21 | Sense Photonics, Inc. | MEMORY PIXEL WITH GAIN CELLS AND ACTIVATION/RECHARGE ACTIVATED CLOCKED |
| CN118235532A (zh) * | 2021-11-09 | 2024-06-21 | 新加坡优尼山帝斯电子私人有限公司 | 半导体内存装置及半导体内存装置的制造方法 |
-
2021
- 2021-12-14 CN CN202180105433.1A patent/CN118696378A/zh active Pending
- 2021-12-14 KR KR1020247022970A patent/KR20240113970A/ko not_active Ceased
- 2021-12-14 WO PCT/JP2021/045965 patent/WO2023112122A1/ja not_active Ceased
- 2021-12-14 JP JP2023567312A patent/JPWO2023112122A1/ja active Pending
-
2022
- 2022-12-08 US US18/077,895 patent/US12277962B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20230186966A1 (en) | 2023-06-15 |
| JPWO2023112122A1 (https=) | 2023-06-22 |
| WO2023112122A1 (ja) | 2023-06-22 |
| KR20240113970A (ko) | 2024-07-23 |
| US12277962B2 (en) | 2025-04-15 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |