JPWO2025013138A1 - - Google Patents

Info

Publication number
JPWO2025013138A1
JPWO2025013138A1 JP2025532234A JP2025532234A JPWO2025013138A1 JP WO2025013138 A1 JPWO2025013138 A1 JP WO2025013138A1 JP 2025532234 A JP2025532234 A JP 2025532234A JP 2025532234 A JP2025532234 A JP 2025532234A JP WO2025013138 A1 JPWO2025013138 A1 JP WO2025013138A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2025532234A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2025013138A1 publication Critical patent/JPWO2025013138A1/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/20DRAM devices comprising floating-body transistors, e.g. floating-body cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
JP2025532234A 2023-07-07 2023-07-07 Pending JPWO2025013138A1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/025322 WO2025013138A1 (ja) 2023-07-07 2023-07-07 半導体素子を用いたメモリ装置

Publications (1)

Publication Number Publication Date
JPWO2025013138A1 true JPWO2025013138A1 (https=) 2025-01-16

Family

ID=94175760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2025532234A Pending JPWO2025013138A1 (https=) 2023-07-07 2023-07-07

Country Status (3)

Country Link
US (1) US12592278B2 (https=)
JP (1) JPWO2025013138A1 (https=)
WO (1) WO2025013138A1 (https=)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2703970B2 (ja) 1989-01-17 1998-01-26 株式会社東芝 Mos型半導体装置
JPH03171768A (ja) 1989-11-30 1991-07-25 Toshiba Corp 半導体記憶装置
JP3808763B2 (ja) 2001-12-14 2006-08-16 株式会社東芝 半導体メモリ装置およびその製造方法
JP5010192B2 (ja) * 2006-06-22 2012-08-29 株式会社東芝 不揮発性半導体記憶装置
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR101442175B1 (ko) * 2008-05-23 2014-09-18 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 메모리 셀 어레이의 배치방법
US8755227B2 (en) * 2012-01-30 2014-06-17 Phison Electronics Corp. NAND flash memory unit, NAND flash memory array, and methods for operating them
JP2021048324A (ja) * 2019-09-19 2021-03-25 キオクシア株式会社 メモリデバイス
US20220367473A1 (en) 2020-12-25 2022-11-17 Unisantis Electronics Singapore Pte. Ltd. Memory device using semiconductor element
CN116724354A (zh) 2020-12-25 2023-09-08 新加坡优尼山帝斯电子私人有限公司 包含半导体元件的存储器装置
WO2022239237A1 (ja) 2021-05-14 2022-11-17 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
EP4454432A4 (en) 2021-10-01 2025-12-03 Neo Semiconductor Inc 3D MEMORY CELLS AND NETWORK ARCHITECTURES
CN118696378A (zh) 2021-12-14 2024-09-24 新加坡优尼山帝斯电子私人有限公司 使用半导体元件的内存装置

Also Published As

Publication number Publication date
US12592278B2 (en) 2026-03-31
US20250014636A1 (en) 2025-01-09
WO2025013138A1 (ja) 2025-01-16

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Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20251222