Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells

Definitions

• the present invention is a memory device that uses semiconductor elements.
• DRAM Dynamic Random Access Memory
• SGT Square Gate Transistor
• Patent Document 1 and Non-Patent Document 1 a selection transistor and connects a capacitor
• PCM Phase Change Memory
• RRAM Resistive Random Access Memory
• Non-Patent Document 4 a resistive variable element
• MRAM Magnetic-resistive Random Access Memory
• DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of one MOS transistor without a capacitor.
• a source-drain current of an N-channel MOS transistor generates holes and electrons in the channel by impact ionization, and some or all of the holes are retained in the channel to write logical memory data "1". Then, the holes are removed from the channel to write logical memory data "0".
• the memory cell there are random memory cells with "1” written and memory cells with "0" written for a common selected word line.
• the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates greatly due to the capacitive coupling between the gate electrode and the channel.
• the issues are to improve the decrease in operating margin due to the floating body channel voltage fluctuation, and to improve the decrease in data retention characteristics due to the removal of some of the holes, which are the signal charges stored in the channel.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11).
• an N + layer which serves as a source or drain and separates the floating body channels of the two MOS transistors, is formed in contact with an insulating layer on the substrate side.
• This N + layer electrically separates the floating body channels of the two MOS transistors.
• a group of holes which is a signal charge, is stored only in the floating body channel of one MOS transistor.
• the other MOS transistor serves as a switch for reading out the group of holes of the signal stored in the other MOS transistor.
• the group of holes which is a signal charge, is stored in the channel of one MOS transistor, so that, as in the memory cell consisting of one MOS transistor described above, the problem is to improve the decrease in the operating margin or to improve the decrease in data retention characteristics caused by removing part of the group of holes, which is the signal charge stored in the channel.
• FIG. 3 there is a dynamic flash memory cell 111 composed of a MOS transistor without a capacitor (see Patent Document 5 and Non-Patent Document 12).
• a floating body semiconductor body 102 on a SiO 2 layer 101 of an SOI substrate.
• an N + layer 103 connected to a source line SL and an N + layer 104 connected to a bit line BL.
• first gate insulating layer 109a connected to the N + layer 103 and covering the floating body semiconductor body 102
• second gate insulating layer 109b connected to the first gate insulating layer 109a via the N + layer 104 and the slit insulating film 110 and covering the floating body semiconductor body 102.
• first gate conductor layer 105a that covers the first gate insulating layer 109a and is connected to the plate line PL
• second gate conductor layer 105b that covers the second gate insulating layer 109b and is connected to the word line WL.
• a slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b.
• DFM Dynamic Flash Memory
• a zero voltage is applied to the N + layer 103, and a positive voltage is applied to the N + layer 104, so that the first N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the first gate conductor layer 105a is operated in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the second gate conductor layer 105b is operated in the linear region.
• no pinch-off point exists in the second N-channel MOS transistor region, and an inversion layer 107b is formed over the entire surface.
• the inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region.
• the memory write operation is performed by removing the electrons from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state becomes logical storage data "1".
• a positive voltage is applied to the plate line PL
• a zero voltage is applied to the word line WL and the bit line BL
• a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor body 102 to perform an erase operation.
• This state becomes logical memory data "0".
• the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical memory data is "1" and lower than the threshold voltage when the logical memory data is "0", thereby obtaining a characteristic in which no current flows even if the voltage of the word line WL is increased when reading logical memory data "0", as shown in FIG. 3(d).
• This characteristic allows a significant expansion of the operating margin compared to a DRAM memory cell composed of a single MOS transistor without a capacitor.
• the channels of the first and second N-channel MOS transistor regions whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed.
• a dynamic flash memory cell 8 having three gates and composed of a MOS transistor without a capacitor is known (see Patent Document 6 and Non-Patent Document 13).
• a silicon semiconductor pillar (Si pillar) 2 is provided on a substrate 1.
• the Si pillar 2 has an N+ layer 3a, a P layer 7, and an N+ layer 3b from below.
• the P layer 7 between the N+ layers 3a and 3b becomes a channel region 7a.
• Surrounding the lower part of the Si pillar 2 from below are a first gate insulating layer 4a, a second gate insulating layer 4b, and a third gate insulating layer 4c.
• first gate conductor layer 5a Surrounding the first gate insulating layer 4a is a first gate conductor layer 5a, surrounding the second gate insulating layer 4b is a second gate conductor layer 5b, and surrounding the third gate insulating layer 4c is a third gate conductor layer 5c.
• the first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6a, and the second gate conductor layer 5b and the third gate conductor layer 5c are separated by an insulating layer 6b.
• a feature of this structure is that the recombination of the holes stored in the channel region 7a between the N+ layers 3a and 3b is significantly suppressed in the N+ layers 3a and 3b by utilizing the electrical shielding between the first gate conductor layer 5a and the third gate conductor layer 5c. As a result, the retention characteristic of data "1" is significantly improved.
• the dynamic flash memory cells can be arranged horizontally on the substrate 1, and multiple memory cells can be stacked vertically to increase the degree of integration (see Patent Document 8).
• the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c can be divided (see, for example, Patent Document 9 and Non-Patent Document 18).
• Non-Patent Documents 14 and 15 a thyristor RAM memory with three gates and no capacitor has been announced (see Non-Patent Documents 14 and 15).
• This thyristor memory has the advantage that the equivalent memory cell size can be reduced by stacking multiple layers, but because it uses a thyristor as the read mechanism, there is a problem that the read current value increases or decreases significantly, resulting in high power consumption.
• Non-Patent Documents 16 and 17 a 1T1C DRAM cell with a stackable capacitor has been announced (see Non-Patent Documents 16 and 17).
• the aspect ratio of the capacitor in a DRAM memory cell is large at 50. Therefore, when a DRAM cell is placed horizontally, the area of this capacitor is very large, and in order to obtain an equivalent area to an economical memory cell like a current vertically placed DRAM cell, for example, 200 layers must be stacked.
• Critoloveanu “A Compact Capacitor-Less High-Speed DRAM Using F ield Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp.179-181 (2012) T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory d esign using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002). T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N.
• a memory device using a semiconductor element comprises: a first block in which a plurality of semiconductor memory cells including a first memory cell and a second memory cell are arranged in a matrix on a substrate;
• the first memory cell includes a first semiconductor body extending parallel to the substrate, and the second memory cell includes a second semiconductor body separated vertically or horizontally from the first semiconductor body and overlapping the first semiconductor body in a plan view or a cross-sectional view;
• the first block comprises: a first impurity region and a second impurity region connected to both ends of the first semiconductor body, a third impurity region and a fourth impurity region respectively connected to both ends of the second semiconductor body; a first gate insulating layer surrounding the first semiconductor body; a second gate insulating layer surrounding the second semiconductor body; a first gate conductor layer and a second gate conductor layer in contact with a first side surface of the first gate insulating layer and the second gate insulating layer, respectively, and connected to
• a second invention is the transistor according to the first invention, wherein the first and third impurity regions are connected to a source line, the second impurity region is connected to a first bit line, the fourth impurity region is connected to a second bit line, and when one of the first gate conductor layer and the second gate conductor layer is connected to a select gate line, the other is connected to a plate line, and the third gate conductor layer is connected to a shield line; controlling voltages applied to the source line, the first and second bit lines, the plate line, the select gate line, and the shield line to perform the data erase operation, the data write operation, and the data read operation; It is characterized by:
• the third invention is the second invention described above, characterized in that a ground voltage is applied to the shielded line during the data erase operation, the data write operation, and the data read operation.
• the fourth invention is the third invention described above, characterized in that the ground voltage is zero volts.
• the fifth invention is the second invention described above, characterized in that the first and second semiconductor bodies overlap in a cross-sectional view of the substrate, and the plate line, the select gate line, and the shield line are arranged parallel to the substrate in a plan view.
• the sixth invention is the second invention, characterized in that the first and second bit lines are orthogonal to the plate line, the select gate line, and the shield line in a vertical cross-sectional view relative to the substrate, and the source line is arranged parallel to the plate line, the select gate line, and the shield line in a plan view.
• the seventh invention is the second invention described above, characterized in that the first and second semiconductor bodies overlap in a plan view of the substrate, and the plate line, the select gate line, and the shield line are arranged parallel to the substrate in a cross-sectional view.
• the eighth invention is the second invention, characterized in that the first and second bit lines are perpendicular to the plate line, the select gate line, and the shield line in a plan view of the substrate, and the source line is arranged parallel to the plate line, the select gate line, and the shield line in a cross-sectional view of the substrate.
• the ninth invention is the first invention described above, characterized in that it has a fourth gate conductor layer that contacts the first side surface of each of the first gate insulating layer and the second gate insulating layer and is aligned with the first and second gate conductor layers.
• the tenth invention is the ninth invention, characterized in that the fourth gate conductor layer is connected to a second select gate line.
• the eleventh invention is characterized in that in the second invention, the channel length of the second gate conductor layer is longer than either or both of the channel length of the first gate conductor layer and the channel length of the third gate conductor layer.
• the twelfth invention is the first invention, characterized in that the third gate conductor layer is made up of the first gate conductor layer, a fifth gate conductor layer facing the second gate conductor layer, and a sixth gate conductor layer.
• the thirteenth invention is characterized in that, in the first invention, a second block including a third memory cell and a fourth memory cell overlapping the first block in a plan view or cross-sectional view is included.
• 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; 1 is a structural diagram of a memory cell according to a first embodiment; A diagram illustrating a dynamic flash memory cell composed of MOS transistors and not having a capacitor as in the conventional example. A diagram illustrating a dynamic flash memory cell having three gates and composed of MOS transistors, without a capacitor as in the conventional example.
• dynamic flash memory The structure and driving method of a memory device using semiconductor elements (hereafter referred to as dynamic flash memory) according to the present invention will be explained below with reference to the drawings.
• Figures 1A to 1F and Figures 2A and 2B will be described with reference to Figures 1A to 1F and Figures 2A and 2B.
• Figures 1A and 1B will be used to describe a structure in which bit lines are arranged vertically with respect to a substrate, and first and second select gate lines and a plate line are arranged horizontally.
• Figure 2 will be used to describe a structure in which bit lines are arranged horizontally with respect to a substrate, and first and second select gate lines and a plate line are arranged vertically.
• FIG. 1A shows a bird's-eye view of the dynamic flash memory cell structure according to the first embodiment of the present invention.
• FIG. 1B(a) shows a plan view of the dynamic flash memory cell structure according to the first embodiment of the present invention
• FIG. 1B(b) and FIG. 1B(c) show the X-X' and Y-Y' cross-sectional views, respectively.
• a first semiconductor body 14 (an example of the "first semiconductor body” in the claims) of a P layer is parallel to a substrate 10 (an example of the "substrate” in the claims).
• Patent Document 8 is a document relating to a structure in which dynamic flash memory cells are provided horizontally with respect to the substrate 10.
• N + layer 16 an example of the "first impurity region” in the claims
• N + layer 17 an example of the "second impurity region” in the claims
• a second semiconductor body 15 of a P layer an example of the "second semiconductor body” in the claims
• an N + layer 18 an example of the "third impurity region” in the claims
• an N + layer 19 an example of the "fourth impurity region” in the claims
• a first gate insulating film 20 (an example of the "first gate insulating film” in the claims) and a second gate insulating film 21 (an example of the “second gate insulating film” in the claims) are formed around the first semiconductor body 14 and the second semiconductor body 15.
• the first gate conductor layer 11 (an example of the "first gate conductor layer” in the claims), the second gate conductor layer 12 (an example of the “second gate conductor layer” in the claims), and the fourth gate conductor layer 13, which are separated from each other, are in contact with the first side surface (an example of the "first side surface” in the claims) of each of the first gate insulating layer 20 and the second gate insulating layer 21.
• third gate conductor layer 22, 23, 24 (an example of the "third gate conductor layer” in the claims) which is in contact with the second side surface (an example of the "second side surface” in the claims) facing the first side surface of the first gate insulating layer 20 and the second gate insulating layer 21 and serves as a common gate for the first semiconductor body 14 and the second semiconductor body 15.
• the third gate conductor layer is shown as three separate gate conductor layers, but it may be a single gate conductor layer.
• the first gate conductor layer 11 and the fourth gate conductor layer 13 may be omitted, as shown in Figures 1D and 1E, respectively.
• the first impurity region 16 and the third impurity region 18 are connected to SL, which is a source line 25 (an example of a "source line” in the claims), the second impurity region 17 is connected to BL0, which is a first bit line 26 (an example of a "first bit line” in the claims), and the fourth impurity region 19 is connected to BL1, which is a second bit line 27 (an example of a "second bit line” in the claims).
• the first gate conductor layer 11 is connected to a first select gate line SG1 (an example of a "select gate line” in the claims)
• the second gate conductor layer 12 is connected to a plate line PL (an example of a "plate line” in the claims)
• the fourth gate conductor layer 13 is connected to a second select gate line SG2
• the third gate conductor layers 22, 23, and 24 are connected to shield lines SHA, SHB, and SHC (an example of a "shield line” in the claims).
• the six terminals of the first memory cell are composed of the first select gate line SG1, the plate line PL, the second select gate line SG2, the shield lines SHA, SHB, SHC, the source line SL, and the first bit line BL0
• the six terminals of the second memory cell are composed of the first select gate line SG1, the plate line PL, the second select gate line SG2, the shield lines SHA, SHB, SHC, the source line SL, and the second bit line BL1.
• the first memory cell and the second memory cell form a part of the first block (an example of the "first block" in the claims).
• the voltages applied to the source line SL, the first bit line BL0, the second bit line BL1, the plate line PL, the first select gate line SG1, the second select gate line SG2, and the shield lines SHA, SHB, and SHC are controlled to perform a data erase operation, a data write operation, and a data read operation for the first memory cell and the second memory cell.
• zero volts which is the ground voltage
• the shield lines SHA, SHB, and SHC is applied to the shield lines SHA, SHB, and SHC.
• the silicon film thickness of the floating body can be made thinner. Even if multiple memory cells are stacked, the aspect ratio can be reduced, making it possible to stack more memory cells, thereby achieving further cost reduction.
• Figure 1C shows an example in which the channel length of the plate line PL (length in the X-X' line direction) is longer than the first select gate line SG1 and the second select gate line SG2. This provides excellent control of the plate line voltage for the floating body of the memory cell. Also, depending on the channel length (gate length) of the plate line, the floating body in the "1" write state can hold more holes.
• Figure 1D shows an example where the first select gate line SG1 adjacent to the source line SL has been eliminated.
• Figure 1E shows an example where the second select gate line SG2 adjacent to the bit lines BL0 and BL1 has been eliminated.
• This allows the cell size of the dynamic flash memory cell to be further miniaturized. It also allows the cell current to be increased, making it possible to achieve higher speeds.
• eliminating one of the select gates has the drawback of reducing data retention capability, it provides better control of the plate line voltage relative to the floating body of the memory cell. Also, depending on the gate length of the plate line, the floating body in the "1" write state can hold more holes. This is a design choice for applications using dynamic flash memory cells.
• Figure 1F shows an example of two stacked dynamic flash memory cells. Shield lines SHA0, SHB0, and SHC0 shield the memory cells of the first block, and shield lines SHA1, SHB1, and SHC1 shield the memory cells of the second block.
• FIG. 2A shows an example in which a first select gate line SG1, a plate line PL, a second select gate line SG2, and a source line SL are arranged vertically with respect to the substrate 10, and a first bit line BL0 and a second bit line BL1 are arranged horizontally.
• this corresponds to the dynamic flash memory cell shown in FIGS. 1A to 1F rotated 90 degrees toward the back of the drawing with respect to the substrate 10.
• this is a design choice for applications using dynamic flash memory cells, the main features are similar to those of the dynamic flash memory cell shown in FIGS. 1A to 1F.
• FIG. 2B shows an example of two dynamic flash memory cells stacked horizontally on a substrate 10.
• dynamic flash memory cells shown in Figures 1A to 1F and Figures 2A and 2B have been described using components with rectangular vertical cross sections, these vertical cross-sectional shapes may be other shapes, such as trapezoidal, for example. Furthermore, the vertical cross sections of each component may be different. This is the same for the other embodiments.
• Dynamic flash memory operation can also be performed in a structure in which the conductivity of the semiconductor body of the N + layers 16, 17, 18, and 19 and the P layers 14 and 15 of the dynamic flash memory cell shown in Figures 1A and 1B are reversed.
• the majority carriers become electrons. Therefore, a group of electrons generated by impact ionization is stored in the floating body, setting the "1" state.
• the dynamic flash memory cell shown in Figures 1A and 1B may have a junctionless structure in which the conductivity of the semiconductor body of the N + layers 16, 17, 18, and 19 and the P layers 14 and 15 are made the same. This is the same for the other embodiments.
• the fourth gate conductor layers 22, 23, and 24 are made to function as shield gates.
• the potential of the floating body semiconductor bases 14 and 15 during operation can be stabilized.
• the floating body semiconductor bases 14 and 15 can be thinned.
• the aspect ratio of the stacked memory cells is reduced, allowing a larger number of memory cells to be stacked, thereby reducing costs. This also applies to the memory cells shown in Figures 1C to 2B.
• the gate conductor layer connected to the plate line may be a single layer or a combination of multiple conductor material layers.
• the gate conductor layer connected to the first and second select gate lines may be a single layer or a combination of multiple conductor material layers.
• the outside of the gate conductor layer may be connected to a wiring metal layer such as W. This also applies to other embodiments of the present invention.
• the voltage applied to the plate line PL in the description of the embodiment may be a fixed voltage of, for example, 0 V, regardless of the operating mode.
• the voltage applied to the plate line PL may be a fixed voltage or a voltage that changes over time, as long as the voltage satisfies the conditions for dynamic flash memory operation.
• an N-type or P-type impurity region may be present between the first impurity region N + layer 16 and/or the second impurity region N + layer 17 and the first semiconductor body P layer 14. This also applies to other embodiments of the present invention.
• the memory device using semiconductor elements according to the present invention provides a high-density, high-performance dynamic flash memory.

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