KR20240113970A - 반도체 소자를 사용한 메모리 장치 - Google Patents

반도체 소자를 사용한 메모리 장치 Download PDF

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Publication number
KR20240113970A
KR20240113970A KR1020247022970A KR20247022970A KR20240113970A KR 20240113970 A KR20240113970 A KR 20240113970A KR 1020247022970 A KR1020247022970 A KR 1020247022970A KR 20247022970 A KR20247022970 A KR 20247022970A KR 20240113970 A KR20240113970 A KR 20240113970A
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South Korea
Prior art keywords
layer
line
voltage
gate
conductor layer
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KR1020247022970A
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English (en)
Korean (ko)
Inventor
리이치로 시로타
고지 사쿠이
노조무 하라다
Original Assignee
유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드
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Publication of KR20240113970A publication Critical patent/KR20240113970A/ko
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H01L29/7926—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
KR1020247022970A 2021-12-14 2021-12-14 반도체 소자를 사용한 메모리 장치 Ceased KR20240113970A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/045965 WO2023112122A1 (ja) 2021-12-14 2021-12-14 半導体素子を用いたメモリ装置

Publications (1)

Publication Number Publication Date
KR20240113970A true KR20240113970A (ko) 2024-07-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247022970A Ceased KR20240113970A (ko) 2021-12-14 2021-12-14 반도체 소자를 사용한 메모리 장치

Country Status (5)

Country Link
US (1) US12277962B2 (https=)
JP (1) JPWO2023112122A1 (https=)
KR (1) KR20240113970A (https=)
CN (1) CN118696378A (https=)
WO (1) WO2023112122A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118235532A (zh) * 2021-11-09 2024-06-21 新加坡优尼山帝斯电子私人有限公司 半导体内存装置及半导体内存装置的制造方法
WO2024042609A1 (ja) * 2022-08-23 2024-02-29 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
WO2024079816A1 (ja) * 2022-10-12 2024-04-18 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
WO2024134761A1 (ja) * 2022-12-20 2024-06-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
JPWO2025013138A1 (https=) 2023-07-07 2025-01-16
WO2025074607A1 (ja) * 2023-10-06 2025-04-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
WO2025088683A1 (ja) * 2023-10-24 2025-05-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置

Citations (4)

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JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
JPH03171768A (ja) 1989-11-30 1991-07-25 Toshiba Corp 半導体記憶装置
US20030111681A1 (en) 2001-12-14 2003-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device and its manufacturing method
US20080137394A1 (en) 2006-12-12 2008-06-12 Renesas Technology Corp. Semiconductor memory device

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JP3957774B2 (ja) 1995-06-23 2007-08-15 株式会社東芝 半導体装置
JP2004326864A (ja) * 2003-04-22 2004-11-18 Toshiba Corp 不揮発性半導体メモリ
JP3898715B2 (ja) 2004-09-09 2007-03-28 株式会社東芝 半導体装置およびその製造方法
JP4083160B2 (ja) * 2004-10-04 2008-04-30 株式会社東芝 半導体記憶装置およびｆｂｃメモリセルの駆動方法
JP4791986B2 (ja) 2007-03-01 2011-10-12 株式会社東芝 半導体記憶装置
US8654592B2 (en) * 2007-06-12 2014-02-18 Micron Technology, Inc. Memory devices with isolation structures
JP2009252264A (ja) * 2008-04-02 2009-10-29 Toshiba Corp 半導体記憶装置およびその駆動方法
US8441053B2 (en) * 2010-10-15 2013-05-14 Powerchip Technology Corporation Vertical capacitor-less DRAM cell, DRAM array and operation of the same
US8902663B1 (en) * 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US9548119B2 (en) * 2014-01-15 2017-01-17 Zeno Semiconductor, Inc Memory device comprising an electrically floating body transistor
US10074438B2 (en) * 2016-06-10 2018-09-11 Cypress Semiconductor Corporation Methods and devices for reducing program disturb in non-volatile memory cell arrays
EP4193181A4 (en) * 2020-09-11 2024-08-21 Sense Photonics, Inc. MEMORY PIXEL WITH GAIN CELLS AND ACTIVATION/RECHARGE ACTIVATED CLOCKED
CN118235532A (zh) * 2021-11-09 2024-06-21 新加坡优尼山帝斯电子私人有限公司 半导体内存装置及半导体内存装置的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
JPH03171768A (ja) 1989-11-30 1991-07-25 Toshiba Corp 半導体記憶装置
US20030111681A1 (en) 2001-12-14 2003-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device and its manufacturing method
US20080137394A1 (en) 2006-12-12 2008-06-12 Renesas Technology Corp. Semiconductor memory device

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E. Yoshida : "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE IEDM (2006).
E. Yoshida, and T. Tanaka : "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE Transactions on Electron Devices, Vol.53, No.4, pp.692 - 69, Apr. 2006.
H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, Y. C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung : "4F2 DRAM Cell with Vertical Pillar Transistor (VPT)," 2011 Proceeding of the European Solid-State Device Research Conference, (2011)
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T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama : "Floating Body RAM Technology and its Scalability to 32㎚ Node and Beyond," IEEE IEDM (2006).
T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama : "Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V, " IEDM (2007)
W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao : "Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology," IEEE Transaction on Electron Devices, pp.1 - 9 (2015)
오오사와 타카시 : 「단일 FET 셀을 사용한 SOI DRAM」 응용 물리 제 75 권 제 9 호, 페이지 1131 - 1135 2006년.

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US20230186966A1 (en) 2023-06-15
JPWO2023112122A1 (https=) 2023-06-22
WO2023112122A1 (ja) 2023-06-22
CN118696378A (zh) 2024-09-24
US12277962B2 (en) 2025-04-15

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