CN1186811C - 补偿型金属氧化物半导体器件结构及其制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 title description 4
- 150000004706 metal oxides Chemical class 0.000 title description 4
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000002019 doping agent Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 16
- 229910052799 carbon Inorganic materials 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000007952 growth promoter Substances 0.000 claims description 8
- 239000003112 inhibitor Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009421 internal insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
本发明公开一种半导体结构及其制造方法，它包括：提供具有下部绝缘体层的硅表面；制备多个邻近源极/漏极区的栅极；在所述栅极之间生长源极/漏极，使得所述源极/漏极在更大的栅极至栅极间距的区域内更厚；以及用一种或多种掺杂剂掺杂所述源极/漏极，使得所述掺杂剂毗邻于所述下部绝缘体层。
Description
技术领域
本发明涉及半导体技术领域，特别涉及改良的补偿型金属氧化物半导体(CMOS)器件及其制造方法。
背景技术
补偿型金属氧化物半导体(CMOS)的制造，例如金属氧化物半导体场效应晶体管(MOSFET)，在本领域中是众所周知的。然而，随着技术发展推进到更高的性能而且晶体管尺寸降低，已确认了三个主要问题，即峡谷效应(canyon effect)、选择性外延生长的小面效应和掺杂剂的横向再分布。
峡谷效应出现在例如没有源极或漏极金属触点的叠置MOSFET结构中，诸如在NFET(N沟道FET)系列中。在此情况中，用于深源极和漏极的掺杂量受邻近栅极间距离(即，栅极至栅极间距)的影响。当栅极至栅极间距减小，深源极/漏极(S/D)的掺杂也减小。当源极/漏极掺杂剂通过相邻栅极间较小的开口而被注入时，较少量的掺杂剂被引入S/D区，该区倾向于向外扩散并明显减小掺杂剂的峰值浓度。当在硅绝缘体(SOI)基板上形成S/D掺杂时，作为栅极到栅极间距的函数，在较小的栅极到栅极间距内的较少掺杂的S/D区引发严重的问题，诸如由S/D掺杂与SOI掩埋氧化物界面的不完全界限导致的邻近器件间的不完全结隔离。此结果是相邻器件间的漏电流，以及用这些器件的电路运行中下降的性能和无规律性。
小面效应作为形成凸起的源极/漏极(RSD)结构以避免SOI器件中硅化物接触成形问题并潜在地减小S/D电阻的结果而发生。为了更高的工作性能而需要RSD结构。目前，因为作为晶体取向和空间群几何结构的函数的外延生长速率的不同，对在栅极侧壁上形成的小面的控制很差。晶体的小面形成是自由能最小化的热力学结果。根据侧壁的取向和生长条件，各种小面在二氧化硅(SiO2)栅极的侧壁上形成，尤其是在硅或硅锗(SiGe)的外延生长过程中。在小面的形状和轮廓上的不可控变化干扰通过注入法的临界掺杂，通常迫使在RSD外延生长前延伸和环形掺杂的应用。因为延伸和环形掺杂显示了选择性外延生长热过程中的瞬态强化扩散(TED)，所以此结果恶化了短沟道性能。
延伸和环形掺杂剂的横向再分布导致恶化的短沟道效应，特别是当将栅极长度减小到0.1微米以下。最明显的短沟道效应是域值电压(Vt)下降。大量的理论研究表明Vt下降仅可以通过提供环形掺杂的更陡的横向梯度来改善，此梯度要求在深亚微米级器件的活化退火过程中环形掺杂剂的TED的减小或消除。在用于NFET环的硼或铟存在的情况下，这尤其是一个问题，众所周知硼或铟从S/D面上明显地向外扩散短至0.1微米的栅极长度。
本发明是在深亚微米尺度上制造CMOS结构的方法，该结构显示了减小的峡谷效应、小面效应和横向掺杂剂扩散。
发明内容
因此，本发明的目的是提供一种制造半导体结构的方法及其所制造的结构。根据本发明的方法制造的半导体结构可以减小峡谷效应、小面效应和横向掺杂剂扩散等问题。
为了实现本发明的目的，提供一种制造半导体结构的方法，包括：制备具有下部绝缘体层的硅表面；制备多个邻近于源极/漏极区的栅极；在所述栅极之间外延生长源极/漏极，使得所述源极/漏极在更大的栅极至栅极间距的区域内更厚；以及用一种或多种掺杂剂掺杂所述源极/漏极，使得所述掺杂剂毗邻于所述下部绝缘体层。
本发明还提供一种半导体结构，包括：具有下部绝缘体层的硅表面；位于所述硅表面上的栅极；位于栅极间的源极/漏极，所述源极/漏极在栅极至栅极间距更大的区域内更厚，并且所述源极/漏极包含一种或多种掺杂剂，使得所述掺杂剂接近下部绝缘体层。
附图说明
图1至8示出工艺的各步骤。
具体实施方式
参照图1，示出了典型的SOI(硅绝缘体)晶片，它包括在下部绝缘体层上的硅层1，此处绝缘体层为掩埋氧化物绝缘体层2。设置多个凸起的结构，此处是栅极3，它确定了其间的区域5，这些区域将被用以构造所示实施例中的源极/漏极。另外，示出了覆盖栅极3的氮化物衬垫3′，该栅极被可去除的第一隔离壁4包围。在半导体技术中，可去除的第一隔离壁被积极使用，并且可以包括多晶硅或氮化物，或使用两种材料的复合物。通常，氮化物衬垫由LPCVD形成(液相化学气相沉积)。一般地，第一隔离壁将是约200至约1000埃厚，并确定了栅极/漏极延伸部分9的长度。在另一实施例中，可以形成更薄的氧化物内部隔离壁11，以在S/D延伸部分布局中制备缓冲层，并保护栅极在可去除的第一隔离壁4的去除过程中免遭任何损坏。
参照图2，毗邻栅极3的源极/漏极区5用生长促进剂掺杂。该掺杂可以转动一角度以获得侧壁覆盖。用于硅外延生长的合适的生长促进剂是锗。图2示出具有从1E14至1E17(cm-2)的总剂量的成角度的锗注入，例如从1E15至2E16(cm-2)。在更大的栅极至栅极间距的区域内有必要有更高的生长促进剂注入6浓度，例如图中右侧所示的区域5。成角度的注入可以通过例如旋转晶片并以四种不同的倾斜方向(例如从顶侧、从底侧、从左侧和从右侧)进行四次注入而实现。倾角通常根据栅极的长径比(栅极高度/栅极长度)和最小的栅极至栅极间距而选取。通过这种方式，在最大的栅极至栅极间距的区域内可以获得例如锗(Ge)的更高的表面浓度。在小的和大的栅极至栅极间距的区域之间表面浓度之差可以达到两倍。优选低能注入(1至5keV)以实现Ge的更高表面浓度，并避免在最终退火中缺陷的形成。需要在注入之后在至少800℃的温度进行快速热退火，以使已经被Ge注入非晶化的表面再结晶。
参照图3，在生长促进剂注入后，运用硅外延生长以抬高源极/漏极7从约50埃到约300埃。外延生长将通常在从500℃到800℃的温度实现。注意，外延生长在更大的栅极到栅极间距的区域内产生更厚的层7。众所周知，SiGe的生长速率随Ge增加的浓度而明显增加，特别是在低温(例如，在600℃以下，例如约500℃)和低压的情况下，于是使锗成为对于硅外延生长的有用的生长促进剂。这被认为是因为在具有高Ge浓度的表面上氢脱附速率更高而发生。当在富锗表面上生长硅时，向生长前端的Ge偏析发生，籍此提高了膜的生长速率。在纯Ge表面上可以得到高达300％的生长速率的提高。结果是，具有最大的栅极3间的距离的区域将被形成得更高更快，因为这些区域具有来自先前步骤的最高Ge浓度。
参照图4，第一隔离壁4被去除，且在延伸区内和在凸出的源极/漏极7的表面上提供扩散抑制剂杂质8。第一隔离壁4可以通过多种工艺除去，如加稀HF的热磷酸。来自源极/漏极外延生长的任何小面形状的变化在此处都不重要，因为注入表面的主要轮廓由栅极的边缘限定。在硼和/或磷被用作杂质的地方，作为扩散抑制剂杂质8，碳将被发现是有用的。碳杂质将被用于仅在延伸区域9形成碳掺杂的Si或SiGe，在该区域需要对硼的瞬态强化扩散的抑制。因为碳的间隙俘获机制，碳被认为抑制硼和磷的扩散。在硅或SiGe层中即使少量碳的注入也被认为减小硼扩散高达两个数量级。利用这一事实，此处所述的工艺可以实现用于NFET的硼环和用于PFET(P沟道FET)的磷环的较陡的梯度。应当注意的是，碳对砷和锑具有相反的效应，即这些杂质的扩散被碳加强。为了避免对PFET内砷环的这种效应，需要在碳注入前掩蔽PFET活性区。
在图5中，制备了延伸和环形杂质。对于NFET器件，杂质通常是砷延伸区和硼环(或二氟化硼，BF2)，而PFET通常是用BF2延伸区(或硼)和砷环(或磷)杂质制造。
参照图6，在掺杂后，第二套氧化物隔离壁4′被制备以覆盖延伸区9和凸出的源极/漏极7的小面。制备第二隔离壁4′的方法是使用等离子体强化化学气相沉积，如在低于600℃的温度下。可以采用低温方法以避免退火和杂质的扩散。使第二隔离壁4′大小合适，以覆盖凸起的源极/漏极7的小面，因而消除后续掺杂过程中的任何小面效应。
参照图7，对选择性硅或SiGe可以施行第二外延生长层12，虽然此步骤是可选的。可以要求进一步增加源极/漏极的厚度以减小S/D串联电阻并避免在薄SOI器件上硅化物接触部形成中的问题。优选的是，根据SOI层的厚度，在源极/漏极7上沉积从50至300埃例如从100至200埃的附加材料12。对于低压下的SiGe外延，第二外延生长通常在从400℃至650℃如从500℃至550℃的温度下进行。注意，凸起的源极/漏极的最终厚度在较大的栅极至栅极间距的区域里更厚。还要注意，注入的碳此时夹在第一外延层7和第二外延层12之间。通常，碳注入的Si或SiGe层的薄层电阻和接触电阻可以在硅化作用后因碳的影响而增加。通过加入第二外延生长和在整个层中夹入碳，避免了碳注入S/D外延层的增大的电阻的问题。
参照图8，硅化作用前制造过程中的最后步骤是注入深源极/漏极杂质10，然后用在约1000℃的温度或被认为对此目的有效的任何温度下的快速热退火活化它们。此深掺杂将足够深以邻近于掩埋氧化物层2。因为在较小的栅极至栅极间距的区域内的材料堆积比在较大的栅极至栅极间距的区域内的薄，所以杂质将更容易穿透前者。因为杂质穿透得更深，它将邻近掩埋氧化物层2，并且因而减小峡谷效应。碳的存在防止了硼和磷杂质的横向扩散，并且因为来自第一外延层的主要小面被隔离壁4覆盖，所以小面效应被消除。还要注意，深源极/漏极结将更加一致地紧靠在经过不同尺寸的叠置器件的掩埋氧化物层2上。
需理解，此处公开的所有物理量，除非另外明确指出的，均不被解释为精确地等于公开的量，而是约等于公开的量。另外，仅仅如“约”或类似限定词的缺少不被解释为任何这种公开的物理量是精确量的明确表示，而不考虑这样的限定词是否相对于此处公开的任何其它物理量而被使用。
虽然已经示出和描述了优选实施例，但是在不背离本发明的实质和范围的情况下，可以对其作出各种修改与替换。于是，应当理解的是，仅通过图示的方法描述了本发明，并且，已在此处得以公开的这些图示和实施例不应被解释为对所附权利要求的限制。
Claims (19)
1.一种制造半导体结构的方法，包括：
制备具有下部绝缘体层的硅表面；
制备多个邻近于源极/漏极区的栅极；
在所述栅极之间外延生长源极/漏极，使得所述源极/漏极在更大的栅极至栅极间距的区域内更厚；以及
用一种或多种掺杂剂掺杂所述源极/漏极，使得所述掺杂剂毗邻于所述下部绝缘体层。
2.根据权利要求1所述的方法，其特征在于，在栅极间生长源极/漏极的所述操作还包括：
在更大的栅极至栅极间距的区域内在所述源极/漏极区中以更大的浓度注入生长促进剂。
3.根据权利要求2所述的方法，其特征在于，注入生长促进剂的所述操作还包括成角度的注入。
4.根据权利要求2所述的方法，其特征在于，所述生长促进剂是锗。
5.根据权利要求1所述的方法，其特征在于，所述下部绝缘体层是掩埋氧化物层。
6.根据权利要求1所述的方法，其特征在于，所述的一种或多种掺杂剂从砷、磷、硼和二氟化硼中选择。
7.根据权利要求1所述的方法，其特征在于，还包括制备与所述栅极邻近的第一隔离壁，以形成邻近所述栅极的延伸区。
8.根据权利要求7所述的方法，其特征在于，还包括：
在生长所述源极/漏极后去除所述第一隔离壁；以及
在所述延伸区中和源极/漏极上注入扩散抑制剂。
9.根据权利要求8所述的方法，其特征在于，所述扩散抑制剂包括碳。
10.根据权利要求8所述的方法，其特征在于，还包括制备邻近所述栅极的第二隔离壁，以覆盖所述延伸区和所述源极/漏极的小面。
11.根据权利要求10所述的方法，其特征在于，还包括：
在所述栅极延伸区和源极/漏极上制备延伸和环形杂质；以及
在已经制备所述第二隔离壁后，在所述源极/漏极上生长附加源极/漏极材料，并在所述源极/漏极与所述附加源极/漏极材料之间加入扩散抑制剂。
12.根据权利要求11所述的方法，其特征在于，还包括退火所述掺杂剂。
13.一种半导体结构，包括：
具有下部绝缘体层的硅表面；
位于所述硅表面上的栅极；
位于栅极间的源极/漏极，所述源极/漏极在栅极至栅极间距更大的区域内更厚，并且所述源极/漏极包含一种或多种掺杂剂，使得所述掺杂剂接近下部绝缘体层。
14.如权利要求13所述的半导体结构，其特征在于，在栅极和源极/漏极之间还包括栅极延伸区。
15.如权利要求13所述的半导体结构，其特征在于，所述栅极延伸区内含有扩散抑制剂。
16.如权利要求13所述的半导体结构，其特征在于，还包括覆盖栅极延伸区及源极/漏极小面的隔离壁。
17.如权利要求13所述的半导体结构，其特征在于，在所述栅极延伸区和源极/漏极上制备延伸和环形杂质。
18.如权利要求13所述的半导体结构，其特征在于，所述源极/漏极包括上下两层。
19.如权利要求18所述的半导体结构，其特征在于，所述的两层源极/漏极间夹插有一层扩散抑制剂。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/717,971 | 2000-11-21 | ||
| US09/717,971 US6303450B1 (en) | 2000-11-21 | 2000-11-21 | CMOS device structures and method of making same |
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Country Status (2)
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| US6743684B2 (en) * | 2002-10-11 | 2004-06-01 | Texas Instruments Incorporated | Method to produce localized halo for MOS transistor |
| US20040102013A1 (en) * | 2002-11-27 | 2004-05-27 | Jack Hwang | Codoping of source drains using carbon or fluorine ion implants to improve polysilicon depletion |
| JP2004311903A (ja) * | 2003-04-10 | 2004-11-04 | Oki Electric Ind Co Ltd | 半導体装置及び製造方法 |
| JP4008860B2 (ja) * | 2003-07-11 | 2007-11-14 | 株式会社東芝 | 半導体装置の製造方法 |
| US20050048732A1 (en) * | 2003-08-26 | 2005-03-03 | International Business Machines Corporation | Method to produce transistor having reduced gate height |
| US6849527B1 (en) * | 2003-10-14 | 2005-02-01 | Advanced Micro Devices | Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and methods of their formation |
| US7005333B2 (en) * | 2003-12-30 | 2006-02-28 | Infineon Technologies Ag | Transistor with silicon and carbon layer in the channel region |
| US7002224B2 (en) * | 2004-02-03 | 2006-02-21 | Infineon Technologies Ag | Transistor with doped gate dielectric |
| US7015108B2 (en) * | 2004-02-26 | 2006-03-21 | Intel Corporation | Implanting carbon to form P-type drain extensions |
| US7094671B2 (en) * | 2004-03-22 | 2006-08-22 | Infineon Technologies Ag | Transistor with shallow germanium implantation region in channel |
| US6881635B1 (en) | 2004-03-23 | 2005-04-19 | International Business Machines Corporation | Strained silicon NMOS devices with embedded source/drain |
| JP4434832B2 (ja) * | 2004-05-20 | 2010-03-17 | Ｏｋｉセミコンダクタ株式会社 | 半導体装置、及びその製造方法 |
| US7479431B2 (en) * | 2004-12-17 | 2009-01-20 | Intel Corporation | Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain |
| US7605042B2 (en) * | 2005-04-18 | 2009-10-20 | Toshiba America Electronic Components, Inc. | SOI bottom pre-doping merged e-SiGe for poly height reduction |
| US8900980B2 (en) * | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
| US7396717B2 (en) * | 2006-04-03 | 2008-07-08 | United Microelectronics Corp. | Method of forming a MOS transistor |
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| JP4658977B2 (ja) * | 2007-01-31 | 2011-03-23 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| US7875511B2 (en) * | 2007-03-13 | 2011-01-25 | International Business Machines Corporation | CMOS structure including differential channel stressing layer compositions |
| JP5222520B2 (ja) * | 2007-10-11 | 2013-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US8999798B2 (en) * | 2009-12-17 | 2015-04-07 | Applied Materials, Inc. | Methods for forming NMOS EPI layers |
| US8633096B2 (en) * | 2010-11-11 | 2014-01-21 | International Business Machines Corporation | Creating anisotropically diffused junctions in field effect transistor devices |
| CN103178092A (zh) * | 2011-12-26 | 2013-06-26 | 上海华虹Nec电子有限公司 | 超高压ldmos器件的结构及制备方法 |
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