CN118613903A - 用于制造双绝缘体上半导体结构的方法 - Google Patents

用于制造双绝缘体上半导体结构的方法 Download PDF

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Publication number
CN118613903A
CN118613903A CN202380019045.0A CN202380019045A CN118613903A CN 118613903 A CN118613903 A CN 118613903A CN 202380019045 A CN202380019045 A CN 202380019045A CN 118613903 A CN118613903 A CN 118613903A
Authority
CN
China
Prior art keywords
layer
substrate
donor substrate
electrically insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380019045.0A
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English (en)
Chinese (zh)
Inventor
卡里纳·杜雷特
卢多维克·埃卡尔诺
C·波特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN118613903A publication Critical patent/CN118613903A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
CN202380019045.0A 2022-01-31 2023-01-30 用于制造双绝缘体上半导体结构的方法 Pending CN118613903A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2200850A FR3132383A1 (fr) 2022-01-31 2022-01-31 Procédé de fabrication d’une structure de type double semi-conducteur sur isolant
FRFR2200850 2022-01-31
PCT/FR2023/050115 WO2023144495A1 (fr) 2022-01-31 2023-01-30 Procede de fabrication d'une structure de type double semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
CN118613903A true CN118613903A (zh) 2024-09-06

Family

ID=80999171

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380019045.0A Pending CN118613903A (zh) 2022-01-31 2023-01-30 用于制造双绝缘体上半导体结构的方法

Country Status (8)

Country Link
US (1) US20250140600A1 (https=)
EP (1) EP4473559B1 (https=)
JP (1) JP2025504526A (https=)
KR (1) KR20240140161A (https=)
CN (1) CN118613903A (https=)
FR (1) FR3132383A1 (https=)
TW (1) TW202347608A (https=)
WO (1) WO2023144495A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117594522A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种新型绝缘体上硅晶圆及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
FR2952224B1 (fr) * 2009-10-30 2012-04-20 Soitec Silicon On Insulator Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.

Also Published As

Publication number Publication date
JP2025504526A (ja) 2025-02-12
WO2023144495A1 (fr) 2023-08-03
KR20240140161A (ko) 2024-09-24
EP4473559B1 (fr) 2026-03-18
EP4473559A1 (fr) 2024-12-11
TW202347608A (zh) 2023-12-01
FR3132383A1 (fr) 2023-08-04
US20250140600A1 (en) 2025-05-01

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