KR20240140161A - 이중 반도체-온-절연체 구조물을 제조하기 위한 공정 - Google Patents

이중 반도체-온-절연체 구조물을 제조하기 위한 공정 Download PDF

Info

Publication number
KR20240140161A
KR20240140161A KR1020247029259A KR20247029259A KR20240140161A KR 20240140161 A KR20240140161 A KR 20240140161A KR 1020247029259 A KR1020247029259 A KR 1020247029259A KR 20247029259 A KR20247029259 A KR 20247029259A KR 20240140161 A KR20240140161 A KR 20240140161A
Authority
KR
South Korea
Prior art keywords
layer
substrate
donor substrate
electrical insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247029259A
Other languages
English (en)
Korean (ko)
Inventor
카린 뒤레트
루도빅 에카르넛
샬린 포르타
Original Assignee
소이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소이텍 filed Critical 소이텍
Publication of KR20240140161A publication Critical patent/KR20240140161A/ko
Pending legal-status Critical Current

Links

Classifications

    • H01L21/76254
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/0223
    • H01L21/3212
    • H01L21/324
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302Non-deposition formation processes
    • H10P14/6304Formation by oxidation, e.g. oxidation of the substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/403Chemomechanical polishing [CMP] of conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
KR1020247029259A 2022-01-31 2023-01-30 이중 반도체-온-절연체 구조물을 제조하기 위한 공정 Pending KR20240140161A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2200850A FR3132383A1 (fr) 2022-01-31 2022-01-31 Procédé de fabrication d’une structure de type double semi-conducteur sur isolant
FRFR2200850 2022-01-31
PCT/FR2023/050115 WO2023144495A1 (fr) 2022-01-31 2023-01-30 Procede de fabrication d'une structure de type double semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
KR20240140161A true KR20240140161A (ko) 2024-09-24

Family

ID=80999171

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247029259A Pending KR20240140161A (ko) 2022-01-31 2023-01-30 이중 반도체-온-절연체 구조물을 제조하기 위한 공정

Country Status (8)

Country Link
US (1) US20250140600A1 (https=)
EP (1) EP4473559B1 (https=)
JP (1) JP2025504526A (https=)
KR (1) KR20240140161A (https=)
CN (1) CN118613903A (https=)
FR (1) FR3132383A1 (https=)
TW (1) TW202347608A (https=)
WO (1) WO2023144495A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117594522A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种新型绝缘体上硅晶圆及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Soiウエーハの製造方法
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
FR2952224B1 (fr) * 2009-10-30 2012-04-20 Soitec Silicon On Insulator Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante.

Also Published As

Publication number Publication date
JP2025504526A (ja) 2025-02-12
WO2023144495A1 (fr) 2023-08-03
EP4473559B1 (fr) 2026-03-18
CN118613903A (zh) 2024-09-06
EP4473559A1 (fr) 2024-12-11
TW202347608A (zh) 2023-12-01
FR3132383A1 (fr) 2023-08-04
US20250140600A1 (en) 2025-05-01

Similar Documents

Publication Publication Date Title
JP4479010B2 (ja) 半導体基板の熱処理方法
CN100592493C (zh) 智能剥离分开后的热处理
US7833877B2 (en) Method for producing a semiconductor substrate
US7563697B2 (en) Method for producing SOI wafer
JPH1197379A (ja) 半導体基板及び半導体基板の製造方法
CN107615445B (zh) 绝缘体上硅晶圆的制造方法
KR102019653B1 (ko) Soi 웨이퍼의 제조방법 및 soi 웨이퍼
US8367519B2 (en) Method for the preparation of a multi-layered crystalline structure
JP5025957B2 (ja) 欠陥クラスタを有する基板内に形成された薄い層を転写する方法
JP2013516767A5 (https=)
KR20240140161A (ko) 이중 반도체-온-절연체 구조물을 제조하기 위한 공정
WO2006109614A1 (ja) Soiウェーハの製造方法およびこの方法により製造されたsoiウェーハ
US20250140601A1 (en) Process for fabricating a double semiconductor-on-insulator structure
US7485545B2 (en) Method of configuring a process to obtain a thin layer with a low density of holes
WO2017217129A1 (ja) 貼り合わせウェーハの製造方法
KR100842848B1 (ko) 반도체 층의 열처리 방법

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000