CN118335773A - 用于在n掺杂的sic层中制造p掺杂栅格的方法 - Google Patents

用于在n掺杂的sic层中制造p掺杂栅格的方法 Download PDF

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CN118335773A
CN118335773A CN202410318815.8A CN202410318815A CN118335773A CN 118335773 A CN118335773 A CN 118335773A CN 202410318815 A CN202410318815 A CN 202410318815A CN 118335773 A CN118335773 A CN 118335773A
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阿道夫·舍纳
谢尔盖·雷沙诺夫
尼古拉斯-蒂埃里·杰巴里
侯赛因·伊莱希帕纳
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Ascaton
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Abstract

提供了一种用于在SiC半导体材料中制造栅格结构的方法，包括以下步骤：提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一导电类型的第一层(n1)，通过在所述第一层(n1)上外延生长至少一种掺杂半导体SiC材料，来形成与第一导电类型相反的第二导电类型的分离的第二区域(p2)，以及在所述第一层(n1)中注入离子，以形成与第一导电类型相反的第二导电类型的第一区域(p1)，其中，每个所述分离的第二区域(p2)与所述第一区域(p1)中的一个接触。还提供了根据该方法制造的半导体材料中的栅格结构和器件。由此，可以制造具有有效的电压阻断、高电流传导、低总电阻、高浪涌电流能力和快速开关的部件。

Description

用于在N掺杂的SIC层中制造P掺杂栅格的方法
本专利申请是2018年9月14日申请的申请号为201880059862.8(PCT/EP2018/074908)的名称为“用于在N掺杂的SIC层中制造P掺杂栅格的方法”的分案申请。
技术领域
本发明涉及一种通过结合离子注入和外延生长来制造改进型栅格结构的经济有效的方法。栅格可以是掩埋栅格或表面栅格。
背景技术
可以使用嵌入式掺杂结构或掩埋栅格(BG)来限制功率半导体表面的电场，从而使电场敏感区域(例如肖特基接触或MOS结构)免受漂移层中的高电场的影响。这对于基于宽带隙半导体(例如SiC)的器件尤为重要，其中，器件漂移层中的电场可能比硅中的电场高10倍。因此，限制半导体表面处或与像栅极氧化物(SiO2)一样的其他材料的界面处的电场很重要，该材料能够承受比半导体低得多的临界电场。
根据当前的技术水平，可以通过离子注入或外延生长来产生SiC中的嵌入式掺杂结构。对于外延生长，刻蚀栅格或沟槽填充栅格是已知的。
离子注入的BG。优点在于可以通过掩模、氧化物或光致抗蚀剂掩模来产生选择性掺杂的区域。在晶片上的掺杂是可控且均匀的。这是一种众所周知的掺杂技术。缺点是由于注入损伤随着注入剂量的增大而增加，因此掺杂程度受到限制。除了像硼一样的小原子之外，SiC中没有掺杂扩散，这表明注入的pn结位于注入剖面结束处和注入损伤较高处。由于注入能量的限制，厚度存在限制，根据注入的离子，1μm的厚度需要400-1000keV的注入能量。高能量注入是高成本的工艺。由于来自于注入损伤的缺陷中心处的再结合，注入的p栅格具有低的发射极效率，这导致器件的浪涌电流能力有限，这取决于栅格pn二极管保护该器件免受如此高电流水平的影响。
外延BG——刻蚀栅格。生长掺杂的外延层，通过沟道/漂移层的刻蚀和重新生长来限定栅格。优点是深掺杂结构是可能的，栅格厚度不是问题。即使对于高浓度掺杂剂，掺杂也无损伤。高掺杂浓度是可能的，接近于半导体-半金属过渡。缺点是掺杂栅格区域的尖角会导致电场聚集，从而限制器件的电压阻断能力(voltage blocking capability)。
外延BG——沟槽填充栅格。用圆角化转角进行沟槽刻蚀，然后用外延生长进行沟槽填充以及随后的平坦化，然后用外延生长来再生长。优点包括深掺杂结构是可能的。栅格厚度没有问题。即使对于高浓度，无损伤掺杂也是可能的。高掺杂浓度是可能的，接近于半导体-半金属过渡。缺点包括：这是复杂的工艺，其涉及沟槽刻蚀、两次外延再生长以及具有亚微米精度和均匀性的平坦化，这是非常昂贵的工艺。沟槽的再生长需要低的生长速率，因此该工艺耗费很长的时间，这也是个昂贵的工艺。
US 5,705,406公开了一种通过使用离子注入技术来制造具有SiC的半导体层的半导体器件的方法。它教导通过在高温下进行离子注入来减少注入损伤和增加离子注入的剂量。还公开了如何通过离子注入获得更厚的BG。公开了薄层外延生长和离子注入的重复工艺周期。
US 6,897,133公开了一种在碳化硅中生产肖特基二极管的方法。为了避免刻蚀的外延BG的尖角，外延发射极在沟槽刻蚀结构中生长，该结构具有如上所述的外延BG-沟槽填充栅格那样的圆形。这是困难的工艺，其需要先进的刻蚀和平坦化，以去除沟槽外部的掺杂。
US 8,633,560公开了一种半导体器件。通过结合沟槽刻蚀和离子注入来制造沟槽栅格也具有尖角的问题，其中，必须刻蚀圆角化转角。
发明内容
本发明的一个目的是消除现有技术中的至少一些缺点，并且提供一种改进型栅格及其制造方法。
经过广泛研究，已经发现结合碳化硅中的外延生长和离子注入技术可以具有优点。
在第一方面中，提供了一种在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
a)提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一层n1，
b)通过外延生长在第一层n1上形成分离的第二区域p2，所述外延生长添加至少一种掺杂半导体SiC材料，必要时，借助于去除部分添加的半导体材料，在第一层n1上形成分离的第二区域p2，
c)在由紧接着步骤a)之后和紧接着步骤b)之后构成的组中选择的阶段中，进行离子注入至少一次；在第一层n1中注入离子，以形成第一区域p1，其中，整个第二区域p2与第一区域p1接触。
在第二方面中，提供了一种通过如上所述的方法制造的半导体材料中的栅格结构。
在第三方面中，提供了一种使用如上所述的方法制造的器件。然后将栅格集成在该器件中。
随附权利要求限定了其他方面和实施例，其通过引用特别地结合在本文中。
可以制造具有圆角化转角以及具有高掺杂程度的上部的掩埋栅格。离子注入的第一区域p1周围的转角变圆，这避免了电场聚集，并且具有许多优点。此外，器件的离子注入部件是低掺杂的，这产生了低损伤。然而，通过外延生长来制造高掺杂部分，允许达到很高的掺杂程度。
具有高掺杂的第二区域p2允许有效的、低电阻的欧姆接触。
一个优点是由于掺杂栅格中的较低电阻，可以制造具有更快的开关能力的部件。
一个优点是通过避免栅格转角处的电场聚集以及由此有效地使半导体表面屏蔽于高电场，获得非常有效的阻断。这可以用于降低电阻或提高工作温度。
另一个优点是在传导期间获得了载流子从掺杂栅格进入第一层n1的非常有效的发射，这提供了处理非常高的电流水平的能力，并且因此提供了改进和稳定的浪涌电流能力。
又一个优点是与现有技术相比简化了制造，这避免了昂贵的工艺，例如高能量注入、单独的高温退火和亚微米精度的平坦化。
此外，对于整个器件工艺而言，边缘端接(edge termination)可以与注入的p1栅格同时形成，这避免了附加昂贵的制造步骤。
附图说明
参考以下附图描述本发明，图中：
图1示出采用根据本发明的方法制造的栅格结构的示意性剖视图。
图2示出采用根据本发明的方法制造的掩埋栅格结构的另一示意性剖视图。
具体实施方式
在公开和详细描述本发明之前，应当理解，本发明不限于本文公开的特定化合物、配置、方法步骤、衬底和材料，因为这些化合物、配置、方法步骤、衬底和材料可能有所不同。还应当理解，本文所使用的术语仅用于描述特定实施例的目的，而无意于是限制性的，因为本发明的范围仅由随附权利要求及其等同方案来限制。
必须注意，正如在本说明书和随附权利要求书中使用的，单数形式“一”、“一个”和“所述”包括复数对象，除非上下文另外明确指出。
如果没有其他限定，本文使用的任何术语和科学术语旨在具有本发明所属领域的技术人员通常理解的含义。
在整个说明书和权利要求书中使用的“掩埋栅格”表示栅格结构，其中，具有一种导电类型的材料在具有相反导电类型的材料中。
在整个说明书和权利要求书中使用的“导电类型”表示在半导体材料中的传导类型。N型表示电子传导，意味着过剩电子在半导体中移动以产生电流，而p型表示空穴传导，意味着过剩空穴在半导体中移动以产生电流。通过施主掺杂获得n型半导体材料，而通过受主掺杂剂获得p型半导体。在SiC中，氮通常用作施主掺杂剂，而铝用作受主掺杂剂。如果材料是诸如SiC的掺杂半导体，则该材料具有导电类型p或导电类型n。
技术人员认识到，对于大多数包括n型和p型掺杂材料的半导体器件，所有掺杂材料都可以交换导电类型，使得n变成p而p变成n。因此，也包括这样的变型，其中，n是p掺杂的，而p是n掺杂的。
在整个说明书和权利要求书中使用的“掺杂”表示诸如SiC的本征半导体已经添加了杂质，以调节其电特性，并且成为非本征半导体。
在整个说明书和权利要求书中使用的“外延”表示所述材料已经通过外延生长(在这种情况下是SiC的外延生长)制成。
在整个说明书和权利要求书中使用的“衬底”表示一块材料，在该材料上建立功率器件。
第一方面，提供了一种在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
a)提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一层n1，
b)通过外延生长在第一层n1上形成分离的第二区域p2，所述外延生长添加至少一种掺杂半导体SiC材料，必要时，借助于去除部分添加的半导体材料，在第一层n1上形成分离的第二区域p2，
c)在由紧接着步骤a)之后和紧接着步骤b)之后构成的组中选择的阶段中，进行离子注入至少一次；在第一层n1中注入离子，以形成第一区域p1，其中，整个第二区域p2与第一区域p1接触。
在一个实施例中，第一层n1是轻掺杂层。存在包括第一层n1的衬底，而在一个实施例中，衬底包括一个或更多个附加层。附加层的示例包括但不限于与第一层n1相反的掺杂层。
在第二区域p2形成在第一层n1上之前，可以进行离子注入以形成第一区域p1。然而，在第二区域p2形成在第一层n1的顶部上之后，也可以注入离子。然后，离子通过第二区域p2向下注入到在第二区域p2下方的第一层n1中，以形成第一区域p1。
在上述实施例中，得到的是表面栅格。本发明还能够用于制造掩埋栅格。在一个实施例中，该方法还包括在步骤c)之后的一个步骤，该步骤包括在第二区域p2和第一层n1上生长第二层n2的外延生长。这将产生掩埋栅格。
存在多种制造根据本发明的栅格的方法。在一个实施例中，该方法还包括步骤a)之后紧接着的一个步骤，该步骤包括在第一层n1上生长第二层n2的外延生长，然后在某些区域上刻蚀穿透整个第二层n2，其中，该随后的步骤在刻蚀区域的底部形成分离的第二区域p2。这也产生了相同类型的结构，其中，第二区域p2在第一区域p1上。
在一个实施例中，第一层n1和第二层n2是n掺杂的，而第一区域p1和第二区域p2是p掺杂的。
栅格结构由SiC制成。
当在步骤b)中形成的层的部分被去除时，该层在所选区域上被完全去除，从而形成了构成第二区域p2的岛。因此，第二区域p2变得分离。
整个第二区域p2与第一区域p1接触，即整个第二区域p2在下面都具有第一区域p1，但是整个第一区域p1不一定在顶部都具有第二区域p2。在一个实施例中，整个第二区域p2都与第一区域p1对齐。这意味着第一区域p1的一些或全部在顶部具有第二区域p2，并且该第二区域p2在第一区域p1上对齐。对齐意味着第一区域p1从上方看时的顶表面与第二区域p2从下方看时的底表面相匹配。顶部被定义为第二区域p2所在的方向，而底部被定义为第一区域p1所在的方向。
在一个实施例中，一部分第一区域p1在顶部具有第二区域p2。在一些应用中，仅一部分第一区域p1在顶部具有第二区域p2。因此，更多个第一区域p1在顶部没有第二区域p2，由此第二层n2直接在第一区域p1上。
在替代实施例中，整个第一区域p1在顶部具有第二区域p2。
在一个实施例中，第一区域p1和第二区域p2之间的接触面积使得第一区域p1和第二区域p2的面积相匹配，并且具有相等的大小和相等的尺寸。在替代实施例中，第二区域p2的与第一区域p1接触的表面略小于第一区域p1的面积，以保证高掺杂的p2不存在可能产生不期望的高电场的转角。
在一个实施例中，步骤b)中的外延生长添加了厚度在0.1-3.0μm之间的层。该层厚度限定了第二区域p2的厚度。
在一个实施例中，步骤b)中的外延生长使用Al作为掺杂剂。
在一个实施例中，步骤b)中的外延生长添加了掺杂浓度在5e19-3e20cm-3之间的至少一个层。
在一个实施例中，在步骤b)中添加的至少一个层具有掺杂梯度，其中，在距第一区域p1最远处掺杂浓度较高。当在第二区域p2上要直接形成欧姆接触时，第二区域p2的形成梯度是一个优点。
在一个实施例中，通过干法刻蚀执行步骤b)中的去除第二区域p2。
在一个实施例中，仅在步骤b)之前执行离子注入。
在一个实施例中，仅在步骤b)之前执行步骤c)中的离子注入，并且其中，步骤b)中的外延生长与被注入的第一区域p1的退火同时进行。因此，在一个步骤中执行被注入的第一区域p1的外延生长和退火，这简化了生产工艺。
在一个实施例中，用小于350keV的能量执行离子注入。应当记住，高能量注入是一个昂贵的工艺。
在一个实施例中，第一区域p1的厚度在0.2-2.0μm之间。第一区域p1的厚度由离子注入工艺确定。并且，也在较小的程度上由随后的退火确定。
在一个实施例中，第一区域p1的掺杂浓度在1e18-1e19cm-3之间。
在一个实施例中，第一区域p1具有朝向p2的掺杂浓度较高的掺杂梯度。具有朝向n1向下的掺杂程度最低的梯度掺杂的优点在于避免在pn结p1-n1处产生高电场。朝向p2的较高掺杂程度提供了更好的发射极效率。
在一个实施例中，使用B(硼)掺杂第一区域p1，并且其中，离子注入步骤之后是扩散步骤。这将使器件具有较低的泄漏电流。在一个实施例中，与Al相比，使用更高的能量来注入B。
在一个实施例中，使用从包括Al和B的组中选择的至少一个来掺杂第一区域p1。
在一个实施例中，A1被用于掺杂第二区域p2，而B被用于掺杂第一区域p1。
在一个实施例中，如果步骤b)包括第二层n2的外延生长，则进行步骤b)，使得第二层n2的厚度在0.5-3μm之间。
在一个实施例中，在第二层n2的生长之后执行表面平坦化步骤。在一个实施例中，使用CMP(化学机械平坦化)来平坦化。
在一个实施例中，必要时，通过部分去除可选的第二层n2以暴露p2，直接在至少一个第二区域p2的顶部上进行欧姆接触。在要产生欧姆接触的区域p2上方去除部分第二层n2。这将使得可以接近p2，用以直接在p2上产生欧姆接触。在一个实施例中，不必去除一部分第二层n2以暴露p2，由此，在不去除一部分第二层n2的情况下，可以直接在p2上进行欧姆接触。
在一个实施例中，在至少一部分第二层(n2)上形成肖特基接触。对于一些实施例，在使肖特基接触沉积之前可能需要平坦化。
在一个实施例中，p2的厚度与两个第二区域p2之间的间隔之比小于1。对于任何两个第二区域p2之间的所有间隔，p2的厚度与两个第二区域p2之间的间隔之比小于1。假设在步骤c)期间不从第二区域p2的顶部去除材料，则将p2的厚度定义为在步骤b)中生长的层的厚度。该间隔是在n1-n2界面处测量的两个第二区域p2之间的距离。两个相邻的第二区域p2之间的间隔是从一个第二区域p2的一侧到另一个第二区域p2的最近侧的距离。在许多实施例中，第二区域p2的图案是规则的，沿着所有方向具有相等的间隔，从而使得容易计算厚度间隔比。对于不规则的图案，可以对每个间隔计算比率，然后每个比率都应当小于1。
在一个实施例中，在制造步骤c)中集成了包括栅格结构的器件的边缘端接，以同时形成边缘端接和第一区域p1。
在第二方面中，提供了用如上所述的方法来制造的半导体材料中的栅格结构。设想存在多个第一区域p1和第二区域p2，在它们之间具有间隔，形成栅格结构。在各个实施例中，第一区域p1以及可选地与顶部的第二区域p2形成图案。一个示例是从上方看的六边形图案。还包括其他形状。
在第三方面中，提供了使用如上所述的方法制造的器件。然后将栅格集成到该器件中。可以使用根据该方法制造的栅格制成的器件的一个示例是MOSFET。可以使用根据该方法制造的栅格制成的器件的其他示例包括但不限于肖特基二极管、JFET(结型场效应晶体管)、BJT(双极结型晶体管)和IGBT(绝缘栅极双极晶体管)。
栅格是要制造的器件中的特征，其具有规则地间隔开的相反掺杂区域。通过要使用栅格的部件或器件及其电压、电流、开关频率等确定精准的设计。

Claims (24)

1.一种用于在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一导电类型的第一层(n1)，
通过在所述第一层(n1)上外延生长至少一种掺杂半导体SiC材料，来形成与第一导电类型相反的第二导电类型的分离的第二区域(p2)，以及
在所述第一层(n1)中注入离子，以形成与第一导电类型相反的第二导电类型的第一区域(p1)，其中，每个所述分离的第二区域(p2)与所述第一区域(p1)中的一个接触。
2.根据权利要求1所述的方法，其中，注入离子的步骤在形成所述分离的第二区域(p2)之前执行。
3.根据权利要求1所述的方法，其中，通过经由所述分离的第二区域(p2)将离子注入所述第一层(n1)中，注入离子的步骤在形成所述分离的第二区域(p2)之后执行。
4.一种半导体材料中的栅格结构，其通过根据权利要求1所述的方法制造。
5.一种使用根据权利要求1所述的方法制造的器件。
6.一种用于在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一导电类型的第一层(n1)，
通过在所述第一层(n1)上外延生长至少一种掺杂半导体SiC材料，来形成与第一导电类型相反的第二导电类型的分离的第二区域(p2)，
在所述第一层(n1)中注入离子，以形成与第一导电类型相反的第二导电类型的第一区域(p1)，其中，每个所述分离的第二区域(p2)与所述第一区域(p1)中的一个接触；以及
在所述分离的第二区域(p2)和所述第一层(n1)上外延生长第二层(n2)。
7.根据权利要求6所述的方法，其中，所述第二层(n2)的厚度在0.5μm-3.0μm之间。
8.根据权利要求6所述的方法，进一步包括：
对所述第二层(n2)的表面进行平坦化。
9.根据权利要求6所述的方法，进一步包括：
在所述第二层(n2)的至少一部分上形成肖特基接触。
10.根据权利要求6所述的方法，其中在形成所述分离的第二区域(p2)之前执行离子注入。
11.根据权利要求1所述的方法，其中在形成所述分离的第二区域(p2)之后执行离子注入，并且离子注入包括：经由所述分离的第二区域(p2)将离子注入所述第一层(n1)中。
12.一种半导体材料中的栅格结构，其通过根据权利要求6所述的方法制造。
13.一种使用根据权利要求6所述的方法制造的器件。
14.一种用于在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一导电类型的第一层(n1)，
在所述第一层(n1)上外延生长第二层(n2)，
在特定区域上刻蚀穿透整个第二层(n2)，
在所述第一层上于所述特定区域处外延生长至少一种掺杂半导体SiC材料，以形成与第一导电类型相反的第二导电类型的分离的第二区域(p2)，以及
在所述第一层(n1)中注入离子，以形成与第一导电类型相反的第二导电类型的第一区域(p1)，其中，每个所述分离的第二区域(p2)与所述第一区域(p1)中的一个接触。
15.根据权利要求14所述的方法，其中，注入离子的步骤在形成所述分离的第二区域(p2)之前执行。
16.根据权利要求14所述的方法，其中在形成所述分离的第二区域(p2)之后执行离子注入，并且离子注入包括：经由所述分离的第二区域(p2)将离子注入所述第一层(n1)中。
17.一种半导体材料中的栅格结构，其通过根据权利要求14所述的方法制造。
18.一种使用根据权利要求14所述的方法制造的器件。
19.一种用于在SiC半导体材料中制造栅格结构的方法，所述方法包括以下步骤：
提供包括掺杂半导体SiC材料的衬底，所述衬底包括第一导电类型的第一层(n1)，
在所述第一层(n1)上外延生长至少一种掺杂半导体SiC材料，以形成与第一导电类型相反的第二导电类型的分离的第二区域(p2)，
在所述第一层(n1)中注入离子，以形成与第一导电类型相反的第二导电类型的第一区域(p1)，其中，每个所述分离的第二区域(p2)与所述第一区域(p1)中的一个接触，以及
直接在至少一个所述分离的第二区域(p2)的顶部上进行欧姆接触。
20.根据权利要求19所述的方法，进一步包括：
在所述分离的第二区域(p2)和所述第一层(n1)上外延生长第二层(n2)，
其中，直接在至少一个所述分离的第二区域(p2)的顶部上进行欧姆接触包括：部分去除第二层(n2)以暴露所述分离的第二区域(p2)中的至少一个。
21.根据权利要求19所述的方法，其中，注入离子的步骤在形成所述分离的第二区域(p2)之前执行。
22.根据权利要求19所述的方法，其中，在形成所述分离的第二区域(p2)之后执行离子注入，并且离子注入包括：经由所述分离的第二区域(p2)将离子注入所述第一层(n1)中。
23.一种半导体材料中的栅格结构，其通过根据权利要求19所述的方法制造。
24.一种使用根据权利要求19所述的方法制造的器件。
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