CN117461123A - 通过pvd法控制低电阻材料的电阻率和结晶度的方法 - Google Patents
通过pvd法控制低电阻材料的电阻率和结晶度的方法 Download PDFInfo
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- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 8
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- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 6
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Abstract
本发明涉及一种低电阻材料的成膜方法,其涉及利用物理气相沉积(Physical Vapor Deposition,PVD)在半导体基板上成膜的低电阻材料的成膜方法,包括以下阶段:a)在1Pa至40Pa的压力以及低温下,利用磁控溅射在SiO2晶圆上层压阻挡层;b)在层压所述阻挡层后,不施加DC电源,而是在Ar气体氛围下施加RF偏压(RF bias)来最阻挡层的表面进行改性;以及c)利用磁控溅射在阻挡层上展压低电阻材料,所述低电阻材料是从由钨(W)、钌(Ru)、钼(Mo)、钴(Co)及铑(Rh)组成的群组中选择的一种以上。
Description
技术领域
本发明涉及利用物理气相沉积(Physical Vapor Deposition,PVD)控制半导体基板膜的电阻率及结晶度的方法,具体地,包括利用PVD在SiO2晶圆上层压由氮化钛(TiN)、氮化钽(TaN)或氮化硅(SiNx;x>0)组成的阻挡层,然后在进行After Bias处理后层压W、Ru、Co、Rh或Mo的阶段的半导体基板膜的电阻率及结晶度的控制方法或低电阻材料(W、Ru、Mo、Co、Rh等)的成膜方法。
背景技术
随着半导体元件的不断微细化,在新一代布线结构中考虑使用钨(W)、钼(Mo)、钴(Co)、铑(Rh)、钌(Ru)等低电阻率材料,其中,Ru作为Cu的替代材料,是一种正在得到积极开发研究的材料。Ru作为粘合(Adhesion)层及阻挡层(Barrier layer)与TiN(TaN、SiNx)层压在一起使用,当在下方层(TiN)上层压Ru时,由于TiN的定位(Orientation)会导致出现孔隙(void)并降低结晶度的问题。
为解决这一问题,本发明通过PVD低温(100℃以下)高压过程(Process)在下方层TiN上沉积无定型(Amorphous like)膜,经过连续的After Bias处理来改善TiN的粗糙度(Roughness)。在通过上述过程制备的TiN层上层压Ru时,确认到具有改善孔隙(void)并降低电阻率的效果。
在先技术文献
专利文献
(专利文献1)(1)韩国公开专利公报第10-2019-0051082号(2019.05.14.)
发明内容
发明要解决的问题
为改善TiN的膜密度、电阻等膜质会使用化学气相沉积(Chemical VaporDeposition,CVD)及原子层沉积(Atomic Layer Deposition,ALD)工艺,在物理气相沉积(Physical Vapor Deposition,PVD)工艺中,通过施加RF偏压(RF Bias)以及高温成膜的过程来沉积TiN。然而本发明的目的在于通过PVD法有意使TiN层具有无定形(电阻率高)膜质,并通过无定型TiN膜增加Ru的晶粒尺寸(Grain size),由此来提高结晶度。
并且,本发明的目的在于,在对Ru成膜之前,向无定型膜的TiN施加After Bias(Treatment,Bombardment)处理,由此改善TiN的粗糙度,抑制Ru生成孔隙,提高结晶度,不仅如此,通过在TiN层上形成Ru膜,获得电阻率低的Ru膜。
然而,本发明要解决的技术问题并不受限于上述言及课题,未言及的其他课题将通过下面的记载由本领域普通技术人员明确理解。
解决问题的技术手段
根据本发明的一实施例,涉及一种利用物理气相沉积(Physical VaporDeposition,PVD)在半导体基板上成膜的低电阻材料的成膜方法,包括以下阶段:
a)在1Pa至40Pa的压力以及低温(100℃以下)下,利用磁控溅射在SiO2晶圆上层压阻挡层;
b)在层压所述阻挡层后,不施加DC电源,而是在Ar气体氛围施加RF偏压(RF bias)来对阻挡层的表面进行改性;以及
c)利用磁控溅射在阻挡层上层压低电阻材料,
所述低电阻材料是从由钨(W)、钌(Ru)、钼(Mo)、钴(Co)及铑(Rh)组成的群组中选择的一种以上。
所述阻挡层可以是从由氮化钛(TiN)、氮化钽(TaN)及氮化硅(SiNx;x>0)组成的群组中选择的一种以上。
所述阶段c)可以包括形成低电阻材料的成核层(种子层)的阶段;以及形成所述低电阻材料的结晶层的阶段。
发明的效果
根据本发明的一实施例,半导体基板膜的Ru、W、Mo、Co、Rh等低电阻材料的成膜方法,利用PVD法使TiN层形成无定形膜质,由此,具有增加Ru等的晶粒尺寸并改善结晶度的效果。并且,对所述TiN层进行After Bias处理,可以改善TiN层的粗糙度,通过适当调节RF偏压与时间来改善TiN层的粗糙度,可以最好地抑制孔隙生成并提高结晶度,由此最终对电阻率及结晶度进行控制。
并且,通过两个阶段(2steps)在TiN层上层压Ru层,由此,与第2阶段(2nd step)的层压条件无关地,对第1阶段(1st step)的成核(Nucleation)进行控制,可以在增大晶粒尺寸的同时降低电阻率。
进一步地,通过调节TiN的成膜条件(DC电压、RF电压、Ar、N2流量、压力等),最佳地调节After Bias效果,由此,最终可以提供孔隙得到改善,电阻率降低的半导体基板膜,可以不利用ALD、CVD等,而是通过PVD来控制半导体基板膜的电阻率及结晶度。
应当理解,本发明的效果并不受限于此,还包括可以通过本发明的具体实施或权利要求中记载的结构推导出的全部效果。
附图说明
图1是显示根据本发明一实施例的TiN及Ru层压工艺过程的附图。
图2是显示形成TiN膜的工艺的附图。
图3是显示After Bias及Ru成膜工艺的附图。
图4a是显示在层压TiN(4nm)后,不经过额外处理直接层压Ru(30nm)时,TiN表面不稳定,TiN结晶及Ru的结晶度随TiN表面粗糙度而随机变化,以及晶粒尺寸减小,电阻率上升的结果的附图。
图4b是显示在高压(1~40Pa)及低温(100℃以下)下形成TiN(4nm)膜,经过AfterBias处理后层压Ru(30nm)时,粗糙度及电阻率得到改善的结果的附图。
图5是显示在不同条件(RF电源,时间)下经过After Bias处理后,以相同条件的两个阶段(2steps)沉积Ru后的Ru层的电阻率变化的测量结果的附图。
图6是对结果进行比较的附图,比较的分别是按照不同DC电源(0.5kW,2kW,4kW)对Ru层进行单一阶段(1step)沉积时的晶粒尺寸及电阻率变化结果,以及利用0.5kW DC电源沉积Ru层的第一层(1st layer),然后利用2kW DC电源沉积第二层(2nd layer)时的晶粒尺寸及电阻率的结果。
图7a是在SiO2上通过单一阶段(1step)沉积Ru层(30nm)后测量晶粒尺寸及电阻率(10.79μΩcm)的结果的附图。
图7b是在SiO2上通过两个阶段(2steps)沉积Ru层(26nm/4nm)后测量晶粒尺寸及电阻率(10.50μΩcm)的结果的附图。
图7c是在SiO2上层压TiN(4nm)后,不经过After Bias处理在TiN(4nm)上通过单一阶段(1step)沉积Ru层后,测量晶粒尺寸、晶粒数量级电阻率(12.77μΩcm)的结果的附图。
图7d是在SiO2上层压TiN(4nm)后,经过After Bias处理后在TiN(4nm)上通过单一阶段(1step)沉积Ru层,然后测量晶粒尺寸、晶粒数量及电阻率(11.67μΩcm)的结果的附图。
图7e是在SiO2上层压TiN(4nm)后,不经过After Bias处理在TiN(4nm)上通过两个阶段(2steps)沉积Ru层后,测量晶粒尺寸、晶粒数量及电阻率(12.15μΩcm)的结果的附图。
图7f是在SiO2上层压TiN(4nm)后,经过After Bias处理后在TiN(4nm)上通过两个阶段(2steps)沉积Ru层,然后测量晶粒尺寸、晶粒数量及电阻率(11.08μΩcm)的结果的附图。
具体实施方式
下面将参照附图对实施例进行详细说明。应当理解,可以对实施例进行多种改变,本申请的权利范围并不受限于下面的实施例。对实施例进行的所有改变、及其等同物乃至其替代物均属于本发明的权利范围。
实施利中使用的术语并非用于限制本发明而仅为说明目的。在内容中没有特别说明的情况下,单数表达包括复数含义。在本说明书中,“包括”或者“具有”等术语用于表达存在说明书中所记载的特征、数字、步骤、操作、构成要素、配件或其组合,并不排除存在或者额外附加一个或以上其他特征、数字、步骤、操作、构成要素、配件或其组合的可能性。
在没有其他定义的情况下,包括技术或者科学术语在内的本文使用的全部术语都具有本领域普通技术人员所理解的通常含义。通常使用的如词典定义的术语,应理解为相关技术内容中的含义,在本说明书中没有明确定义的情况下,不能解释为理想化或过于形式化的含义。
并且,在参照附图进行说明的过程中,相同的构成要素使用相同的附图标记,并省略重复说明。在说明实施例的过程中,当判断对于相关公知技术的具体说明会不必要地混淆实施例时,省略其详细说明。
根据本发明的一实施例,提供一种利用物理气相沉积(Physical VaporDeposition,PVD)在半导体基板上成膜的低电阻材料的成膜方法,包括以下阶段:
a)在1Pa至40Pa的压力以及低温(100℃以下)下,利用磁控溅射在SiO2晶圆上层压阻挡层;
b)在层压所述阻挡层后,不施加DC电源,而是在Ar气体氛围下施加RF偏压(RFbias)来对阻挡层的表面进行改性;以及
c)利用磁控溅射在阻挡层层上压低电阻材料,
所述低电阻材料是从由钨(W)、钌(Ru)、钼(Mo)、钴(Co)及铑(Rh)组成的群组中选择的一种以上。
通过所述阶段a)形成的阻挡层不仅可以是由氮化钛(TiN)构成,还可以是由氮化钽(TaN)或氮化硅(SiNx;x>0)构成,阻挡层的厚度优选为4nm以下。
一方面,当超过4nm时,在对Ru/TiN成膜时,会因Ru等低电阻材料的电阻率的升高出现信号延迟及电压下降的问题,还会降低设备性能。
所述阶段a)中通过磁控溅射对TiN等进行层压的层压条件可以有多种,可以在高压及低温(100℃以下)下利用磁控溅射,特别是现有的PVD过程通常在0.1Pa至0.9Pa的压力下实施,然而本发明具有在1Pa至40Pa的高压下实施的特点。
并且,After bias的效果会根据TiN等的成膜条件有所不同,考虑到在最佳的成膜条件下实现无定形化的TiN等会产生最佳结果(低电阻率),TiN的最优成膜条件是:DC电源:10kW~30kW、RF电源:200W以下、Ar/N2的比率为1/10以下、压力:1Pa~40Pa及低温(100℃以下)。
一方面,为了进行粘合(Adhesion)与阻挡(Barrier),除了在SiO2晶圆层压TiN等下部膜之外,还会在上面层压Ru等低电阻材料,此时,会因Ru/TiN结构导致电阻率上升的问题。
为了解决这一问题,根据本发明的一实施例,在完成阶段a)的层压阻挡层之后,在层压低电阻材料之前,会在Ar气体氛围下施加RF偏压(RF bias)来实施After Bias,由此对TiN表面进行改性。
通过阶段b)的After Bias,可以降低最终成膜有低电阻材料的半导体基板的电阻率,这是因为相比未实施After Bias的情况,改善了不稳定的TiN层的表面粗糙度,去除了键合内杂质(氧等),由此增大了成膜的低电阻材料(Ru、Mo、W、Co、Rh等)的晶粒尺寸,减小孔隙,最终产生了改善电阻率的效果。
一方面,如图5所示,通过调节所述阶段b)的RF电源及时间,可以最终调节电阻率,在50W至300W及10秒至100秒期间,优选在100W至300W及10秒至100秒期间,更优选在100W至300W及10秒至60秒期间,特别优选在300W及10秒至50秒期间施加RF偏压时,相比现有水平,可以显着降低电阻率,增加晶粒尺寸并减少孔隙。
根据本发明的一实施例,在实施所述阶段b)的After Bias之后,利用磁控溅射层压Ru、W、Mo、Co、Rh等低电阻材料,实施层压直到层压所需厚度(阶段c)。
此时,通过所述阶段c)层压的低电阻材料的层压厚度可以是10nm至30nm,当沉积所需厚度时,从腔室去除晶圆来完成低电阻材料成膜工艺。
一方面,如前所述,所述阶段c)可以通过单一阶段(1step)进行沉积,也可以分为形成作为种子层的成核层的第1阶段(1st step)与形成结晶层的第2阶段(2nd step),通过两个阶段(2steps)形成为双层。
此时,如图7所示,相比通过单一阶段沉积的情况(c)及(d),形成为双层低电阻材料(Ru等)的情况(e)及(f)的晶粒尺寸更大,晶粒数更少,电阻率更低,相比通过单一阶段形成低电阻材料,更优选通过两个阶段形成为双层。在这里,晶粒数量是直接对各个SEM图像中相同大小的部份(区域)的晶粒数量进行计数来得出。
一方面,可以通过改变第1阶段的实施条件来控制成核(Nucleation),由此可以与第2阶段的沉积条件无关地降低电阻率,并且,即使在形成结晶层的阶段施加高于成核层形成阶段的DC电源,相比在单一阶段中使用与形成成核层阶段相同的DC电源,仍可获得相同程度的电阻率,这具有缩短成膜时间并改善分布的优点。
作为一实施例,例如,通过单一阶段(1step)分别使用0.5kW、2kW及4kW的DC电源来层压Ru层的情况,可以确认到随着DC电源的增加,晶粒尺寸变小,电阻率变大(图6),可以确认到通过单一阶段使用0.5kW的DC电源时的晶粒尺寸,与在第1阶段使用0.5kW,在第2阶段使用2kW时的晶粒尺寸几乎相同(图6)。
一方面,在对低电阻材料进行成膜时,当通过单一阶段(1step)进行沉积时,低电阻材料的成膜条件可以是:2kW至8kW的DC电源、50W的RF电源。当所述DC电源低于2kW时,由于延长成膜时间,不仅对量产产生负面影响,还会导致成膜分布变差;当超过8kW时,所形成的晶粒尺寸过小,会增大电阻率。
并且,当分为形成作为种子层的成核层的第1阶段(1st step)与形成结晶层的第2阶段(2nd step),通过两个阶段(2steps)来形成双层低电阻材料膜时,在第1阶段成膜时,DC电源可以是0.3kW至1kW,此时不施加RF电源。当DC电源小于0.3kW时,会难以放电;当超过1kW时会出现增大电阻率的问题。由此,在第2阶段成膜时,当DC电源低于2kW,由于延长成膜时间,不仅对量产产生负面影响,还会导致成膜分布变差;当超过10kW时,所形成的晶粒尺寸过小,因此优选为2kW至10kW,此时RF电源可以是50W。
并且,所述成核层(种子层)的厚度不到4nm时,难以成核(Nucleation),因此优选为4nm以上,优选地,成核层及结晶层的厚度之和优选为10nm至30nm。一方面,利用低电源成膜的成核层越厚,形成的晶粒尺寸越大,这可以直接改善电阻率,因此,成核层的厚度不存在上限,但考虑到量产,成核层越厚成膜工艺所需时间更长,因此适当的成核层厚度是4nm。
利用上述方法制备成膜有TiN等阻挡层与Ru、W、Mo、Co、Rh等低电阻材料的半导体基板,随着半导体元件的微细化可用于新一代布线结构,特别适用于不足28nm的节距(pitch)的微细图案。
下面通过实施例更详细地说明本发明。下面的实施例仅用于对本发明进行示例,本发明的范围并非受限于此。
<实施例>
1)TiN的层压方法
使用名称为ENTRON-EX的实验设备,基于物理气相沉积(PVD)系统进行成膜。TiN与Ru成膜是在不同的工艺腔室实现,基板是使用SiO2基板。
基板是经过负载锁定(Load lock)腔室被传递至TiN腔室,固定基板,向ESC施加电源实现适合成膜的基板温度,向腔室内供应Ar/N2气体。为了对腔室进行放电,向目标部位施加DC,在基板台(stage)部施加RF,使沉积物质从目标部位朝向基板实现成膜。在这里,RF将离子拉向基板台方向,起到控制膜质及分布的作用,TiN的成膜条件如下:
DC:10kW~30kW;
RF:200W以下;
Ar/N2比率:1/10以下;
压力:1Pa~40Pa(高压);
温度:低温(100℃以下)
2)After bias处理方法
为实施After bias处理,完成TiN沉积后,将基板移动至Ru腔室。向腔室内供应Ar气体,向基板台施加RF偏压,将Ar离子拉向基板进行处理,After bias条件如下:
DC:0kW;
Ar:170sccm;
RF:300W;
时间及温度:10秒,200℃以上的高温。
3)低电阻材料(Ru)的沉积方法
-单一阶段(1step)成膜方法
经过After bias处理后,为在经过After bias处理的TiN膜上沉积Ru膜,在相同的Ru腔室内以2kW的DC电源,50W的RF电源,170sccm的Ar流量,470℃,65秒的成膜条件对Ru进行成膜,其结果,获得30nm厚度的单一层的Ru膜。
-两个阶段(2steps)成膜方法
与所述单一成膜阶段类似地,经过After bias处理后,在相同的Ru腔室内,在经过After bias处理的TiN膜上沉积30nm的Ru膜。此时,Ru成膜是通过顺序采用低电源条件的第1阶段以及高电源条件的第2阶段实现沉积,相应阶段的实施条件与成膜厚度如下:
第1阶段:DC 0.5kW,RF 0W,Ar 170sccm,76sec,470℃,4nm(成膜厚度)
第2阶段:DC 2kW,RF 50W,Ar 170sccm,56sec,470℃,26nm(成膜厚度)。
一方面,晶粒尺寸越大电阻率越得到改善,在利用低电源时晶粒尺寸会更大。然而考虑到量产,由于时间成本也十分重要,需要利用高电源成膜来缩短时间,因此通过上述两个阶段(2steps)进行成膜。
即,因为受到Ru成膜的第1阶段的晶粒尺寸的影响,在第2阶段即使采用高电源也会具有大的晶粒尺寸,由此,具有部份改善电阻率及量产性的效果。
在Ru成膜后,晶圆经过传送腔室(Transfer Chamber)回到前开式晶圆传送盒(Foup),则本实验结束。
综上,通过有限的附图对实施例进行了说明,本领域普通技术人员能够基于所述记载进行多种更改与变形。例如,所说明的技术按照与说明的方法不同的顺序执行,和/或所说明的构成要素按照与说明的方法不同的形态进行结合或组合,或者由其他构成要素或者等同物置换或代替,也能得到适当的结果。
因此,其他体现、其他实施例及权利要求的等同物均属于所附权利要求书的范围。
Claims (14)
1.一种低电阻材料的成膜方法,
涉及一种利用物理气相沉积(PhysicalVapor Deposition,PVD)在半导体基板上成膜的低电阻材料的成膜方法,包括以下阶段:
a)在1Pa至40Pa的压力以及低温下,利用磁控溅射在SiO2晶圆上层压阻挡层;
b)在层压所述阻挡层后,不施加DC电源,而是在Ar气体氛围下施加RF偏压(RF bias)来对阻挡层的表面进行改性;以及
c)利用磁控溅射在阻挡层上层压低电阻材料,
所述低电阻材料是从由钨(W)、钌(Ru)、钼(Mo)、钴(Co)及铑(Rh)组成的群组中选择的一种以上。
2.根据权利要求1所述的低电阻材料的成膜方法,
所述阻挡层是从由氮化钛(TiN)、氮化钽(TaN)及氮化硅(SiNx;x>0)组成的群组中选择的一种以上。
3.根据权利要求1所述的低电阻材料的成膜方法,
所述阻挡层的厚度是4nm以下。
4.根据权利要求1所述的低电阻材料的成膜方法,
所述阻挡层是TiN层,
所述阶段a)的磁控溅射的实施条件是10kW至30kW的DC、200W以下的RF、1/10以下的Ar/N2比率以及1Pa至40Pa的压力。
5.根据权利要求1所述的低电阻材料的成膜方法,
所述阶段b)是在100W至300W及10秒至60秒期间施加RF偏压。
6.根据权利要求1所述的低电阻材料的成膜方法,
所述阶段b)是在300W及10秒期间施加RF偏压。
7.根据权利要求1所述的低电阻材料的成膜方法,
所述阶段c)的层压厚度是10nm至30nm。
8.根据权利要求1所述的低电阻材料的成膜方法,
所述阶段c)包括形成低电阻材料的成核层(种子层)的阶段;以及形成所述低电阻材料的结晶层的阶段。
9.根据权利要求8所述的低电阻材料的成膜方法,
所述成核层(种子层)的厚度是4nm以上。
10.根据权利要求8所述的低电阻材料的成膜方法,
相比形成成核层的阶段,形成所述结晶层的阶段施加更高的DC电源。
11.根据权利要求8所述的低电阻材料的成膜方法,
形成所述成核层的阶段的RF是0W。
12.根据权利要求9所述的低电阻材料的成膜方法,
所述成核层(种子层)与结晶层的厚度之和为10nm至30nm。
13.根据权利要求1或8所述的低电阻材料的成膜方法,
所述低电阻材料是钌(Ru)。
14.根据权利要求1所述的低电阻材料的成膜方法,
成膜有所述阻挡层与低电阻材料的半导体基板用于具有不到28nm的节距(pitch)的微细图案。
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- 2022-06-08 WO PCT/KR2022/008042 patent/WO2023277370A1/ko active Application Filing
- 2022-06-08 CN CN202280041318.7A patent/CN117461123A/zh active Pending
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