CN117198869A - 使用pvd钌的方法与装置 - Google Patents

使用pvd钌的方法与装置 Download PDF

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CN117198869A
CN117198869A CN202311032383.6A CN202311032383A CN117198869A CN 117198869 A CN117198869 A CN 117198869A CN 202311032383 A CN202311032383 A CN 202311032383A CN 117198869 A CN117198869 A CN 117198869A
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layer
ruthenium
temperature
forming
substrate
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乔斯林甘·罗摩林甘
罗斯·马歇尔
雷建新
唐先民
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Applied Materials Inc
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Applied Materials Inc
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Abstract

描述了含钌的栅极层叠和形成含钌栅极层叠的方法。含有钌的栅极层叠包含：多晶硅层，在基板上；硅化物层，在多晶硅层上；阻挡层，在硅化物层上；钌层，在阻挡层上；及间隔层，包含在钌层的侧面上的氮化物，其中钌层在形成间隔层之后基本上不包含氮化钌。形成钌层包含以下步骤：在氪环境中在包含高电阻率陶瓷材料的高电流静电卡盘上溅射钌。溅射的钌层在大于或等于约500℃的温度下退火。

Description

使用PVD钌的方法与装置
本发明申请是申请号为201780061629.9，申请日为2017年10月2日，名称为“使用PVD钌的方法与装置”的发明专利申请的分案申请。
技术领域
本公开一般涉及结合物理气相沉积(PVD)钌的方法和电子装置。特定地，本公开涉及其中以PVD Ru层替代PVD钨，以提供较低电阻率膜的方法和电子装置。
背景技术
半导体集成电路的持续小型化已迫使许多传统结构发生变化，且已需要随之而来的需求，以改进用以创建新结构的工艺。用于较大特征尺寸的传统MOS(金属氧化物半导体)晶体管栅极结构包括沉积的氮化钨阻挡层和钨通孔层。溅射是沉积WN阻挡层和W通孔层的通常优选方法。然而，随着膜厚度的降低，钨电阻率增加，导致在位线应用中未来节点DRAM的有用性降低。
因此，本领域存在有用于膜和用以沉积具有较低的位线电阻率和对氧化不敏感的膜的方法的需求。
发明内容
本公开的一个或多个实施方式涉及形成栅极层叠的方法。提供了一种等离子体溅射腔室，包括靶和基座，靶包含钌，基座用于支撑与靶相对而溅射沉积的基板。基座包含大于或等于约350℃的温度的高电流静电卡盘。氪流到腔室中并激发成等离子体，以在基板上沉积钌层。提供退火腔室，且在大于或等于约500℃的温度下对基板上的钌层进行退火。
本公开的另外的实施方式涉与栅极层叠，包含：多晶硅层，在基板上；硅化物层，在多晶硅层上；阻挡层，在硅化物层上；钌层，在阻挡层上；及间隔层，包含在钌层的侧面上的氮化物。钌层在形成间隔层之后基本上不包含氮化钌。
本公开的进一步的实施方式涉及形成栅极层叠的方法。在基板上形成多晶硅层。在多晶硅层上形成硅化物层。硅化物层包含具有约的厚度的硅化钛。在硅化物层上形成阻挡层。阻挡层包含TiN、TaN、WN或TiSiN的一种或多种。在阻挡层上形成任选的界面层。PVD Ru层沉积在阻挡层或任选的界面层上。PVD Ru层在氪环境中，以大于或等于约350℃的温度，在包含高电阻率陶瓷的高电流静电卡盘上沉积在基板上。PVD Ru层具有约/>到约的范围中的厚度。PVD Ru层在大于或等于约500℃的温度下进行退火。在退火的PVDRu层的侧面上形成间隔层。间隔层包含SiN并基本上不形成氮化钌。
附图简要说明
因此，可详细了解本发明的上述特征的方式，简短摘要于上的本发明的更具体的描述可通过参考实施方式而获得，其中一些实施方式显示在附图中。然而，应当注意附图仅显示了本发明的典型实施方式，且因此不应被视为限制本发明的范围，因为本发明可承认其他同等有效的实施方式。
图1根据本公开的一个或多个实施方式的气体层叠；
图2显示了根据本公开的一个或多个实施方式的物理气相沉积腔室的示意性横截面图；
图3显示了作为膜厚度的函数的钌和钨膜的金属电阻率的曲线图；及
图4显示了作为静电卡盘温度的函数的钌膜的电阻率的曲线图。
具体描述
在描述本发明的几个示例性实施方式之前，应当理解本发明不限于以下的描述中所阐述的构造或工艺步骤的细节。本发明能够具有其他实施方式并且能够以各种方式实践或执行。
本文所用的“基板”是指在制造过程中在上面进行膜处理的任何基板或形成在基板上的材料表面。例如，可进行处理的基板表面包括诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石的材料，及诸如金属、金属氮化物、金属合金和其它导电材料的任何其它材料，这取决于应用。基板包括(但不限于)半导体晶片。基板可暴露于预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火及/或烘烤基板表面。除了直接在基板本身的表面上进行膜处理之外，在本发明中，所公开的膜处理步骤的任何一个也可在如下面更详细公开的基板上形成的下层上进行，术语“基板表面”意欲包括上下文所指示的此类下层。因此，例如，当将膜/层或部分膜/层沉积在基板表面上时，新沉积的膜/层的暴露表面成为基板表面。
如在本说明书和所附随的权利要求书中所使用的，术语“前驱物”、“反应物”、“反应性气体”及类似术语可互换使用，以指能够与基板表面反应的任何气体物质。
在本公开的一个或多个实施方式中，较低电阻率的Ru膜用高温偏压静电卡盘(ESC)沉积。一些实施方式在约190℃至约550℃的温度范围中使用Kr溅射Ru工艺。在一些实施方式中可使用两步骤工艺来改善Ru电阻率以及膜表面形态。随着工艺温度在约190℃至约550℃的范围中升高，Ru电阻随着ESC温度的升高而降低，并在约680℃至约900℃的范围中的温度退火。通过组合高温Ru工艺和较高温度退火工艺，与W膜相比可形成较低电阻率的Ru膜。
参考图1，本公开的一个或多个实施方式涉及金属氧化物半导体晶体管栅极层叠40。晶体管栅极层叠40包括形成为较低掺杂的硅层基板14的高掺杂源极/漏极(S/D)区域10、12，源极/漏极(S/D)区域10、12可在硅晶片上外延地形成或甚至在绝缘体上硅(SOI))结构中形成。可能在S/D区域10、12的注入和退火步骤之前，可在整个MOS区域之上方形成薄的栅极氧化物层16。栅极层叠40形成在栅极氧化物层16的上方。各种实施方式的栅极层叠40包含多晶硅层20、硅化物层42、阻挡层44和钌层46。氧化物-氮化物-氧化物(ONO)结构可夹在多晶硅层20内。
源极/漏极孔26可光刻地蚀刻到S/D区域10、12的上方的栅极氧化物层16，以限定栅极层叠40。可由氧化硅制成的间隔物28可形成在栅极层叠40的侧面上。在形成栅极层叠40之后，可使用层叠40作为注入掩模而注入S/D区域10、12。
随后的处理步骤可在S/D孔26的底部打开栅极氧化物层16，如有必要，提供欧姆接触层，并用多晶硅或金属去填充S/D孔26，以电接触S/D区域10、12。可移除覆盖层24以在形成MOS栅极的S/D区域10、12之间提供与栅极氧化物层16的顶部的电接触。
各种实施方式的钌层46直接形成在阻挡层44上。如就这一点而使用的，术语“直接”表示在钌层46和阻挡层44之间不存在界面层。
本公开的一个或多个实施方式涉及包含在基板14上的多晶硅层20的栅极层叠。多晶硅层20可具有合适的厚度并且可通过任何合适的技术形成。一些实施方式的多晶硅层20包含氧化物-氮化物-氧化物(ONO)结构。
硅化物层42形成在多晶硅层20上。一些实施方式的硅化物层42包含硅化钛(TiSi)。硅化物层42的厚度可为任何合适的厚度。在一些实施方式中，硅化物层42具有在约到约/>的范围中的厚度，或在约/>至约/>的范围中，或在约/>至约/>的范围中。
硅化物层42可通过任何合适的技术或工艺形成。例如，硅化物层42可通过化学气相沉积(CVD)，等离子体增强化学气相沉积(PECVD)，原子层沉积(ALD)，等离子体增强原子层沉积(PEALD)，或物理气相沉积(PVD)而形成。
阻挡层44形成在硅化物层42上。阻挡层可由任何合适的材料和任何合适的技术制成。在一些实施方式中，阻挡层包含氮化物。在一个或多个实施方式中，氮化物包含TiN、TaN、WN或TiSiN的一种或多种。
阻挡层的厚度可为任何合适的厚度。在一些实施方式中，阻挡层44具有在约至约/>的范围中的厚度，或在约/>至约/>的范围中，或在约/>至约/>的范围中。
阻挡层44可通过任何合适的技术或工艺形成。例如，阻挡层44可通过化学气相沉积(CVD)，等离子体增强化学气相沉积(PECVD)，原子层沉积(ALD)，等离子体增强原子层沉积(PEALD)，或物理气相沉积(PVD)而形成。
钌层46形成在阻挡层44上。钌层46通过物理气相沉积形成，并可称为PVD Ru层。钌层46可直接形成在阻挡层44上而没有界面层。如就这一点而使用的，“界面层”是在阻挡层44和钌层46之间分开并有意形成的层。在一些实施方式中，钌层46形成在任选的界面层(未显示)上。
钌层46可形成为任何合适的厚度。在一些实施方式中，钌层46具有在约至约的范围中的厚度，或在约/>至约/>的范围中，或在约/>至约/>的范围中，或在约/>至约/>的范围中。
在一些实施方式中，形成钌层46包含提供等离子体溅射腔室，等离子体溅射腔室包括靶和基座，靶包含钌，基座用于支撑与靶相对的待被溅射沉积的基板。一些实施方式的基座包含保持在大于或等于约350℃的温度的高电流静电卡盘。在一些实施方式中，静电卡盘保持在约450℃至约550℃的范围中的温度。在一些实施方式中，高电流静电卡盘包含高电阻率陶瓷。
等离子体处理气体(如，氪气)流到等离子体溅射腔室中并激发成等离子体。等离子体使得钌原子从钌靶溅射到基板上，以沉积钌层46。在一些实施方式中，等离子体处理气体基本上仅包含氪。如就这一点而使用的，术语“基本上只有”表示活性等离子体物质大于或等于约90原子％的Kr。
在图2的横截面图中示意性地显示了可用于溅射钌层46的溅射腔室50的实例。溅射腔室50包括围绕中心轴线54布置的真空腔室52，钌靶56通过隔离器58被支撑在真空腔室52上，隔离器58将靶56真空密封到真空腔室52，并将靶56与电接地真空腔室52电隔离。真空泵系统(未显示)将真空腔室52的内部抽吸到低毫托范围中的压力。
钌靶56的前表面的形状可为平面的或大体上凹的，具有比内径部分更厚的外周边边缘。钌靶56包括面向真空腔室52内部且通常含有不超过5原子％的钌以外的元素的钌层，以提供溅射钌源。
DC功率源60相对于接地的真空腔室52或接地的侧壁屏蔽(未显示)将靶负偏压到约600至1000VDC，以将等离子体处理气体激发成等离子体。
通常，氩是等离子体处理气体，并通过质流控制器从氩气源供应到真空腔室52中。然而，本发明人已经发现，氩原子可能嵌入沉积的钌层46中，而使用氪气源62作为等离子体处理气体不会导致氪原子的嵌入。因此，各种实施方式的等离子体处理气体基本上由氪组成，或由氪组成。在一些实施方式中，等离子体处理气体基本上仅包含氪原子。氪气源62通过质流控制器64连接到真空腔室52。
靶功率将等离子体处理气体激发成等离子体，且等离子体的正电荷离子朝向靶56加速并从靶中溅射钌原子。等离子体的密度通过放置在靶56的背面的磁控管66而增加，磁控管66具有一种磁极性的内部磁极68，内部磁极68通过相对磁极性的外部磁极70所包围。极68、70将平行于靶56的表面的磁场投射到真空腔室52中，以捕获电子，并从而增加等离子体密度和所得到的溅射速率。为了提高溅射均匀性和靶利用率，磁极68、70围绕中心轴线54而不对称，但是支撑在连接到沿着中心轴线54延伸的轴74的臂72上。马达76使轴74旋转，且从而磁控管66围绕中心轴线54提供至少方位均匀性。
真空腔室52内的基座80支撑与靶56相对的晶片82或其它基板，以涂覆从靶56溅射的钌。除了对准标记之外，晶片通常是平面的和圆形的。任选地，RF功率源84通过电容耦合电路86而偏压基座80。基座80是导电的，使得它用作为电极。在真空腔室52内的等离子体存在下的RF偏压导致基座80上产生负DC自偏压，使得溅射的钌离子朝向晶片82加速，并且它们的轨迹进入形成在晶片82中的任何高深宽比的孔。
在溅射钌层46之后，提供退火腔室来退火钌层46。退火腔室可为适于将具有钌层46的基板的温度升高到大于或等于约500℃的温度的任何腔室。合适的退火腔室包括(但不限于)热处理腔室、快速热退火(RTA)腔室，尖峰退火腔室和激光退火腔室。在一些实施方式中，在氮气环境中，在约900℃的温度下退火钌层约30秒。在一些实施方式中，退火钌层包含将钌层加热至约500℃，以大于或等于约50℃/秒的速率将温度升高至约900℃，保持温度约30秒，并以等于或大于约70℃/秒的速率冷却温度。
在形成包括退火的钌层46之后，在钌层46的侧面46a上形成包含氮化物的间隔层28。一些实施方式的间隔层28包含SiN。在一个或多个实施方式中，间隔层28的形成导致在钌层46的侧面基本上不形成氮化钌。如以这种方式使用的，“基本上不含氮化钌”是指小于约5％的钌层46的宽度变成氮化钌。在一些实施方式中，小于约2％的钌层46的宽度变成氮化钌。
在形成间隔层28之前，期间或之后，可在钌层46的顶部上形成任选的覆盖层24。覆盖层24可由与间隔层28相同的材料制成，或者可为不同的材料。
实施例
图3显示了作为膜厚度的函数的沉积的钌，退火的钌和沉积的钨膜的金属电阻率(μΩ-cm)的曲线图。退火后的钌电阻率与沉积的钨电阻率相似。将钌膜在氮气环境中在约900℃的温度下退火约30秒。
图4显示了沉积的钌和退火的钌膜的钌电阻率(μΩ-cm)的曲线图。膜以约450℃的静电卡盘温度沉积，并在氮气环境中在约825℃或900℃下退火约30秒。
贯穿这份说明书的“一个实施方式”，“某些实施方式”，“一个或多个实施方式”或“实施方式”的引用意味着结合实施方式描述的特定特征、结构、材料或特性包括在本发明的至少一个实施方式中。因此，贯穿这份说明书的各个地方中的诸如“在一个或多个实施方式中”，“在某些实施方式中”，“在一个实施方式中”或“在实施方式中”)的短语的出现不一定指代本发明的相同实施方式。此外，特定的特征、结构、材料或特性可以任何合适的方式结合在一个或多个实施方式中。
尽管已经参考特定实施方式描述了本发明，但是应当理解这些实施方式仅仅是本发明的原理和应用的说明。对于熟悉本领域技术者显而易见的是，在不背离本发明的精神和范围的情况下，可对本发明的方法和设备进行各种修改和变化。因此，本发明意图包括在附随的权利要求及其等效物的范围内的修改和变化。

Claims (19)

1.一种形成膜的方法，所述方法包含以下步骤：
提供等离子体溅射腔室，所述等离子体溅射腔室包括靶和基座，所述靶包含钌，所述基座用于支撑与所述靶相对的待被溅射的基板，所述基座包含大于或等于约350℃的高电流静电卡盘；
将氪气流到所述腔室中，并将所述氪气激发成等离子体，以在所述基板上沉积钌层；
提供退火腔室；及
在N2环境中，在900℃的温度下退火在所述基板上的所述钌层30秒。
2.如权利要求1所述的方法，其中所述静电卡盘的温度在450℃至550℃的范围中。
3.如权利要求1所述的方法，其中所述静电卡盘包含高电阻率陶瓷。
4.如权利要求1所述的方法，其中退火所述钌层包含将所述钌层加热至500℃，以大于或等于50℃/秒的速率将所述温度升高至900℃，将所述温度保持30℃秒，并以等于或大于70℃/秒的速率冷却所述温度。
5.如权利要求1所述的方法，其中所述钌层具有至/>的范围中的厚度。
6.如权利要求1所述的方法，其中所述钌层直接沉积在阻挡层上而没有界面层。
7.如权利要求6所述的方法，其中所述阻挡层包含TiN、TaN、WN或TiSiN的一种或多种。
8.如权利要求7所述的方法，其中所述阻挡层形成在硅化物层上。
9.如权利要求8所述的方法，其中所述硅化物层包含具有的厚度的TiSi。
10.如权利要求1所述的方法，所述方法进一步包含在所述钌层的多个侧面上形成间隔层，所述间隔层包含SiN。
11.如权利要求10所述的方法，其中形成所述间隔层的步骤基本上不形成氮化钌。
12.一种形成膜的方法，所述方法包含以下步骤：
在基板上形成多晶硅层；
在所述多晶硅层上形成硅化物层，所述硅化物层包含具有的厚度的硅化钛；
在所述硅化物层上形成阻挡层，所述阻挡层包含TiN、TaN、WN或TiSiN的一种或多种；
任选地在所述阻挡层上形成界面层；
在所述阻挡层或任选的界面层上沉积PVD Ru层，所述PVD Ru层在氪环境中，以大于或等于350℃的温度，在包含高电阻率陶瓷的高电流静电卡盘上沉积在基板上，所述PVD Ru层具有到/>的范围中的厚度；
所述PVD Ru层在在N2环境中，在900℃的温度下进行退火30秒；以及
在退火的PVD Ru层的侧面上形成间隔层，所述间隔层包含SiN并基本上不形成氮化钌。
13.一种形成膜的方法，所述方法包含以下步骤：
提供等离子体溅射腔室，所述等离子体溅射腔室包括靶和基座，所述靶包含钌，所述基座用于支撑与所述靶相对的待被溅射的上面具有阻挡层的基板，所述基座包含温度大于或等于350℃的高电流静电卡盘，所述阻挡层包含TiN、TaN、WN或TiSiN的一种或多种，所述阻挡层形成在硅化物层上；
将氪气流到所述腔室中，并将所述氪气激发成等离子体，以在所述基板的所述阻挡层上沉积钌层；
提供退火腔室；及
在N2环境中，在900℃的温度下退火在所述基板上的所述钌层30秒。
14.如权利要求13所述的方法，其中所述静电卡盘的温度在450℃至550℃的范围中。
15.如权利要求13所述的方法，其中所述静电卡盘包含高电阻率陶瓷。
16.如权利要求13所述的方法，其中退火所述钌层包含将所述钌层加热至500℃，以大于或等于50℃/秒的速率将所述温度升高至900℃，将所述温度保持30℃秒，并以等于或大于70℃/秒的速率冷却所述温度。
17.如权利要求13所述的方法，其中所述钌层具有至/>的范围中的厚度。
18.如权利要求13所述的方法，其中所述硅化物层包含具有的厚度的TiSi。
19.如权利要求13所述的方法，所述方法进一步包含在所述钌层的多个侧面上形成间隔层，所述间隔层包含SiN。
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