CN116110789A - 高压金属栅极器件的制造方法 - Google Patents

高压金属栅极器件的制造方法 Download PDF

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CN116110789A
CN116110789A CN202111320661.9A CN202111320661A CN116110789A CN 116110789 A CN116110789 A CN 116110789A CN 202111320661 A CN202111320661 A CN 202111320661A CN 116110789 A CN116110789 A CN 116110789A
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gate
metal
voltage
dielectric layer
gate metal
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唐小亮
陈昊瑜
邵华
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明公开了一种高压金属栅极器件的制造方法，经过正常工艺的栅极金属沉积之后，进行栅极金属的CMP工艺时，先进行第一次CMP工艺将栅极金属预先减薄到一定厚度，然后沉积一层阻挡介质层，过光刻打开大面积的高压栅极区域，通过蚀刻把除大面积的高压栅极区域之外的阻挡介质层去除，在对栅极金属进行第二次CMP工艺时，由于高压栅极区域的大面积栅极金属的表面有阻挡介质层，研磨偏慢，不会造成CMP碟形下凹。该高压金属栅极器件的制造方法，不但不存在大块栅极金属的碟形下凹问题，同时也能避免因影响栅极介质层而导致影响高压器件的电性。

Description

高压金属栅极器件的制造方法
技术领域
本发明涉及半导体制造技术，特别是涉及一种高压金属栅极器件的制造方法。
背景技术
从28nm节点向下，高性能工艺会采用HK(高介电常数)介质搭配金属栅极来提高器件性能，金属栅极工艺中不可避免需要使用金属的CMP(chemical mechanical polishing，化学机械抛光)工艺，金属CMP工艺中，大块图形不可避免会出现dishing(碟形下凹)，所以栅极的尺寸不能设计得太大，但对高压器件(操作电压8V～40V)来说，不可避免的需要比较大的栅极尺寸来承担高电压操作，这样就会造成大块金属栅极中栅极高度的下降甚至缺失，具体包括以下步骤：
一.经过前序工艺，进行栅极光刻和刻蚀、侧墙工艺后，定义出伪多晶硅栅极(dummy poly gate)，其中至少有一个伪多晶硅高压栅极2，伪多晶硅栅极的伪多晶硅(dummy polycrystalline)3形成在栅介质层8上，如图1所示；
二.在伪多晶硅栅极之间填充隔离介质4进行CMP(chemical mechanicalpolishing，化学机械抛光)工艺，如图2所示；
三.通过选择性刻蚀，去除伪多晶硅栅极的栅介质层8上的伪多晶硅3，如图3所示；
四.在晶圆上进行栅极金属5淀积，如图4所示；
五.进行栅极金属CMP(chemical mechanical polishing，化学机械抛光)。因为高压栅极2上的栅极金属5比较大，会造成CMP碟形下凹(dishing),导致高压栅极2上的栅极金属5的中间偏薄甚至空缺，如图5所示。
为了解决这个问题，目前比较通用的方法是在大面积的高压栅极中增加沟槽，具体工艺包括以下步骤：
(一)在伪多晶硅栅极(dummy poly gate)光刻和刻蚀时，通过光罩在高压栅极2上的大面积的伪多晶硅3中间挖出连通到栅介质层8的沟槽，如图6所示；
(二).在伪多晶硅栅极之间填充隔离介质4，进行CMP(chemical mechanicalpolishing，化学机械抛光)工艺；
(三).通过选择性刻蚀，去除高压栅极2上的伪多晶硅3；
(四).在晶圆上进行栅极金属5淀积；
(五).进行栅极金属CMP(chemical mechanical polishing，化学机械抛光)工艺。
在大面积的高压栅极2的伪多晶硅3中增加沟槽的方法，高压栅极2的大面积的伪多晶硅3中间因为有填充在沟槽中的隔离介质4阻挡，不会造成CMP碟形下凹(dishing)。但是，在高压栅极2的大面积的伪多晶硅3中增加沟槽的方法，如图6所示，由于高压栅极2的大面积的伪多晶硅3中的沟槽会把其下方的栅介质层8暴露出来，后续工艺包括离子注入、金属硅化物等工艺会在栅极介质层8中引入离子，同时蚀刻和酸洗也会影响暴露在外的栅极介质层8，高压器件的电性会受影响，造成高压器件电性在高压和高温下偏移，降低高压器件的可靠性。
发明内容
本发明要解决的技术问题是提供一种高压金属栅极器件的制造方法，不但不存在大块栅极金属的碟形下凹问题，同时也能避免因影响栅极介质层而导致影响高压器件的电性。
为解决上述技术问题，本发明提供的高压金属栅极器件的制造方法，其包括以下步骤：
S1.经过前序工艺，进行栅极光刻和刻蚀、侧墙工艺后，定义出伪多晶硅栅极，其中至少有一个伪多晶硅高压栅极2，伪多晶硅栅极的伪多晶硅3形成在栅介质层8上；
S2.在伪多晶硅栅极之间填充隔离介质4，进行CMP工艺；
S3.通过选择性刻蚀，去除伪多晶硅栅极的栅介质层8上的伪多晶硅；
S4.在晶圆上进行栅极金属5淀积；
S5.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度；
S6.在栅极金属5上淀积一层阻挡介质层6；
S7.通过光刻打开高压栅极2区域，通过蚀刻把高压栅极2区域之外的阻挡介质层6去除；
S8.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度，由于覆盖的阻挡介质层6的阻挡，高压栅极2区域的栅极金属5会高于高压栅极2区域之外的栅极金属5；
S9.干刻或者酸洗，去除高压栅极2区域的栅极金属5上的阻挡介质层6。
较佳的，S9之后还进行S10,进行栅极金属CMP工艺，调整栅极金属5高度。
较佳的，S8中，进行栅极金属CMP工艺，去除高压栅极2区域之外的高于隔离介质4的栅极金属5，由于覆盖的阻挡介质层6的阻挡，高压栅极2区域上的栅极金属5会高于阻挡介质层6。
较佳的，S1中，定义出的伪多晶硅栅极，其中至少有一个伪多晶硅高压栅极2及一个伪多晶硅低压栅极1。
较佳的，高压栅极2的长度大于2.5μm。
较佳的，S4中，在晶圆上淀积的栅极金属5的厚度大于S2之后的栅极之间的隔离介质4的厚度。
较佳的，S4中，在晶圆上淀积的栅极金属5的厚度为30nm～200nm。
较佳的，S5中，进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度，并且栅极金属5上表面最低处高于栅极之间的隔离介质4。
较佳的，S5中，进行栅极金属CMP工艺，将晶圆上淀积的栅极金属5的厚度减少1/3～2/3。
较佳的，栅介质层8为SiON、HfO2或SiO2；
隔离介质4为SiN或SiO2；
阻挡介质层6为SiN或SiO2；
栅极金属5为Al、Ti或W。
本发明的高压金属栅极器件的制造方法，经过正常工艺的栅极金属5沉积之后，进行栅极金属5的CMP工艺时，先进行第一次CMP工艺将栅极金属5预先减薄到一定厚度，然后沉积一层阻挡介质层6，通过光刻打开大面积的高压栅极2区域，通过蚀刻把除大面积的高压栅极2区域之外的阻挡介质层6去除，在对栅极金属5进行第二次CMP工艺时，由于高压栅极2区域的大面积栅极金属5的表面有阻挡介质层6，研磨偏慢，不会造成CMP碟形下凹(dishing)。该高压金属栅极器件的制造方法，不但不存在大块栅极金属的碟形下凹(dishing)问题，同时也能避免因影响栅极介质层8而导致影响高压器件的电性。
附图说明
为了更清楚地说明本发明的技术方案，下面对本发明所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是高压金属栅极器件的制造方法定义出伪多晶硅栅极示意图；
图2是高压金属栅极器件的制造方法在伪多晶硅栅极之间填充隔离介质示意图；
图3是高压金属栅极器件的制造方法去除伪多晶硅示意图；
图4是高压金属栅极器件的制造方法淀积栅极金属示意图；
图5是现有高压金属栅极器件的制造方法进行栅极金属CMP造成CMP碟形下凹示意图；
图6是通过光罩在高压栅极上的大面积的伪多晶硅中间挖出连通到栅介质层的沟槽示意图；
图7是本发明的高压金属栅极器件的制造方法一实施例进行栅极金属CMP工艺第一次减小栅极金属的厚度示意图；
图8是本发明的高压金属栅极器件的制造方法一实施例在栅极金属上淀积阻挡介质层示意图；
图9是本发明的高压金属栅极器件的制造方法一实施例去除高压栅极区域之外的阻挡介质层示意图；
图10是本发明的高压金属栅极器件的制造方法一实施例进行栅极金属CMP工艺第二次减小栅极金属的厚度示意图；
图11是本发明的高压金属栅极器件的制造方法一实施例去除高压栅极区域的栅极金属上的阻挡介质层并少量抛光示意图。
具体实施方式
下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
实施例一
高压金属栅极器件的制造方法，包括以下步骤：
S1.经过前序工艺，进行栅极光刻和刻蚀、侧墙工艺后，定义出伪多晶硅栅极(dummy poly gate)，其中至少有一个伪多晶硅高压栅极2，伪多晶硅栅极(dummy polygate)的伪多晶硅(dummy polycrystalline)3形成在栅介质层8上，如图1所示；
S2.在伪多晶硅栅极之间填充隔离介质4，进行CMP(chemical mechanicalpolishing，化学机械抛光)工艺，如图2所示；
S3.通过选择性刻蚀，去除伪多晶硅栅极(dummy poly gate)的栅介质层8上的伪多晶硅(dummy polycrystalline)，如图3所示；
S4.在晶圆上进行栅极金属5淀积，如图4所示；
S5.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度，如图7所示；
S6.在栅极金属5上淀积一层阻挡介质层6，如图8所示；；
S7.通过光刻打开高压栅极2区域，通过蚀刻把高压栅极2区域之外的阻挡介质层6去除，如图9所示；
S8.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度，由于覆盖的阻挡介质层6的阻挡，高压栅极2区域的栅极金属5会高于高压栅极2区域之外的栅极金属5，如图10所示；
S9.干刻或者酸洗，去除高压栅极2区域的栅极金属5上的阻挡介质层6。
较佳的，S9之后还进行S10,进行少量的栅极金属CMP工艺，调整栅极金属5高度，如图11所示。
实施例一的高压金属栅极器件的制造方法，经过正常工艺的栅极金属5沉积之后，进行栅极金属5的CMP工艺时，先进行第一次CMP工艺将栅极金属5预先减薄到一定厚度，然后沉积一层阻挡介质层6，通过光刻打开大面积的高压栅极2区域，通过蚀刻把除大面积的高压栅极2区域之外的阻挡介质层6去除，在对栅极金属5进行第二次CMP工艺时，由于高压栅极2区域的大面积栅极金属5的表面有阻挡介质层6，研磨偏慢，不会造成CMP碟形下凹(dishing)。
实施例一的高压金属栅极器件的制造方法，不但不存在大块栅极金属的碟形下凹(dishing)问题，同时也能避免因影响栅极介质层8而导致影响高压器件的电性。
实施例二
基于实施例一的高压金属栅极器件的制造方法，S1中，定义出的伪多晶硅栅极，其中至少有一个伪多晶硅高压栅极2及一个伪多晶硅低压栅极1。
较佳的，高压栅极的长度大于2.5μm。
实施例三
基于实施例一的高压金属栅极器件的制造方法，S8中，进行栅极金属CMP工艺，去除高压栅极2区域之外的高于隔离介质4的栅极金属5，由于覆盖的阻挡介质层6的阻挡，高压栅极2区域上的栅极金属5会高于阻挡介质层6。
实施例四
基于实施例一的高压金属栅极器件的制造方法，S4中，在晶圆上淀积的栅极金属5的厚度大于S2之后的栅极之间的隔离介质4的厚度。
较佳的，S4中，在晶圆上淀积的栅极金属5的厚度为30nm～200nm。
实施例五
基于实施例一的高压金属栅极器件的制造方法，S5中，进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属5的厚度，并且栅极金属5上表面最低处高于栅极之间的隔离介质4。
较佳的，S5中，进行栅极金属CMP工艺，将晶圆上淀积的栅极金属5的厚度减少1/3～2/3。
较佳的，栅介质层8为SiON、HfO2或SiO2；。
较佳的，隔离介质4为SiN或SiO2。
较佳的，阻挡介质层6为SiN或SiO2。
较佳的，栅极金属5为Al、Ti或W。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。

Claims (10)

1.一种高压金属栅极器件的制造方法，其特征在于，包括以下步骤：
S1.经过前序工艺，进行栅极光刻和刻蚀、侧墙工艺后，定义出伪多晶硅栅极，其中至少有一个伪多晶硅高压栅极(2)，伪多晶硅栅极的伪多晶硅(3)形成在栅介质层(8)上；
S2.在伪多晶硅栅极之间填充隔离介质(4)，进行CMP工艺；
S3.通过选择性刻蚀，去除伪多晶硅栅极的栅介质层(8)上的伪多晶硅；
S4.在晶圆上进行栅极金属(5)淀积；
S5.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属(5)的厚度；
S6.在栅极金属(5)上淀积一层阻挡介质层(6)；
S7.通过光刻打开高压栅极(2)区域，通过蚀刻把高压栅极(2)区域之外的阻挡介质层(6)去除；
S8.进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属(5)的厚度，由于覆盖的阻挡介质层(6)的阻挡，高压栅极(2)区域的栅极金属(5)会高于高压栅极(2)区域之外的栅极金属(5)；
S9.干刻或者酸洗，去除高压栅极(2)区域的栅极金属(5)上的阻挡介质层(6)。
2.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
S9之后还进行S10,进行栅极金属CMP工艺，调整栅极金属(5)高度。
3.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
S8中，进行栅极金属CMP工艺，去除高压栅极(2)区域之外的高于隔离介质(4)的栅极金属(5)，由于覆盖的阻挡介质层(6)的阻挡，高压栅极(2)区域上的栅极金属(5)会高于阻挡介质层(6)。
4.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
S1中，定义出的伪多晶硅栅极，其中至少有一个伪多晶硅高压栅极(2)及一个伪多晶硅低压栅极(1)。
5.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
高压栅极(2)的长度大于2.5μm。
6.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
S4中，在晶圆上淀积的栅极金属(5)的厚度大于S2之后的栅极之间的隔离介质(4)的厚度。
7.根据权利要求6所述的高压金属栅极器件的制造方法，其特征在于，
S4中，在晶圆上淀积的栅极金属(5)的厚度为30nm～200nm。
8.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
S5中，进行栅极金属CMP工艺，减小晶圆上淀积的栅极金属(5)的厚度，并且栅极金属(5)上表面最低处高于栅极之间的隔离介质(4)。
9.根据权利要求8所述的高压金属栅极器件的制造方法，其特征在于，
S5中，进行栅极金属CMP工艺，将晶圆上淀积的栅极金属(5)的厚度减少1/3～2/3。
10.根据权利要求1所述的高压金属栅极器件的制造方法，其特征在于，
栅介质层(8)为SiON、HfO2或SiO2；
隔离介质(4)为SiN或SiO2；
阻挡介质层(6)为SiN或SiO2；
栅极金属(5)为Al、Ti或W。
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