US20230142968A1 - Method for Manufacturing High-Voltage Metal Gate Device - Google Patents

Method for Manufacturing High-Voltage Metal Gate Device Download PDF

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Publication number
US20230142968A1
US20230142968A1 US17/958,583 US202217958583A US2023142968A1 US 20230142968 A1 US20230142968 A1 US 20230142968A1 US 202217958583 A US202217958583 A US 202217958583A US 2023142968 A1 US2023142968 A1 US 2023142968A1
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gate
metal
voltage
dielectric layer
manufacturing
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Xiaoliang Tang
Haoyu Chen
Hua Shao
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Shanghai Huali Integrated Circuit Corp
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Shanghai Huali Integrated Circuit Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to a semiconductor manufacturing technology, in particular to a method for manufacturing a high-voltage metal gate device.
  • the high-performance process will use HK (high dielectric constant) dielectric and metal gate to improve the performance of the device.
  • Metal Chemical-Mechanical Polishing (CMP) process is inevitably used in the metal gate process.
  • CMP process large patterns will inevitably have the problem of dishing, so the size of the gate cannot be designed too large.
  • the process specifically includes the following steps:
  • gate photolithography, etching and sidewall processes are performed to define at least one dummy poly gate, and at least one dummy poly gate is dummy poly high-voltage gate 2 , and dummy polycrystalline 3 of the dummy poly gate is formed on a gate dielectric layer 8 , as illustrated in FIG. 1 .
  • Isolation dielectric 4 is filled between the dummy poly gates and a CMP process is performed, as illustrated in FIG. 2 .
  • the dummy polycrystalline on the gate dielectric layer 8 of the dummy poly gate is removed through selective etching, as illustrated in FIG. 3 .
  • a gate metal 5 is deposited on a wafer, as illustrated in FIG. 4 .
  • Gate metal CMP is performed. Since the gate metal 5 on the high-voltage gate 2 is comparatively large, CMP dishing will be caused, resulting in that the middle of the gate metal 5 on the high-voltage gate 2 is thin or even empty, as illustrated in FIG. 5 .
  • the current common method is to add a trench in a large-area high-voltage gate.
  • the specific process includes the following steps:
  • a trench connected to the gate dielectric layer 8 is dug out through a mask in the middle of the large-area dummy polycrystalline 3 on the high-voltage gate 2 , as illustrated in FIG. 6 .
  • An isolation dielectric 4 is filled between the dummy poly gates and a CMP process is performed.
  • a gate metal 5 is deposited on a wafer.
  • etching and acid pickling will also influence the exposed gate dielectric layer 8 , and the electrical properties of the high-voltage device will be affected, causing the electrical properties of the high-voltage device to shift under high voltage and high temperature, and reducing the reliability of the high-voltage device.
  • the technical problem to be solved by the present application is to provide a method for manufacturing a high-voltage metal gate device, which not only avoids the dishing problem of the large gate metal, but also can avoid affecting the electrical properties of the high-voltage device due to the influence on the gate dielectric layer.
  • the method for manufacturing the high-voltage metal gate device includes the following steps:
  • the method for manufacturing the high-voltage metal gate device further includes step S 10 : performing a gate metal CMP process to adjust the height of the gate metal 5 .
  • step S 8 the gate metal CMP process is performed to remove the gate metal 5 above the isolation dielectric 4 outside the high-voltage gate 2 region, wherein due to the blocking effect of the blocking dielectric layer 6 , the gate metal 5 in the high-voltage gate 2 region is higher than the blocking dielectric layer 6 .
  • the defined dummy poly gate includes at least one dummy polycrystalline high-voltage gate 2 and one dummy polycrystalline low-voltage gate 1 .
  • the length of the high-voltage gate 2 is greater than 2.5 ⁇ m.
  • step S 4 the thickness of the gate metal 5 deposited on the wafer is greater than the thickness of the isolation dielectric 4 between gates after step S 2 .
  • the thickness of the gate metal 5 deposited on the wafer is 30 nm-200 nm.
  • step S 5 the gate metal CMP process is performed to reduce the thickness of the gate metal 5 deposited on the wafer, and the lowest position of an upper surface of the gate metal 5 is higher than the isolation dielectric 4 between gates.
  • the gate metal CMP process is performed to reduce the thickness of the gate metal 5 deposited on the wafer by 1/3-2/3.
  • the gate dielectric layer 8 is SiON, HfO 2 or SiO 2 ,
  • the isolation dielectric 4 is SiN or SiO 2 .
  • the blocking dielectric layer 6 is SiN or SiO 2 .
  • the gate metal 5 is Al, Ti or W.
  • the method for manufacturing the high-voltage metal gate device provided by the present application, after the deposition of a gate metal 5 through a normal process, in CMP processes performed to the gate metal 5 , firstly a first CMP process is performed to thin the gate metal 5 to a certain thickness in advance, then a blocking dielectric layer 6 is deposited, a large-area high-voltage gate 2 region is opened through photolithography, and the blocking dielectric layer 6 other than the blocking dielectric layer in the large-area high-voltage gate 2 region is removed through etching.
  • the polishing speed is slow, and CMP dishing will not be caused.
  • the method for manufacturing the high-voltage metal gate device not only avoids the dishing problem of the large gate metal, but also can avoid affecting the electrical properties of the high-voltage device due to the influence on the gate dielectric layer 8 .
  • FIG. 1 illustrates a schematic diagram of a dummy poly gate defined by adopting a method for manufacturing a high-voltage metal gate device.
  • FIG. 2 illustrates a schematic diagram after filling an isolation dielectric between dummy poly gates in a method for manufacturing a high-voltage metal gate device.
  • FIG. 3 illustrates a schematic diagram after removing dummy polycrystalline in a method for manufacturing a high-voltage metal gate device.
  • FIG. 4 illustrates a schematic diagram after depositing a gate metal in a method for manufacturing a high-voltage metal gate device.
  • FIG. 5 illustrates a schematic diagram of CMP dishing caused during gate metal CMP in an existing method for manufacturing a high-voltage metal gate device.
  • FIG. 6 illustrates a schematic diagram of a trench connected to a gate dielectric layer dug out through a mask in the middle of large-area dummy polycrystalline on a high-voltage gate.
  • FIG. 7 illustrates a schematic diagram after performing a gate metal CMP process to reduce the thickness of a gate metal for the first time in a method for manufacturing a high-voltage metal gate device according to an embodiment of the present application.
  • FIG. 8 illustrates a schematic diagram after depositing a blocking dielectric layer on a gate metal in a method for manufacturing a high-voltage metal gate device according to an embodiment of the present application.
  • FIG. 9 illustrates a schematic diagram after removing a blocking dielectric layer outside a high-voltage gate region in a method for manufacturing a high-voltage metal gate device according to an embodiment of the present application.
  • FIG. 10 illustrates a schematic diagram after performing a gate metal CMP process to reduce the thickness of a gate metal for the second time in a method for manufacturing a high-voltage metal gate device according to an embodiment of the present application.
  • FIG. 11 illustrates a schematic diagram after removing a blocking dielectric layer on a gate metal in a high-voltage gate region and performing slight polishing in a method for manufacturing a high-voltage metal gate device according to an embodiment of the present application.
  • a method for manufacturing a high-voltage metal gate device includes the following steps:
  • the method for manufacturing the high-voltage metal gate device further includes step S 10 : performing a slight gate metal CMP process to adjust the height of the gate metal 5 , as illustrated in FIG. 11 .
  • a first CMP process is performed to thin the gate metal 5 to a certain thickness in advance, then a blocking dielectric layer 6 is deposited, a large-area high-voltage gate 2 region is opened through photolithography, and the blocking dielectric layer 6 other than the blocking dielectric layer in the large-area high-voltage gate 2 region is removed through etching.
  • a second CMP process performed to the gate metal 5 due to the blocking dielectric layer 6 on the surface of the large-area gate metal 5 in the high-voltage gate 2 region, the polishing speed is slow, and CMP dishing will not be caused.
  • the method for manufacturing the high-voltage metal gate device according to embodiment 1 not only avoids the dishing problem of the large gate metal, but also can avoid affecting the electrical properties of the high-voltage device due to the influence on the gate dielectric layer 8 .
  • the defined dummy poly gate includes at least one dummy polycrystalline high-voltage gate 2 and one dummy polycrystalline low-voltage gate 1 .
  • the length of the high-voltage gate 2 is greater than 2.5 ⁇ m.
  • step S 8 the gate metal CMP process is performed to remove the gate metal 5 above the isolation dielectric 4 outside the high-voltage gate 2 region. Due to the blocking effect of the blocking dielectric layer 6 , the gate metal 5 in the high-voltage gate 2 region is higher than the blocking dielectric layer 6 .
  • step S 4 the thickness of the gate metal 5 deposited on the wafer is greater than the thickness of the isolation dielectric 4 between gates after step S 2 .
  • the thickness of the gate metal 5 deposited on the wafer is 30 nm-200 nm.
  • step S 5 the gate metal CMP process is performed to reduce the thickness of the gate metal 5 deposited on the wafer, and the lowest position of an upper surface of the gate metal 5 is higher than the isolation dielectric 4 between gates.
  • the gate metal CMP process is performed to reduce the thickness of the gate metal 5 deposited on the wafer by 1/3-2/3.
  • the gate dielectric layer 8 is SiON, HfO 2 or SiO 2 ,
  • isolation dielectric 4 is SiN or SiO 2 .
  • the blocking dielectric layer 6 is SiN or SiO 2 .
  • the gate metal 5 is Al, Ti or W.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
US17/958,583 2021-11-09 2022-10-03 Method for Manufacturing High-Voltage Metal Gate Device Pending US20230142968A1 (en)

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CN202111320661.9 2021-11-09
CN202111320661.9A CN116110789A (zh) 2021-11-09 2021-11-09 高压金属栅极器件的制造方法

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