CN115699307A - 采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法 - Google Patents

采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法 Download PDF

Info

Publication number
CN115699307A
CN115699307A CN202180040282.6A CN202180040282A CN115699307A CN 115699307 A CN115699307 A CN 115699307A CN 202180040282 A CN202180040282 A CN 202180040282A CN 115699307 A CN115699307 A CN 115699307A
Authority
CN
China
Prior art keywords
die
metallization structure
package
interconnect
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180040282.6A
Other languages
English (en)
Inventor
卫洪博
M·徐
A·帕蒂尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN115699307A publication Critical patent/CN115699307A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

公开了采用分离的、双面的IC金属化结构以促进采用堆叠裸片的半导体裸片模块的集成电路(IC)封装，以及相关的制造方法。IC封装中的多个IC裸片在IC裸片模块中以背对背、顶部和底部IC裸片配置的方式被堆叠和结合在一起，这可以将IC封装的高度最小化。金属化结构在与IC裸片模块的相应顶面和底面邻近的分开的顶部金属化结构与底部金属化结构之间被分离，以促进到裸片的裸片到裸片电连接和外部电连接。通过暴露相应的内表面和外表面上的衬底互连件以用于相应的裸片电互连和外部电互连，顶部金属化结构和底部金属化结构可以是双面的。在其他方面，压缩结合被包括在以背对背配置的方式安装在一起的IC裸片之间，以进一步最小化IC封装的总高度。

Description

采用分离的、双面的金属化结构来促进采用堆叠裸片的半导 体裸片(“裸片”)模块的集成电路(IC)封装以及相关的制造 方法
优先权申请
本申请要求2020年6月24日提交的、题目为“INTEGRATED CIRCUIT(IC)PACKAGESEMPLOYING SPLIT,DOUBLE-SIDED METALLIZATION STRUCTURES TO FACILITATE ASEMICONDUCTOR DIE(“DIE”)MODULE EMPLOYING STACKED DICE,AND RELATED FABRICATIONMETHODS”的美国专利申请序列号16/910486的优先权，通过引用以其整体并入本文。
技术领域
本公开的领域涉及集成电路(IC)封装，该IC封装包括附接到封装结构的一个或多个半导体裸片，该封装结构提供至半导体裸片的电接口。
背景技术
集成电路(IC)是电子设备的基石。IC被封装在IC封装中，IC封装也被称为“半导体封装”或“芯片封装”。IC封装包括作为(多个)IC的一个或多个半导体裸片，半导体裸片被安装在封装衬底上并且电耦合到封装衬底，以提供针对(多个)半导体裸片的物理支撑和电接口。封装衬底可以是例如嵌入式迹线衬底(ETS)，嵌入式迹线衬底(ETS)包括在一个或多个电介质层中的嵌入式电迹线，并且包括将电迹线耦合在一起以提供(多个)半导体裸片之间的电接口的垂直互连通路(过孔)。(多个)半导体裸片被安装到在封装衬底的顶层中暴露的互连件并且与其电对接，以将(多个)半导体裸片电耦合到封装衬底的电迹线。
(多个)半导体裸片和封装衬底被包封(encapsulate)在诸如模制化合物的封装材料中，以形成IC封装。IC封装还可以包括球栅阵列(BGA)中的外部焊球，外部焊球电耦合到在封装衬底的底层中暴露的互连件，以将焊球电耦合到封装衬底中的电迹线。焊球提供到IC封装中的(多个)半导体裸片的外部电接口。当IC封装被安装到印刷电路板(PCB)时，焊球电耦合到PCB上的金属接触件，以通过IC封装中的封装衬底PCB中的电迹线到IC芯片之间的电接口。
发明内容
本文公开的方面包括集成电路(IC)封装，该IC封装采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片模块。还公开了相关的芯片封装和制造IC封装的方法。IC封装包括安装在金属化结构上以提供到IC裸片的互连的多个半导体裸片(也被称为“IC裸片”)。在示例性方面中，为了促进缩小IC封装的总高度以节省面积，IC封装中的多个IC裸片在IC封装中的IC裸片模块中以背对背、顶部和底部IC裸片配置的方式被堆叠和结合在一起。然后，为了促进到以背对背配置的方式堆叠的IC裸片的裸片到裸片电连接和外部电连接，IC封装的金属化结构在与IC裸片模块的相应顶面和底面邻近的分开的顶部金属化结构与底部金属化结构之间被分离。IC裸片的有源表面被安装和电连接到它们相应的顶部金属化结构和底部金属化结构，顶部金属化结构和底部金属化结构包括用于在IC裸片之间布线电信号的电迹线的一个或多个布线层。金属化结构具有暴露的衬底互连件，该衬底互连件电连接到IC裸片的有源面上的相应裸片互连件，以提供到IC裸片的电连接。
IC封装的金属化结构在安装在IC裸片模块的相对侧上的顶部金属化结构与底部金属化结构之间被分离，可以允许减小顶部金属化结构和底部金属化结构的组合厚度，而不会有翘曲或机械不稳定性的风险。IC封装的金属化结构在安装在IC裸片模块的相对侧上的顶部金属化结构与底部金属化结构之间被分离，也为IC封装和IC裸片模块提供了对称结构。此外，在示例性方面中，与顶部IC裸片邻近定位的顶部金属化结构可以被配置为主要提供涉及至顶部IC裸片的互连的电迹线，以最小化在顶部金属化结构中的电迹线布线的复杂性。与底部IC裸片邻近定位的底部金属化结构可以被配置为主要提供涉及至底部IC裸片的互连的电迹线，以也最小化在底部金属化结构中的电迹线布线的复杂性。最小化在金属化结构中的电迹线布线的复杂性可以是减小金属化结构的高度并且因此减小IC封装的总高度的重要因素。裸片到裸片互连可以由导电结构(例如，过孔)提供，该导电结构(例如，过孔)延伸通过IC裸片模块中的可用区域并且电连接到顶部金属化结构和底部金属化结构的内表面。因此，作为示例，可以不需要硅通孔(TSV)来提供裸片到裸片互连。
为了进一步促进缩小IC封装的总高度以节省面积，以背对背配置的方式堆叠的IC裸片之间的结合可以是压缩结合(例如，氧化物到氧化物结合)。例如，压缩结合可以是热压缩结合。热压缩结合是一种晶片结合，它也被称为扩散结合、压力结合、热压焊接或固态焊接。因此，作为示例，IC裸片结合不需要粘合剂。与例如粘合剂相比，压缩结合在IC封装的高度方向上可以消耗更少或不消耗附加面积。此外，作为示例，为了进一步促进缩小IC封装的总高度以节省面积，IC裸片的有源侧与其相应的顶部金属化结构和底部金属化结构之间的结合也可以是压缩结合和热压缩结合。
就此而言，在一个示例性方面，提供了一种IC封装。IC封装包括第一金属化结构，第一金属化结构包括至少一个第一互连层。IC封装还包括第二金属化结构，第二金属化结构包括至少一个第二互连层。IC封装还包括被布置在第一金属化结构与第二金属化结构之间的IC裸片模块。IC裸片模块包括第一IC裸片，第一IC裸片包括第一有源表面和第一非有源表面。IC裸片模块还包括第二IC裸片，第二IC裸片包括第二有源表面和第二非有源表面，IC裸片模块还包括在第一IC裸片的第一非有源表面与第二IC裸片的第二有源表面之间的压缩结合，该压缩结合将第一IC裸片的第一非有源表面耦合到第二IC裸片的第二非有源表面。第一IC裸片的第一非有源表面电耦合到第一金属化结构的至少一个第一互连层。第二IC裸片的第二非有源表面电耦合到第二金属化结构的至少一个第二互连层。
在另一个示例性方面，提供了一种制造IC封装的方法。方法包括制造包括至少一个第一互连层的第一金属化结构。方法还包括制造包括至少一个第二互连层的第二金属化结构。方法还包括制造被布置在第一金属化结构与第二金属化结构之间的IC裸片模块。制造IC裸片模块包括提供包括第一有源表面和第一非有源表面的第一IC裸片。IC裸片模块还包括提供包括第二有源表面和第二非有源表面的第二IC裸片。制造IC裸片模块还包括：将第一IC裸片的第一非有源表面压缩结合到第二IC裸片的第二非有源表面，以将第一IC裸片耦合到第二IC裸片。方法还包括：将第一IC裸片的第一有源表面电耦合到第一金属化结构的至少一个第一互连层，以及将第二IC裸片的第二有源表面电耦合到第二金属化结构的至少一个第二互连层。
附图说明
图1是示例性倒装芯片集成电路(IC)封装的侧视图，该封装包括多个半导体裸片，每个半导体裸片被表面安装在封装衬底上并且电连接到封装衬底中的金属化结构以进行裸片连接；
图2A和图2B是采用半导体裸片(“IC裸片”)模块的示例性IC封装的侧视图，该半导体裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片(die-to-die)互连和外部互连；
图3A和图3B是图2A-图2B中的IC封装的右侧视图和左侧视图，以图示IC封装的附加示例性细节；
图4A和图4B是图示制造图2A-图3B中的IC封装的示例性过程的流程图；
图5A-图5E是图示制造图2A-图3B中的IC封装的另一示例性过程的流程图，该过程包括以背对背配置的方式结合(bond)IC裸片，并且使用热压缩结合将IC裸片安装到它们相应的顶部金属化结构和底部金属化结构；
图6A-图6J图示了根据图5A-图5E中的示例性过程的、在制造图2A-图3B中的IC封装期间的示例性制造阶段；
图7是示例性的基于处理器的系统的框图，该系统可以被提供在一个或多个IC封装(包括但不限于图2A-图3B中的IC封装，并且根据图4A和图4B以及图5A-图6J中的制造过程)中，该一个或多个IC封装采用半导体裸片(“IC裸片”)模块，该半导体裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片互连和外部互连；以及
图8是示例性无线通信设备的框图，该无线通信设备包括在一个或多个IC封装(包括但不限于图2A-图3B中的IC封装，并且根据图4A和图4B以及图5A-图6J中的制造过程)中提供的射频(RF)组件，该IC封装采用半导体裸片(“IC裸片”)模块，该半导体裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片互连和外部互连。
具体实施方式
现在参考附图，描述了本公开的几个示例性方面。“示例性”一词在本文中用于表示“作为示例、实例或说明”。在本文中被描述为“示例性”的任何方面不必被解释为比其他方面优选或有利。
在从图2A开始讨论采用分离的、双面的金属化结构以促进采用堆叠裸片的集成电路(IC)裸片模块的IC封装的示例之前，下面在图1中首先描述一种采用公共封装衬底的倒装芯片IC封装，公共封装衬底被定向在相对的IC裸片之间，相对的IC裸片被安装在封装衬底的相对侧上并且电连接到公共封装衬底以进行裸片连接。
就此而言，图1图示了IC组装件100的截面的示意图，该IC组装件100包括使用焊球106被安装到印刷电路板(PCB)104的倒装芯片IC封装102(“IC封装102”)。IC封装102包括具有相应的前表面110(1)-110(4)(即，有源表面)的多个半导体裸片(“IC裸片”)108(1)-108(4)，前表面110(1)-110(4)经由裸片到裸片结合和/或底部填充粘合剂被安装到封装衬底116的相应的前表面112和底表面114。例如，IC裸片108(1)-108(3)可以是提供功率管理相关功能的功率管理IC(PMIC)。作为示例，IC裸片108(4)可以是应用IC裸片，诸如处理器。焊球106形成在封装衬底116的底表面114上，以在IC封装102被安装到PCB 104时，提供到IC裸片108(1)-108(4)的电接口。封装衬底116可以是包括一个或多个电介质层的嵌入式迹线衬底(ETS)，电介质层包括嵌入式电迹线118(例如，铜金属迹线)，嵌入式电迹线118耦合到焊球106以提供焊球106与IC裸片108(1)-108(4)之间的电信号布线。封装衬底116中的电迹线118耦合到从封装衬底116的前表面112和底表面114暴露的焊球120(1)-120(4)，以提供到IC裸片108(1)-108(4)的电连接。IC裸片108(1)-108(4)包括金属互连件(例如，焊垫(pad))，当IC裸片108(1)-108(4)被安装到封装衬底116时，金属互连件耦合到相应的焊球120(1)-120(4)，以提供到封装衬底116中的电迹线118的电连接，电迹线118被布线到连接到PCB 104的焊球106。IC裸片108(1)-108(4)之间的裸片到裸片电连接也可以通过耦合焊球120(1)-120(4)和封装衬底116中的电迹线118来进行。
继续参考图1，封装衬底116包括多个电介质层，这些电介质层可以例如被层压在一起以形成封装衬底116。不同电介质层中的电迹线118通过过孔(未示出)耦合在一起。为了降低封装衬底116中的布线复杂性，封装衬底116可以被设计成使得更多地涉及提供到IC裸片108(1)-108(4)的电连接的电介质层可以邻近相应的IC裸片108(1)-108(4)被定位。就此而言，封装衬底116的更靠近其前表面112和IC裸片108(1)-108(3)被定位的电介质层区域124(1)可以包括涉及至耦合到IC裸片108(1)-108(3)的焊球120(1)-120(3)的电互连的电迹线118。封装衬底116的更靠近其底表面114和IC裸片108(4)被定位的电介质层区域124(2)可以包括更多地涉及提供至耦合到IC裸片108(4)的焊球120(4)的电互连的电迹线118。提供包括用于针对所有IC裸片108(1)-108(4)的电连接的电布线的公共封装衬底116，可以允许在分开的制造工艺中与IC裸片108(1)-108(4)分开地制造封装衬底116，以用于模块化和制造灵活性。然而，这可以使得在封装衬底116中需要较大数目的电介质层。例如，图1中的封装衬底116可以具有十(10)个电介质层。这会增加制造封装衬底116的制造工艺的复杂性，并且导致制造时间和相关联成本增加以及产量降低。可以采用硅通孔(TSV)来提供裸片到裸片互连，但TSV在制造工艺方面昂贵。
就此而言，图2A和图2B是采用半导体裸片(“IC裸片”)模块202的示例性IC封装200的侧视图，该半导体裸片采用堆叠IC裸片204(1)-204(3)。图2B是图示图2A中图示的IC封装200的附加示例性细节的侧视图。如图2A中所示，IC裸片模块202被布置在X轴和Y轴方向上的水平平面P1中，并且形成在分离的、双侧的顶部金属化结构206T与底部金属化结构206B之间，以提供到IC裸片204(1)-204(3)的裸片到裸片互连和外部互连。金属化结构206T、206B包括用于信号布线的电迹线的一个或多个金属或互连层，并且包括垂直互连通路(过孔)以将不同层之间的电迹线耦合在一起。金属化结构206T、206B还用作支撑结构，其中IC裸片模块202可以被布置在支撑结构上并且由其支撑。作为非限制性示例，金属化结构206T、206B可以是封装衬底或再分布层(RDL)。如下面更详细讨论的，金属化结构206T、206B可以包括互连层，互连层为IC封装200中的IC裸片204(1)-204(3)提供外部和裸片到裸片电信号布线。顶部金属化结构206T和底部金属化结构206B被布置在水平平面P2和P3中，水平平面P2和P3在X轴和Y轴方向上并且平行于IC裸片模块202的水平平面P1。作为示例，IC裸片204(1)可以是专用裸片，作为示例，诸如是通用处理器。作为另一示例，IC裸片204(2)、204(3)中的一个IC裸片可以是功率管理IC(PMIC)，功率管理IC(PMIC)控制功率管理功能以用于管理到IC裸片204(1)的功率。作为另一示例，IC裸片204(2)、204(3)中的另一个IC裸片可以是专用处理器，诸如调制解调器或基带处理器。第二IC裸片模块205也被安装在顶部金属化结构206T之上，并且包括电连接到顶部金属化结构206T的其他组件(包括IC裸片207(1)、207(2))。
如下面更详细讨论的，为了最小化图2A中的IC封装200的总高度H1(如Z轴方向上所示)，IC裸片204(1)和IC裸片204(2)、IC裸片204(3)在IC裸片模块202中以背对背配置的方式被结合(即，直接或间接地物理附接)在一起。最小化IC封装200的总高度H1对于最大化对IC封装200的应用的使用可以是重要的。如下面更详细讨论的，IC裸片204(2)、204(3)利用压缩结合208(1)、208(2)被结合到IC裸片204(1)。例如，压缩结合可以是热压缩结合，热压缩结合是氧化物到氧化物热压缩结合。提供压缩结合208(1)、208(2)将IC裸片204(2)、IC裸片204(3)固定到IC裸片204(1)，可以最小化IC裸片模块202的高度H2，并且因此最小化IC封装200的总高度H1，因为作为示例，可以避免附加粘合材料(诸如粘合剂)的使用。热压缩结合是晶片或结合，其也被称为扩散结合、压力接合和热压焊接。在该示例中，如图2A中所示，经由施加力并且可选地同时施加热以形成压缩结合，相应IC裸片204(2)、204(3)的顶部非有源表面211(2)、211(3)与IC裸片204(1)的顶部非有源表面211(1)原子接触。IC裸片204(2)、204(3)自图2A中的IC裸片204(1)倒置。
例如，相应IC裸片204(1)-204(3)的顶部非有源表面211(1)-211(3)可以包括相应的氧化物层215(1)-215(3)，使得相应IC裸片204(2)、204(3)的非有源表面211(2)、211(3)以氧化物到氧化物压缩结合的方式，与IC裸片204(1)的顶部非有源表面211(1)结合。例如，相应IC裸片204(1)-204(3)的顶部非有源表面211(1)-211(3)和它们的氧化物层215(1)-215(3)例如通过压缩结合和热压缩结合被结合在一起。在热压缩结合中，将IC裸片204(2)、204(3)的顶部非有源表面211(2)、211(3)与其氧化物层215(2)、215(3)之间的扩散与IC裸片204(1)的顶部非有源表面211(1)及其氧化物层215(1)原子接触。基于晶格振动，来自IC裸片204(2)、204(3)的氧化物层215(2)、215(3)的原子和来自IC裸片204(1)的顶部非有源表面211(1)的氧化物层215(1)的原子从一个晶格迁移到其他晶格，使得顶部非有源表面211(2)、211(3)和顶部非有源表面211(1)粘附并结合一起。作为另一示例，氧化物层215(1)-215(3)是通过等离子体增强化学气相沉积(PE-CVD)形成的、经化学机械抛光(CMP)处理的氧化物层215(1)-215(3)。在等离子体激活后，具有PE-CVD氧化物层215(1)-25(3)的IC裸片204(1)-204(3)可以由液体表面张力驱动并且被精确对准，然后通过氧化物到氧化物直接结合被紧密地结合到晶圆。在IC裸片204(1)-204(3)的顶部非有源表面211(1)-211(3)被背对背安装，然后以特定的温度(诸如150摄氏度至180摄氏度)烘烤之后，每个IC裸片204(1)-204(3)的氧化物层215(1)-215(3)开始扩散以随后结合，而无需使用任何粘合剂。
继续参考图2A，因为IC裸片204(1)和204(2)、204(3)被结合在一起，所以分离的顶部金属化结构206T和底部金属化结构206B被提供在相应IC裸片204(2)、204(3)和204(1)的上方和下方，以有助于对IC封装200中的IC裸片204(1)-204(3)的外部电信号访问并且提供裸片到裸片互连。就此而言，顶部金属化结构206T和底部金属化结构206B可以是嵌入式迹线衬底(ETS)，嵌入式迹线衬底(ETS)包括在一个或多个电介质材料层中的电迹线，以提供电信号布线。如图2B中的IC封装200的更详细图示中所示，顶部金属化结构206T和底部金属化结构206B提供通过相应顶部金属化结构206T和底部金属化结构206B的相应顶部外表面214和底部外表面216暴露的外部衬底互连件210、212，以提供对IC封装200中的IC裸片204(1)-204(3)的电信号访问。例如，图2B中所示的焊球218电连接到底部金属化结构206B中的外部衬底互连件212，以提供通过底部金属化结构206B到IC裸片204(1)的外部接口。还可以提供电连接到顶部金属化结构206T中的外部衬底互连210的焊球，以提供通过顶部金属化结构206T到IC裸片204(2)、204(3)的外部接口。
注意，术语“顶部”和“底部”是相对术语，并且图2A和图2B中的金属化结构206T被标记为“顶部”，这是因为在该示例中被定向在底部金属化结构206B上方。但还应当注意，IC封装200也可以被定向为自如图2中所示旋转180度的位置，其中底部金属化结构206B将会在顶部金属化结构206T上方。因此，术语“顶部”和“底部”是相对术语，并且不意味着暗示关于一个金属化结构206T对另一金属化结构206B的定向的限制。
继续参考图2B，顶部金属化结构206T和底部金属化结构206B还通过内部的底部衬底互连件220和顶部衬底互连件222向相应的IC裸片204(2)、204(3)和204(1)提供裸片互连，底部衬底互连件220和顶部衬底互连件222通过相应的顶部金属化结构206T和底部金属化结构206B的相应的底部内表面226和顶部内表面224暴露。相应IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)(例如，金属焊垫)电连接到内部衬底互连件220、222。第一IC裸片204(1)的裸片互连件228(1)通过第一IC裸片204(1)的底部有源表面213(1)暴露。第二IC裸片204(2)的裸片互连件228(2)通过第二IC裸片204(2)的底部有源表面213(2)暴露。第三IC裸片204(3)的裸片互连228(3)通过第三IC裸片204(3)的底部有源表面213(3)暴露。裸片互连件228(1)-228(3)通过内部衬底互连件220、222以及通过底部金属化结构206B和顶部金属化结构206T，将相应的IC裸片204(1)-204(3)耦合到它们相应的外部衬底互连件210、212，以提供对IC封装200中的IC裸片204(1)-204(3)的外部电信号访问。因此，通过顶部金属化结构206T和底部金属化结构206B都具有相应的内部的底部衬底互连件220和顶部衬底互连件222以及外部的顶部衬底互连件210和底部衬底互连件212，顶部金属化结构206T和底部金属化结构206B是“双面的(double-sided)”。
在该示例中，相应IC裸片204(1)-204(3)的裸片互连228(1)-228(3)可以被结合到内部衬底互连件220、222，并且通过底部金属化结构206B和顶部金属化结构206T、通过相应的压缩结合231(1)-231(3)被结合到它们相应的外部衬底互连件210、212，以提供对IC封装200中的IC裸片204(1)-204(3)的外部电信号访问。就此而言，通过施加力以及可选地同时施加热，将相应IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)与内部衬底互连件220、222原子接触并穿过底部金属化结构206B和顶部金属化结构206T。将IC裸片204(2)、204(3)的裸片互连件228(1)-228(3)之间的扩散与内部衬底互连件220、222原子接触。来自IC裸片204(1)-204(3)的底部有源表面213(2)、213(3)的原子以及来自底部金属化结构206B和顶部金属化结构206T的内部衬底互连件220、222的原子基于晶格振动，从一个晶格迁移到其他晶格，使得裸片互连件228(1)-228(3)和内部衬底互连件220、222粘合并且对接在一起。
如图2A和图2B中所示的IC封装200的金属化结构在顶部金属化结构206T与底部金属化结构206B之间的分离，还可以促进顶部金属化结构206T和底部金属化结构206B中的电迹线的更有效、不那么复杂的布线，以用于提供对相应IC裸片204(2)、204(3)和204(1)的电信号访问。例如，位于顶部IC裸片204(2)、204(3)上方并且与其最紧密相邻的顶部金属化结构206T可以被设计成包括主要涉及至顶部IC裸片204(2)、204(3)的互连(以及由此与顶部IC裸片204(2)、204(3)的电信号布线)的电迹线。注意，用于IC裸片204(1)-204(3)的“顶部”和“底部”是相对术语，意味着顶部IC裸片204(2)、204(3)被定位成与顶部金属化结构206T相邻，并且底部IC裸片204(1)被定位成与底部金属化结构206T相邻。
类似地，位于底部IC裸片204(1)下方并且与其最紧密相邻的底部金属化结构206B可以被设计成包括主要涉及至底部IC裸片204(1)的互连(以及由此与底部IC裸片204(1)的电信号布线)的电迹线。这允许用于与底部IC裸片204(1)的互连和信号布线所涉及的电迹线必须被包括在与用于与顶部IC裸片204(2)、204(3)的互连和信号布线所涉及的电迹线相同的金属化结构中。如果在单个金属化结构中提供用于所有IC裸片204(1)-204(3)的互连和信号布线所涉及的电迹线，则可能必须在金属化结构中提供附加布线层，以提供足够的“空白空间”以避免电迹线之间的干扰。这些附加的布线层可能向金属化结构添加附加厚度，从而以不希望的方式增加IC衬底的总高度。
此外，通过在图2中的IC封装200中提供分离的顶部金属化结构206T和底部金属化结构206B，可以实现附加的机械稳定性，这可以导致减少的翘曲，同时最小化顶部金属化结构206T和底部金属化结构206B中的布线层。这是因为顶部金属化结构206T和底部金属化结构206B被完全结合到IC裸片模块202，意味着相应的顶部金属化结构206T和底部金属化结构206B的底部内表面226和顶部内表面224被结合到IC裸片模块202。例如，这与以下IC封装形成对比：该IC封装在IC裸片之间包括单个金属化结构，该IC裸片被安装到单个金属化结构的相对的顶部外表面和底部外表面以形成IC封装。在该备选示例中，将会没有被完全结合到单个金属化结构的中间IC裸片模块202。因此，包括这种单个金属化结构的这种IC封装可能更容易受到翘曲和/或机械不稳定性的影响。因此，这种单个金属化结构可能必须包括附加的电介质层以增加更多的机械稳定性和/或避免或减少翘曲，这会增加这种IC封装的总高度。
参考图2B，IC封装200的顶部金属化结构206T和底部金属化结构206B还促进IC裸片204(1)和IC裸片204(2)、204(3)之间通过内部衬底互连件220、222的裸片到裸片互连。可以在IC裸片模块202中形成垂直互连通路(过孔)223，垂直互连通路(过孔)223分别电耦合到顶部金属化结构206T的内部衬底互连件220和底部金属化结构206B的内部衬底互连222，并且在内部衬底互连件220、222之间，以提供顶部金属化结构206T与底部金属化结构206B之间的电信号布线以及通过相应的裸片互连件228(1)-228(3)到IC裸片204(1)-204(3)的电信号布线。可选的无源电气组件217(1)、217(2)(诸如电感器或电容器)也可以形成在IC裸片模块202中，与IC裸片204(1)-204(3)邻近，并且互连到顶部金属化结构206T和底部金属化结构206B中的衬底互连件/在顶部金属化结构206T和底部金属化结构206B中的衬底互连件之间。此外，例如，其他IC封装可以在IC裸片之间提供单个金属化结构，该IC裸片被安装到单个金属化结构的相对的顶部外表面和底部外表面以形成IC封装。然而，作为示例，诸如这种IC封装的单个金属化结构的厚度可能必须包括附加的电介质层来避免翘曲或机械不稳定性，因此导致整体上比图2A和图2B中的IC封装200更高的IC封装。
为了提供关于图2A和图2B中的IC封装200的附加示例性细节，提供了图3A和图3B。图3A是图2A和图2B中的IC封装200在截面S1中的左侧视图。图3B是图2A和图2B中的IC封装200在截面S2中的右侧视图。如图3A和图3B中所示，IC封装200包括底部金属化结构206B和顶部金属化结构206T。作为非限制性示例，底部金属化结构206B包括如图3A和图3B中所示的多个互连层300(1)-300(3)，这些互连层是可以由作为衬底的层压电介质层中的陶瓷材料制成的电介质层或被制造为再分布层(RDL)。顶部互连层300(1)包括顶部内部衬底互连件222，顶部内部衬底互连件222在该示例中是与过孔304(1)接触的金属接触件302(1)。过孔304(1)还与顶部互连层300(1)与底部互连层300(3)之间的中间互连层300(2)中的金属接触件302(2)接触。互连层300(2)中的金属接触件302(2)也与互连层300(2)中的过孔304(2)接触。过孔304(2)与底部外部衬底互连件212接触，底部外部衬底互连件212在该示例中是底部互连层300(3)中的金属接触件302(3)。金属接触件302(3)与焊球218电接触，以提供通过底部金属化结构206B到IC裸片204(1)的外部电信号接口。互连层300(3)中的金属接触件302(3)中的至少一个金属接触件电耦合到互连层300(1)中的至少一个金属接触件302(1)，以提供焊球218与IC裸片204(1)之间的外部电接口。金属接触件302(1)-302(3)可以由具有高导电性的铜制成，以获得较低的信号布线电阻和较高的电性能。
继续参考图3A和图3B，IC封装200还包括顶部金属化结构206T，顶部金属化结构206T包括如图3A和图3B中所示的多个互连层306(1)-306(3)，作为示例，这些互连层是电介质层，并且可以由层压电介质层中的陶瓷材料制成或被制造为RDL。顶部互连层306(1)包括顶部外部衬底互连件210，顶部外部衬底互连件210在该示例中是与顶部互连层306(1)与底部互连层306(3)之间的中间互连层306(2)中的过孔310(2)接触的金属接触308件(1)。过孔310(2)也与互连层306(2)中的金属接触件308(2)接触。互连层306(2)中的金属接触件308(2)也与互连层300(3)中的过孔310(3)接触。过孔310(3)与底部内部衬底互连件220接触，底部内部衬底互连件220在该示例中是互连层300(3)中的金属接触件308(3)。金属接触件308(3)与焊球218电接触，以提供通过底部金属化结构206B到IC裸片204(1)的外部电信号接口。底部互连层306(3)中的金属接触件308(3)中的至少一个金属接触件电耦合到互连层300(1)中的至少一个金属接触件308(1)以提供到IC裸片204(2)、204(3)的外部电接口。金属接触件308(1)-308(3)可以由具有高导电性的铜制成，以获得较低的信号布线电阻和较高的电性能。
参考图3B，形成在IC裸片模块202中的过孔223电耦合到顶部金属化结构206T的金属接触件308(2)和底部金属化结构206T的金属接触件302(2)并且在金属接触件308(2)与金属接触件302(2)之间。过孔223提供顶部金属化结构206T与底部金属化结构206B之间的电信号布线，并且通过相应的裸片互连件228(1)-228(3)提供到IC裸片204(1)-204(3)的电信号布线。
继续参考图3A和图3B，底部金属化结构206B和顶部金属化结构206T各自的互连层300(1)-300(3)和306(1)-306(3)可以是RDL。就此而言，参考图3B中的底部金属化结构206B中的互连层300(1)-300(3)，底部互连层300(3)可以包括诸如电介质材料层的钝化层312(3)，钝化层312(3)被部分地布置在金属接触件302(3)下方。金属接触件302(3)被布置在钝化层312(3)中的开口314(3)中。中间互连层300(2)也可以包括诸如电介质材料层的钝化层312(2)，钝化层312(2)被部分地布置在金属接触件302(2)上方。过孔304(2)和金属接触件302(2)被布置在钝化层312(2)中的开口314(2)中。顶部互连层300(1)也可以包括诸如电介质材料层的钝化层312(1)，钝化层312(1)被部分地布置在过孔304(1)和金属接触件302(1)上方。过孔304(1)和金属接触件302(1)被布置在钝化层312(1)中的开口314(1)中。
参考图3A中的顶部金属化结构206T中的互连层306(1)-306(3)，顶部互连层306(1)可以包括诸如电介质材料层的钝化层316(1)，钝化层316(1)被部分地布置在金属接触件308(1)上方。金属接触件308(1)被布置在钝化层316(1)中的开口318(1)中。中间互连层306(2)也可以包括诸如电介质材料层的钝化层316(2)，钝化层316(2)被部分地布置在金属接触件308(2)上方。过孔310(2)和金属接触件308(2)被布置在钝化层316(2)中的开口318(2)中。底部互连层306(3)也可以包括诸如电介质材料层的钝化层316(3)，钝化层316(3)被部分地布置在过孔310(2)和金属接触件308(2)下方。过孔310(3)和金属接触件308(3)被布置在钝化层316(3)中的开口318(3)中。
返回参考图2B，顶部金属化结构206T、底部金属化结构206B和IC裸片模块202的相应高度H3、H4和H2可以被设计为实现IC封装200的总高度H1，如在图2A中的Z轴方向上所示的。作为非限制性示例，如在Z轴方向上所示的顶部金属化结构206T的高度H3可以在十五(15)微米(μm)(1L)和150μm(10L)之间。作为非限制性示例，如在Z轴方向上所示的底部金属化结构206B的高度H4可以在十五(15)μm(1L)和150μm(10L)之间。作为示例，如在Z轴方向上所示的IC裸片模块202的高度H2可以在100μm和600μm之间。作为非限制性示例，IC裸片模块202的高度H2与顶部金属化结构206T和底部金属化结构206B的组合高度H3+H4的比率可以在0.33和二十(20)之间。
图4A和图4B图示了说明制造图2A-图3B中的IC封装200的示例性过程400的流程图。就此而言，如图4A中所示，过程400包括制造第一金属化结构206B，第一金属化结构206B包括至少一个第一互连层300，诸如上文描述和图3A和图3B中所示的互连层300(1)-300(3)(图4A中的框402)。第一金属化结构206B包括第一顶表面224和第一底表面216。在示例性IC封装200中，第一金属化结构206B包括通过第一金属化结构206B的第一顶表面224暴露的一个或多个第一顶部衬底互连222件。第一金属化结构206B还包括通过第一金属化结构206B的第一底表面216暴露的一个或多个第一底部衬底互连件212。第一金属化结构206B还包括一个或多个第一顶部衬底互连件222中的至少一个第一顶部衬底互连件222，至少一个第一顶部衬底互连件222电耦合到一个或多个第一底部衬底互连件212中的至少一个第一底部衬底互连件212。
继续参考图4A，过程400还包括制造第二金属化结构206T，第二金属化结构206T包括至少一个第二互连层306，诸如上文描述并在图3A和图3B中所示的互连层306(1)-306(3)(图4A中的框404)。在示例性IC封装200中，第二金属化结构206T包括第二顶表面214和第二底表面226。第二金属化结构206T还包括通过第二金属化结构206T的第二顶表面214暴露的一个或多个第二顶部衬底互连件210。第二金属化结构206T还包括通过第二金属化结构206T的第二底表面226暴露的一个或多个第二底部衬底互连件220。第二金属化结构206T还包括一个或多个第二顶部衬底互连件210中的至少一个第二顶部衬底互连件210，该至少一个第二顶部衬底互连件210电耦合到一个或多个第二底部衬底互连件220中的至少一个第二底部衬底互连件220。
继续参考图4A，过程400还包括制造布置在第一金属化结构206B与第二金属化结构206T之间的IC裸片模块202(图4A中的框406)。制造IC裸片模块202包括：提供包括第一有源表面213(1)和第一非有源表面211(1)的第一IC裸片204(1)(图4A中的框406(1))。制造IC裸片模块202还包括：提供包括第二有源表面213(2)和第二非有源表面211(2)的第二IC裸片204(2)(图4A中的框406(2))。制造IC裸片模块202还包括：将第一IC裸片204(1)的第一非有源表面211(1)压缩结合到第二IC裸片204(2)的第二非有源表面211(2)(图4A中的框406(3))。例如，第一IC裸片204(1)的第一非有源表面211(1)和第二IC裸片204(2)的第二非有源表面211(2)可以以背对背配置的方式被压缩结合在一起。第一IC裸片204(1)的第一非有源表面211(1)可以被压缩结合到第二IC裸片204(2)的第二非有源表面211(2)，以将第一IC裸片204(1)耦合到第二IC裸片204(2)。
参考图4B，制造IC封装200还包括：将第一IC裸片204(1)的第一有源表面213(1)电耦合到第一金属化结构206B的至少一个第一互连层300(图4B中的框408)。例如，在IC封装200中，将第一IC裸片204(1)的第一有源表面213(1)电耦合到第一金属化结构206B的至少一个第一互连层300可以包括：将第一IC裸片204(1)的一个或多个第一裸片互连件228(1)中的至少一个第一裸片互连件电耦合到第一金属化结构206B的一个或多个第一底部衬底互连件222中的至少一个第一底部衬底互连件。制造IC裸片模块202还包括：将第二IC裸片204(2)的第二有源表面213(1)电耦合到第二金属化结构206T的至少一个第二互连层306(图4B中的框410)。例如，在IC封装200中，将第二IC裸片204(2)的第二有源表面213(2)电耦合到第二金属化结构206T的至少一个第二互连层306可以包括：将第二IC裸片204(2)的一个或多个第二裸片互连件228(2)中的至少一个第二裸片互连件电耦合到第二金属化结构206T的一个或多个第一底部衬底互连件220中的至少一个第一底部衬底互连件。
如上所述，图2中IC封装200的分离的、顶部金属化结构206T和底部金属化结构206B可以包括根据RDL制造工艺制造的RDL。RDL是金属(例如，铜)焊垫层在电介质材料层上的分布。第二电介质材料层形成在金属层之上，然后被图案化以打开通往下方金属层的通道。第二金属焊垫层可以跨第二电介质层分布，并且向下进入开口中，以在第二金属焊垫层与第一金属焊垫层之间形成互连。顶部金属化结构206T的衬底互连件210、220和底部金属化结构206B的衬底互连件212、222可以由从顶部金属化结构206T和底部金属化结构206B的相应内表面RDL暴露的金属层/焊垫来形成。可以由RDL形成的顶部金属化结构206T和底部金属化结构206B，可以减小相应的内部衬底互连件220、222到IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)的电阻，这是因为内部衬底互连件220、222是针对RDL中在顶部金属化结构206T和底部金属化结构206B的内表面224、226上暴露的金属层/焊垫而形成的。形成在顶部金属化结构206T和底部金属化结构206B的RDL中的金属层/焊垫比其他类型的互连件(诸如焊球)更加导电并且可以具有更小的电阻。
就此而言，图5A-图5E图示了说明制造图2A-图3B中的IC封装200的示例性过程500的流程图，过程500包括形成顶部金属化结构206T和底部金属化结构206B作为衬底。图6A-图6J图示了当制造过程出现时，图2A-图3B中的IC封装200的图5A-图5E中的过程步骤中的每个过程步骤的示例性制造阶段。将结合下文描述图5A-图5E中的过程步骤和图6A-图6J中的示例性相关制造阶段。
参考图5A，制造图2A-图3B中的IC封装200的过程包括提供和制备IC裸片204(1)-204(3)，用于其背对背结合为IC封装200的一部分。就此而言，图6A图示了制造阶段600A中的IC裸片204，其中IC裸片204可以是IC裸片204(1)-204(3)中的任何IC裸片。图6A中示出了仅一个IC裸片204，但注意图6A中的IC裸片204可以是IC裸片204(1)-204(3)中的任何IC裸片。通过减薄图6B中的制造阶段600B中所示的IC裸片204的顶部非有源表面211来制备IC裸片204(图5A中的框502)。然后，将氧化物层602添加到IC裸片204的顶部非有源表面211，以制备IC裸片204的顶部非有源表面211，顶部非有源表面211用于氧化物到氧化物压缩结合到另一IC裸片204的另一底部非有源表面(图5A中的框504)。
制造过程500中的下一个过程步骤涉及制备IC封装200的IC裸片204(1)-204(3)，IC裸片204(1)-204(3)要以背对背配置的方式被压缩结合在一起。这在图6C和图6D中的示例性制造阶段600C和600D中被示出。如图6C中的制造阶段600C中所示，临时结合膜604(1)形成在IC裸片204(1)的有源底表面213(1)上，并且被安装到载体606(1)上以能够在结合过程期间处理IC裸片204(1)(图5B中的框506)。同样如图6C中的制造阶段600C中所示的，临时结合膜604(2)形成在IC裸片204(2)、204(3)的有源底表面213(2)、213(3)上，并且被安装到载体606(2)上以便能够在结合过程期间处理IC裸片204(2)、204(3)(图5B中的框506)。例如，载体606(1)、606(2)允许IC裸片204(1)-204(3)被操纵和对齐，以用于将IC裸片204(1)-204(3)的相应顶部非有源表面211(1)-211(3)上的氧化物层602(1)-602(3)结合在一起，以将IC裸片204(1)-204(3)结合在一起，作为形成图2A-图3B中的IC封装200的IC裸片模块202的一部分，如图6D中的制造阶段600D中所示的(图5B中的框508)。
例如，相应IC裸片204(1)-204(3)的顶部非有源表面211(1)-211(3)及其氧化物层215(1)-215(3)通过压缩结合和热压缩结合被结合在一起。在热压缩结合中，将IC裸片204(2)、204(3)的顶部非有源表面211(2)、211(3)与其氧化物层215(2)、215(3)之间的扩散与IC裸片204(1)的顶部非有源表面211(1)及其氧化物层215(1)原子接触。来自IC裸片204(2)、204(3)的氧化物层215(2)、215(3)的原子和来自IC裸片204(1)的顶部非有源表面211(1)的氧化物层215(1)的原子基于晶格振动从一个晶格迁移到其他晶格，使得顶部非有源表面211(2)、211(3)和顶部非有源表面211(1)粘附并结合在一起。作为另一示例，氧化物层215(1)-215(3)可以是由等离子体增强化学气相沉积(PE-CVD)形成的、经化学机械抛光(CMP)处理的氧化物层215(1)-215(3)。在等离子体激活后，具有PE-CVD氧化物层215(1)-215(3)的IC裸片204(1)-204(3)可以由液体表面张力驱动并且被精确对准，然后通过氧化物到氧化物直接结合被紧密地结合到晶圆。在IC裸片204(1)-204(3)的顶部非有源表面211(1)-211(3)被背对背安装，然后以特定的温度(诸如150摄氏度至180摄氏度)烘烤之后，每个IC裸片204(1)-204(3)的氧化物层215(1)-215(3)开始扩散以随后结合，而无需使用任何粘合剂。
制造过程500中的下一个过程步骤涉及：制备底部金属化结构206B和顶部金属化结构206T，IC裸片204(1)-204(3)被安装到底部金属化结构206B和顶部金属化结构206T作为IC封装200的一部分，如图6E和图6F-1-图6F-2中的制造阶段600E和600F中所示的。IC裸片204(1)-204(3)到底部金属化结构206B和顶部金属化结构206T的安装是对齐的，使得IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)电连接到底部金属化结构206B和顶部金属化结构206T的相应的底部衬底互连件220和顶部衬底互连件222，以提供到IC裸片204(1)-204(3)的电连接。就此而言，如图6E中的制造阶段600E中所示，提供了底部金属化结构206B。可以是例如焊球的过孔223形成在底部金属化结构206B上，以提供从底部金属化结构206B到顶部金属化结构206T的互连(图5C中的框510)。底部金属化结构206B被制造和/或处理，使得底部衬底互连件222通过底部金属化结构206B的内表面226暴露(图5C中的框510)。如图6F-1中的制造阶段600F中所示，提供了顶部金属化结构206T。顶部金属化结构206T被制造和/或处理，使得底部衬底互连件220通过顶部金属化结构206T的内表面224暴露(图5C中的框512)。然后，底部金属化结构206B和顶部金属化结构206T的顶部衬底互连件222和底部衬底互连件220被压缩结合608(例如，热压缩结合)到IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)(图5C中的框512)。这也在图6F-2中的制造阶段600F的更详细的图示中被示出，制造阶段600F用于压缩结合顶部金属化结构206T中的IC裸片204(2)，但也适用于将IC裸片204(1)、204(3)压缩结合到相应的底部金属化结构206B和顶部金属化结构206T。如图6F-2中所示，顶部金属化结构206T的底部衬底互连件220被压缩结合(例如，热压缩结合)到IC裸片204(2)的裸片互连件228(2)以形成压缩结合610(2)。然后，如图6G中的制造阶段600G中所示，电介质材料613被布置在顶部金属化结构206T与底部金属化结构206B之间，以添加用于保护IC裸片204(1)-204(3)和过孔223的结构，并且防止电短路(图5D中的框514)。
例如，通过压缩结合和热压缩结合，压缩接点608在底部金属化结构206B和顶部金属化结构206T的顶部衬底互连件222和底部衬底互连件220与IC裸片204(1)-204(3)的裸片互连228(1)-228(3)之间形成结合。在压缩结合中，将底部金属化结构206B和顶部金属化结构206T的顶部衬底互连件222和底部衬底互连件220与IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)之间的扩散原子接触。来自底部金属化结构206B和顶部金属化结构206T的顶部衬底互连件222和底部衬底互连件220的原子以及来自IC裸片204(1)-204(3)的裸片互连件228(1)-228(3)的原子基于晶格振动从一个晶格迁移到其他晶格，使得底部金属化结构206B和顶部金属化结构206T的底部衬底互连件222、220粘合并结合在一起。也可以通过在压缩结合期间进行烘烤(诸如以230摄氏度-280摄氏度之间的温度)来施加热压力以增强扩散。
然后，在如图6H中所示的下一个制造阶段600H中，诸如IC裸片207(1)、207(2)和其他电气组件612的附加电气组件可以被安装到顶部金属化结构206T，作为IC封装200的一部分(图5E中的框516)。然后，在如图6I中所示的下一个制造阶段600I中，电介质材料614或模制化合物可以被布置在IC裸片207(1)、207(2)和其他电气组件612之上作为IC封装200的一部分用于保护(图5E中的框518)。然后，在如图6J中所示的下一个制造阶段600J中，焊球218被形成为与底部金属化结构206B电接触，以提供到IC封装中的IC裸片204(1)-204(3)和其他IC裸片207(1)、207(2)和电气组件612的外部接口。
注意，本文使用的“顶部”和“底部”是相对术语，并且不意味着限制或暗示“顶部”引用的元素必须始终被定向为高于“底部”引用的元素的严格定向，反之亦然。
采用IC裸片模块的IC封装(包括但不限于图2A-图3B中的IC封装，并且根据图2A-图3B中的制造过程，以及根据图4A和图4B以及图5A-图6J中的制造过程)可以被提供在或被集成到任何基于处理器的设备中，IC裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片互连和外部互连。示例包括但不限于：机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、全球定位系统(GPS)设备、移动电话、蜂窝电话、智能电话、会话发起协议(SIP)电话、平板计算机、平板手机、服务器、计算机、便携式计算机、移动计算设备、可穿戴计算设备(例如，智能手表、健康或健身跟踪器、眼镜等)、台式计算机、个人数字助理(PDA)、监控器、计算机显示器、电视、调谐器、无线电设备、卫星无线电设备、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、便携式数字视频播放器、机动车、交通工具组件、航空电子系统、无人机和多轴线飞行器。
就此而言，图7图示了基于处理器的系统700的一个示例，系统700包括可以在采用IC裸片模块的IC封装702(包括但不限于图2A-图3B中的IC封装，并且根据图4A和图4B以及图5A-图6J中的制造过程，以及根据本文公开的任何方面)中提供的电路，IC裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片互连和外部互连。在该示例中，基于处理器的系统700可以形成为IC封装702中的IC 704和片上系统(SoC)706。基于处理器的系统700包括CPU 708，CPU 708包括一个或多个处理器710，处理器710也可以被称为CPU核或处理器核。CPU 708可以具有耦合到CPU 708的高速缓冲存储器712，以用于快速访问临时存储的数据。CPU 708耦合到系统总线714并且可以将包括在基于处理器的系统700中的主设备和从设备互耦。众所周知，CPU 708通过在系统总线714上交换地址、控制和数据信息来与这些其他设备通信。例如，CPU 708可以将总线事务请求传输到作为从设备的一个示例的存储器控制器716。尽管图7中未图示，但可以提供多个系统总线714，其中每个系统总线714构成不同的结构。
其他主设备和从设备可以连接到系统总线714。作为示例，如图7中图示的，这些设备可以包括存储器系统720(存储器系统720包括存储器控制器716和(多个)存储器阵列718)、一个或多个输入设备722、一个或多个输出设备724、一个或多个网络接口设备726和一个或多个显示控制器728。存储器系统720、一个或多个输入设备722、一个或多个输出设备724、一个或多个网络接口设备726和一个或多个显示控制器728中的每个可以被提供在相同或不同的IC封装702中。(多个)输入设备722可以包括任何类型的输入设备，包括但不限于输入键、开关、语音处理器等。(多个)输出设备724可以包括任何类型的输出设备，包括但不限于音频、视频、其他视觉指示器等。(多个)网络接口设备726可以是被配置为允许与网络730交换数据的任何设备。网络730可以是任何类型的网络，包括但不限于有线或无线网络、专用或公共网络、局域网(LAN)、无线局域网(WLAN)、广域网(WAN)、BLUETOOTHTM网络和因特网。(多个)网络接口设备726可以被配置为支持所需的任何类型的通信协议。
CPU 708还可以被配置为通过系统总线714访问(多个)显示控制器728以控制发送到一个或多个显示器732的信息。(多个)显示控制器728将信息发送到(多个)显示器732以经由一个或多个视频处理器734进行显示，视频处理器734将要被显示的信息处理成适于(多个)显示器732的格式。作为示例，(多个)显示控制器728和(多个)视频处理器734可以作为IC被包括在相同或不同的IC封装702中，以及被包括在包含CPU 708的相同或不同的IC封装702中。(多个)显示器732可以包括任何类型的显示器，包括但不限于阴极射线管(CRT)、液晶显示器(LCD)、等离子显示器、发光二极管(LED)显示器等。
图8图示了包括由一个或多个IC 802形成的射频(RF)组件的示例性无线通信设备800，其中IC 802中的任何IC可以被包括在采用IC裸片模块的IC封装803(包括但不限于图2A-图3B中的IC封装，并且根据图4A和图4B以及图5A-图6J中的制造过程，以及根据本文公开的任何方面)中，IC裸片模块采用在分离的、双面的顶部金属化结构与底部金属化结构之间形成的堆叠IC裸片，以提供到IC裸片的裸片到裸片互连和外部互连。作为示例，无线通信设备800可以包括上述设备中的任何设备或被提供在上述设备中的任何设备中。如图8中所示，无线通信设备800包括收发器804和数据处理器806。数据处理器806可以包括用于存储数据和程序代码的存储器。收发器804包括支持双向通信的发射器808和接收器810。通常，无线通信设备800可以包括用于任何数目的通信系统和频带的任何数目的发射器808和/或接收器810。收发器804的全部或一部分可以被实现在一个或多个模拟IC、RF IC(RFIC)、混合信号IC等上。
发射器808或接收器810可以用超外差架构或直接转换架构来被实现。在超外差架构中，信号在RF与基带之间分多个阶段进行频率转换，例如，对于接收器810，在一个阶段中从RF转换到中频(IF)，然后在另一阶段从IF转换到基带。在直接转换架构中，信号在一个阶段中在RF与基带之间进行频率转换。超外差转换架构和直接转换架构可以使用不同的电路块和/或具有不同的要求。在图8中的无线通信设备800中，发射器808和接收器810利用直接转换架构来进行实现。
在发射路径中，数据处理器806处理要被发射的数据，并且向发射器808提供I和Q模拟输出信号。在示例性无线通信设备800中，数据处理器806包括数模转换器(DAC)812(1)、812(2)，以用于将由数据处理器806生成的数字信号转换成I和Q模拟输出信号，例如I和Q输出电流，以进行进一步处理。
在发射器808内，低通滤波器814(1)、814(2)分别对I和Q模拟输出信号进行滤波，以去除由先前的数模转换引起的不期望信号。放大器AMP 816(1)、816(2)分别放大来自低通滤波器814(1)、814(2)的信号，并且提供I和Q基带信号。上转换器818通过混频器820(1)、820(2)，利用来自TX LO信号生成器822的I和Q发射(TX)本地振荡器(LO)信号，来对I和Q基带信号进行上转换，以提供上转换信号824。滤波器826对上转换信号824进行滤波，以去除由频率上转换引起的不期望信号以及接收频带中的噪声。功率放大器(PA)828放大来自滤波器826的上转换信号824，以获得期望的输出功率水平并且提供发射RF信号。发射RF信号通过双工器或交换机830进行路由，并且经由天线832被发射。
在接收路径中，天线832接收由基站发射的信号，并且提供接收的RF信号，该RF信号通过双工器或交换机830进行路由，并且被提供给低噪声放大器(LNA)834。双工器或交换机830被设计成与特定的接收(RX)至TX双工器频率分离操作，以使RX信号与TX信号隔离。所接收的RF信号被LNA 834放大，并且被滤波器836滤波以获得期望的RF输入信号。下转换混频器838(1)、838(2)将滤波器836的输出与来自RX LO信号生成器840的I和Q RX LO信号(即，LO_I和LO_Q)混合，以生成I和Q基带信号。I和Q基带信号被放大器(AMP)842(1)、842(2)放大，并且被低通滤波器844(1)、844(2)进一步滤波，以获得I和Q模拟输入信号，I和Q模拟输入信号被提供给数据处理器806。在该示例中，数据处理器806包括ADC 846(1)、846(2)，以用于将模拟输入信号转换成数字信号，以供数据处理器806进一步处理。
在图8的无线通信设备800中，TX LO信号生成器822生成用于频率上转换的I和QTX LO信号，而RX LO信号生成器840生成用于频率下转换的I和Q RX LO信号。每个LO信号是具有特定基频的周期信号。TX锁相环(PLL)电路848从数据处理器806接收定时信息，并且生成用于调整来自TX LO信号生成器822的TX LO信号的频率和/或相位的控制信号。类似地，RX PLL电路850从数据处理器806接收定时信息，并且生成用于调整来自RX LO信号生成器840的RX LO信号的频率和/或相位的控制信号。
本领域技术人员将进一步理解，结合本文公开的方面描述的各种说明性的逻辑块、模块、电路和算法可以实现为电子硬件、存储在存储器或另一计算机可读介质中并且由处理器或其他处理设备执行的指令或两者的组合。作为示例，本文描述的主设备和从设备可以在任何电路、硬件组件、集成电路(IC)或IC芯片中被采用。本文公开的存储器可以是任何类型和大小的存储器，并且可以被配置为存储期望的任何类型的信息。为了清楚地说明这种可互换性，上面已经大体上根据其功能描述了各种说明性的组件、框、模块、电路和步骤。如何实现这种功能取决于特定的应用、设计选择和/或施加于整个系统的设计约束。本领域技术人员可以针对每个特定的应用以变化的方式来实现所描述的功能，但是这种实现决定不应当被解释为导致脱离本公开的范围。
结合本文公开的方面描述的各种说明性逻辑块、模块和电路可利用被设计成执行本文所描述的功能的处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其他可编程逻辑设备、分立的门或晶体管逻辑、分立的硬件组件或其任何组合来进行实现或执行。处理器可以是微处理器，但在备选方案中，处理器可以是任何常规的处理器、控制器、微控制器或状态机。处理器还可以被实现为计算设备的组合(例如DSP与微处理器的组合、多个微处理器、与DSP核结合的一个或更多个微处理器或任何其他这种配置)。
本文公开的方面可以以硬件和被存储在硬件中的指令来体现，并且可以驻存在例如随机存取存储器(RAM)、闪存、只读存储器(ROM)、电可编程ROM(EPROM)、电可擦可编程ROM(EEPROM)、寄存器、硬盘、可移动磁盘、CD-ROM或本领域已知的任何其他形式的计算机可读介质中。示例性存储介质耦合到处理器，使得处理器能够从该存储介质读取信息并且能够向该存储介质写入信息。在备选方案中，存储介质可以被整合到处理器。处理器和存储介质可驻存在ASIC中。ASIC可以驻存在远程站中。在备选方案中，处理器和存储介质可以作为分立组件驻存在远程站、基站或服务器中。
还应当注意，描述了本文的任何示例性方面中描述的操作性步骤以提供示例和讨论。所描述的操作可以以除了图示的顺序之外的许多不同的顺序执行。另外，在单个操作步骤中描述的操作实际上可以在许多不同的步骤中执行。附加地，可以组合示例性方面中讨论的一个或多个操作步骤。应当理解，流程图中图示的操作步骤可以进行许多不同的修改，这对于本领域技术人员来说是明显的。本领域技术人员还将理解，可以使用多种不同科技和技术中的任何一种来表示信息和信号。例如，在以上整个说明书中可能引用的数据、指令、命令、信息、信号、位、符号和码片可以由电压、电流、电磁波、磁场或粒子、光学场或粒子或其任何组合表示。
提供对本公开的先前描述以使本领域技术人员能够制造或使用本公开。对本公开的各种修改对于本领域技术人员而言将是明显的，并且本文中定义的一般原理可以应用于其他变型。因此，本公开内容不旨在限于本文描述的示例和设计，而是与符合本文公开的原理和新颖特征的最宽范围一致。

Claims (25)

1.一种集成电路(IC)封装，包括：
第一金属化结构，包括至少一个第一互连层：
第二金属化结构，包括至少一个第二互连层；以及
IC裸片模块，被布置在所述第一金属化结构与所述第二金属化结构之间，所述IC裸片模块包括：
第一IC裸片，包括第一有源表面和第一非有源表面；
第二IC裸片，包括第二有源表面和第二非有源表面；以及
压缩结合，在所述第一IC裸片的所述第一非有源表面与所述第二IC裸片的所述第二非有源表面之间，将所述第一IC裸片的所述第一非有源表面耦合到所述第二IC裸片的所述第二非有源表面；
所述第一IC裸片的所述第一非有源表面电耦合到所述第一金属化结构的所述至少一个第一互连层；并且
所述第二IC裸片的所述第二非有源表面电耦合到所述第二金属化结构的所述至少一个第二互连层。
2.根据权利要求1所述的IC封装，其中：
所述第一金属化结构被布置在第一水平平面内；
所述第二金属化结构被布置在平行于所述第一水平平面的第二水平平面内；
所述第一IC裸片被布置在平行于所述第一水平平面的第三水平平面内；并且
所述第二IC裸片被布置在平行于所述第一水平平面的所述第二水平平面内。
3.根据权利要求1所述的IC封装，其中：
所述第一金属化结构包括第一再分布层(RDL)结构；并且
所述第二金属化结构包括第二RDL结构。
4.根据权利要求1所述的IC封装，其中：
所述第一金属化结构包括第一封装衬底；并且
所述第二金属化结构包括第二封装衬底。
5.根据权利要求1所述的IC封装，其中：
所述第一IC裸片的所述第一有源表面包括第一底部有源表面；
所述第一IC裸片的所述第一非有源表面包括第一顶部非有源表面；
所述第二IC裸片的所述第二有源表面包括第二底部有源表面；并且
所述第二IC裸片的所述第二非有源表面包括第二顶部非有源表面。
6.根据权利要求1所述的IC封装，其中：
所述第一IC裸片还包括从所述第一有源表面暴露的至少一个第一裸片互连件；
所述第二IC裸片还包括从所述第二有源表面暴露的至少一个第二裸片互连件；并且
还包括：
第一压缩结合，在所述至少一个第一裸片互连件与所述至少一个第一互连层之间，将所述至少一个第一裸片互连件电耦合到所述至少一个第一互连层；以及
第二压缩结合，在所述至少一个第二裸片互连件与所述至少一个第二互连层之间，将所述至少一个第二裸片互连件电耦合到所述至少一个第二互连层。
7.根据权利要求6所述的IC封装，其中：
所述第一金属化结构还包括电耦合到所述至少一个第一互连层的至少一个第一衬底互连件；
所述第二金属化结构还包括电耦合到所述至少一个第二互连层的至少一个第二衬底互连件；
所述至少一个第一裸片互连件电耦合到所述至少一个第一衬底互连件，以电耦合到所述至少一个第一互连层；并且
所述至少一个第二裸片互连件电耦合到所述至少一个第二衬底互连，以电耦合到所述至少一个第二互连层。
8.根据权利要求2所述的IC封装，其中：
所述第一金属化结构在垂直于所述第一水平平面的高度轴线方向上的高度在十五(15)微米(μm)与150μm之间；并且
所述第二金属化结构在垂直于所述第一水平平面的所述高度轴线方向上的高度在十五(15)μm与150μm之间。
9.根据权利要求8所述的IC封装，其中所述IC裸片模块在垂直于所述第一水平平面的所述高度轴线方向上的高度在100μm与600μm之间。
10.根据权利要求2所述的IC封装，其中所述IC裸片模块在垂直于所述第一水平平面的高度轴线方向上的高度与所述第一金属化结构和所述第二金属化结构在所述高度轴线方向上的组合高度的比率在0.33与20.0之间。
11.根据权利要求1所述的IC封装，其中：
所述IC裸片模块还包括第三IC裸片，所述第三IC裸片包括第三有源表面和第三非有源表面；
所述第三IC裸片的所述第三非有源表面与所述第一IC裸片的所述第一非有源表面之间的压缩结合将所述第一IC裸片的所述第三非有源表面电耦合到所述第一IC裸片的所述第一非有源表面；并且
所述第三IC裸片的所述第三非有源表面电耦合到所述第二金属化结构的所述至少一个第二互连层。
12.根据权利要求11所述的IC封装，其中：
所述第三IC裸片还包括从所述第三有源表面暴露的至少一个第三裸片互连件；并且
还包括：
第三压缩结合，在所述至少一个第三裸片互连件与所述至少一个第二互连层之间，将所述至少一个第三裸片互连件电耦合到所述至少一个第二互连层。
13.根据权利要求1所述的IC封装，其中所述IC裸片模块还包括至少一个无源电气设备，所述至少一个无源电气设备被布置成与所述第一IC裸片和所述第二IC裸片相邻；
所述至少一个无源电气设备电耦合到所述第一金属化结构的所述至少一个第一互连层以及所述第二金属化结构的所述至少一个第二互连层。
14.根据权利要求1所述的IC封装，其中所述IC裸片模块还包括与所述第一IC裸片和所述第二IC裸片邻近布置的至少一个垂直互连通路(过孔)；
所述至少一个过孔电耦合到所述第一金属化结构的至少一个第一互连层以及所述第二金属化结构的至少一个第二互连层。
15.根据权利要求1所述的IC封装，还包括电耦合到所述第一金属化结构的至少一个第一互连层的至少一个焊料凸块。
16.根据权利要求1所述的IC封装，所述IC封装被集成到设备中，所述设备选自由以下项组成的组：机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、全球定位系统(GPS)设备、移动电话、蜂窝电话、智能电话、会话发起协议(SIP)电话、平板计算机、平板手机、服务器、计算机、便携式计算机、移动计算设备、可穿戴计算设备、台式计算机、个人数字助理(PDA)、监控器、计算机显示器、电视、调谐器、无线电设备、卫星无线电设备、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(DVD)播放器、便携式数字视频播放器、机动车、交通工具组件、航空电子系统、无人机和多轴线飞行器。
17.一种制造集成电路(IC)封装的方法，包括：
制造包括至少一个第一互连层的第一金属化结构：
制造包括至少一个第二互连层的第二金属化结构；
制造被布置在所述第一金属化结构与所述第二金属化结构之间的IC裸片模块，包括：
提供包括第一有源表面和第一非有源表面的第一IC裸片；
提供包括第二有源表面和第二非有源表面的第二IC裸片；以及
将所述第一IC裸片的所述第一非有源表面压缩结合到所述第二IC裸片的所述第二非有源表面，以将所述第一IC裸片耦合到所述第二IC裸片；
将所述第一IC裸片的所述第一有源表面电耦合到所述第一金属化结构的所述至少一个第一互连层；以及
将所述第二IC裸片的所述第二有源表面电耦合到所述第二金属化结构的所述至少一个第二互连层。
18.根据权利要求17所述的方法，其中将所述第一IC裸片的所述第一非有源表面压缩结合到所述第二IC裸片的所述第二非有源表面包括：
在所述第一IC裸片的所述第一非有源表面上布置第一氧化物层；
在所述第二IC裸片的所述第二非有源表面上布置第二氧化物层；以及
将所述第一非有源表面上的所述第一氧化物层压缩到所述第二非有源表面上的所述第二氧化物层。
19.根据权利要求18所述的方法，其中将所述第一非有源表面压缩结合到所述第二非有源表面还包括：在将所述第一非有源表面上的所述第一氧化物层压缩到所述第二非有源表面上的所述第二氧化物层之前：
将所述第一氧化物层的温度升高到150摄氏度至180摄氏度之间；以及
将所述第二氧化物层的温度升高到150摄氏度至180摄氏度之间。
20.根据权利要求17所述的方法，其中将所述第一非有源表面压缩结合到所述第二非有源表面包括：
在所述第一IC裸片的所述第一有源表面上形成第一临时结合膜；
将第一载体安装在所述第一临时结合膜上；
在所述第二IC裸片的所述第二有源表面上形成第二临时结合膜；
将第二载体安装在所述第二临时结合膜上；以及
将所述第一IC裸片的所述第一非有源表面压缩到所述第二IC裸片的所述第二非有源表面。
21.根据权利要求17所述的方法，其中：
将所述第一IC裸片的所述第一有源表面电耦合到所述第一金属化结构的所述至少一个第一互连层还包括：将所述第一IC裸片的所述第一有源表面压缩结合到所述第一金属化结构；并且
将所述第一IC裸片的所述第二有源表面电耦合到所述第一金属化结构的所述至少一个第二互连层还包括：将所述第二IC裸片的所述第二有源表面压缩结合到所述第二金属化结构。
22.根据权利要求21所述的方法，还包括：
在将所述第一IC裸片的所述第一有源表面压缩结合到所述第一金属化结构之前：
将所述第一金属化结构的温度升高到150摄氏度至180摄氏度之间；以及
在将所述第二IC裸片的所述第二有源表面压缩结合到所述第二金属化结构之前：
将所述第二金属化结构的温度升高到150摄氏度至180摄氏度之间。
23.根据权利要求17所述的方法，其中制造所述IC裸片模块还包括：在所述第一金属化结构上与所述第一IC裸片邻近地布置电气组件。
24.根据权利要求17所述的方法，其中制造所述IC裸片模块还包括在所述第一IC裸片和所述第二IC裸片之上布置模制材料。
25.根据权利要求23所述的方法，还包括形成与所述第一金属化结构的所述至少一个第一互连层电接触的一个或多个焊球。
CN202180040282.6A 2020-06-24 2021-05-24 采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法 Pending CN115699307A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/910,486 US11456291B2 (en) 2020-06-24 2020-06-24 Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
US16/910,486 2020-06-24
PCT/US2021/033915 WO2021262368A1 (en) 2020-06-24 2021-05-24 Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods

Publications (1)

Publication Number Publication Date
CN115699307A true CN115699307A (zh) 2023-02-03

Family

ID=76641770

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180040282.6A Pending CN115699307A (zh) 2020-06-24 2021-05-24 采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法

Country Status (8)

Country Link
US (1) US11456291B2 (zh)
EP (1) EP4173038A1 (zh)
JP (1) JP7391247B2 (zh)
KR (1) KR102598381B1 (zh)
CN (1) CN115699307A (zh)
BR (1) BR112022025594A2 (zh)
TW (1) TW202201575A (zh)
WO (1) WO2021262368A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230317677A1 (en) * 2022-04-04 2023-10-05 Qualcomm Incorporated Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
CN103296014A (zh) * 2012-02-28 2013-09-11 刘胜 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN104871309A (zh) * 2012-12-21 2015-08-26 斯兰纳半导体美国股份有限公司 背靠背堆叠集成电路组合件以及制作方法
CN107408547A (zh) * 2015-03-03 2017-11-28 苹果公司 扇出型系统级封装件及其形成方法
CN110998837A (zh) * 2017-08-23 2020-04-10 美光科技公司 用于改善堆叠式半导体装置中电力递送及发信的方法及系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001018864A1 (fr) 1999-09-03 2001-03-15 Seiko Epson Corporation Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique
US20020074652A1 (en) 2000-12-15 2002-06-20 Pierce John L. Method, apparatus and system for multiple chip assemblies
JP2003234451A (ja) * 2002-02-06 2003-08-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN102063584B (zh) 2006-01-24 2012-12-05 Nds有限公司 芯片攻击保护
US9818680B2 (en) 2011-07-27 2017-11-14 Broadpak Corporation Scalable semiconductor interposer integration
US8105915B2 (en) * 2009-06-12 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers
JP2011165032A (ja) 2010-02-12 2011-08-25 Buffalo Inc コンピュータプログラム及びデータバックアップ方法
MY178559A (en) 2014-07-07 2020-10-16 Intel Corp Package-on-package stacked microelectronic structures
US9941207B2 (en) 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US10636773B2 (en) * 2015-09-23 2020-04-28 Mediatek Inc. Semiconductor package structure and method for forming the same
CN109103167B (zh) 2017-06-20 2020-11-03 晟碟半导体（上海）有限公司 用于存储器装置的异构性扇出结构
KR102071457B1 (ko) 2018-03-13 2020-01-30 삼성전자주식회사 팬-아웃 반도체 패키지
US20210280523A1 (en) 2020-03-04 2021-09-09 Qualcomm Incorporated Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
CN103296014A (zh) * 2012-02-28 2013-09-11 刘胜 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN104871309A (zh) * 2012-12-21 2015-08-26 斯兰纳半导体美国股份有限公司 背靠背堆叠集成电路组合件以及制作方法
CN107408547A (zh) * 2015-03-03 2017-11-28 苹果公司 扇出型系统级封装件及其形成方法
CN110998837A (zh) * 2017-08-23 2020-04-10 美光科技公司 用于改善堆叠式半导体装置中电力递送及发信的方法及系统

Also Published As

Publication number Publication date
WO2021262368A1 (en) 2021-12-30
KR20230011422A (ko) 2023-01-20
EP4173038A1 (en) 2023-05-03
WO2021262368A4 (en) 2022-02-03
TW202201575A (zh) 2022-01-01
US11456291B2 (en) 2022-09-27
JP7391247B2 (ja) 2023-12-04
BR112022025594A2 (pt) 2023-01-03
KR102598381B1 (ko) 2023-11-06
US20210407979A1 (en) 2021-12-30
JP2023524170A (ja) 2023-06-08

Similar Documents

Publication Publication Date Title
US20210280523A1 (en) Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die (&#34;die&#34;) module employing stacked dice, and related fabrication methods
KR102643781B1 (ko) 3차원(3d) 다이 적층을 위한 fs-beol 대 bs-beol 적층을 채용하는 집적 회로(ic) 패키지들 및 관련 제조 방법들
TW202306094A (zh) 在晶粒－基板支起腔中採用晶粒到晶粒（ｄ２ｄ）連接的拆分式晶粒積體電路（ｉｃ）封裝及相關製造方法
KR102598381B1 (ko) 적층된 다이들을 이용하는 반도체 다이(die) 모듈을 용이하게 하기 위해 분할된 양면 금속화 구조물들을 이용하는 집적 회로(ic) 패키지들, 및 그의 제조 방법들
TW202318609A (zh) 具有用於積體電路（ｉｃ）封裝高度控制的具有多種厚度的嵌入式金屬跡線的嵌入式跡線基板（ｅｔｓ）
TW202329347A (zh) 採用具有雙面嵌入式跡線基板（ｅｔｓ）的封裝基板的積體電路（ｉｃ）封裝以及相關製造方法
CN117957654A (zh) 用于支持较高连接密度的多管芯集成电路封装及相关制造方法
US20230299048A1 (en) Three-dimensional (3d) integrated circuit (ic) (3dic) package with a bottom die layer employing an extended interposer substrate, and related fabrication methods
US11769732B2 (en) Integrated circuit (IC) with reconstituted die interposer for improved connectivity, and related methods of fabrication
US20230059431A1 (en) Stacked die integrated circuit (ic) package employing interposer for coupling an upper stacked die(s) to a package substrate for package height reduction, and related fabrication methods
US20230317677A1 (en) Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods
US20230268637A1 (en) Antenna modules employing three-dimensional (3d) build-up on mold package to support efficient integration of radio-frequency (rf) circuitry, and related fabrication methods
TW202406042A (zh) 在封裝基板之上採用引線接合通道的積體電路（ｉｃ）封裝及相關製造方法
CN118056277A (zh) 采用耦合到管芯侧嵌入式迹线基板（ets）层中的嵌入式金属迹线的补充金属层的集成电路（ic）封装以及相关的制造方法
TW202228214A (zh) 具有基板上嵌入式跡線基板（ｅｔｓ）層的積體電路（ｉｃ）封裝基板以及相關製造方法
TW202312416A (zh) 在封裝基板中的（諸）金屬結構中具有空隙定義區段以減小晶粒－基板機械應力的半導體晶粒模組封裝以及相關方法
TW202213551A (zh) 具有堆疊晶粒引線鍵合連接的積體電路（ｉｃ）封裝及相關方法
CN117999648A (zh) 采用填充金属用于基于ets的基板中的嵌入式金属迹线以降低信号路径阻抗的集成电路（ic）封装件和相关制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination