BR112022025594A2 - Pacotes de circuito integrado (ic) que empregam estruturas de metalização de dois lados divididas para facilitar um módulo de matriz semicondutora ("matriz") empregando dados empilhados,e métodos de fabricação relacionados - Google Patents
Pacotes de circuito integrado (ic) que empregam estruturas de metalização de dois lados divididas para facilitar um módulo de matriz semicondutora ("matriz") empregando dados empilhados,e métodos de fabricação relacionadosInfo
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- BR112022025594A2 BR112022025594A2 BR112022025594A BR112022025594A BR112022025594A2 BR 112022025594 A2 BR112022025594 A2 BR 112022025594A2 BR 112022025594 A BR112022025594 A BR 112022025594A BR 112022025594 A BR112022025594 A BR 112022025594A BR 112022025594 A2 BR112022025594 A2 BR 112022025594A2
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
PACOTES DE CIRCUITO INTEGRADO (IC) QUE EMPREGAM ESTRUTURAS DE METALIZAÇÃO DE DOIS LADOS DIVIDIDAS PARA FACILITAR UM MÓDULO DE MATRIZ SEMICONDUTORA ("MATRIZ") EMPREGANDO DADOS EMPILHADOS,E MÉTODOS DE FABRICAÇÃO RELACIONADOS. São divulgados pacotes de circuitos integrados (IC) que empregam estruturas de metalização de IC de dois lados divididas para facilitar um módulo de matriz semicondutora empregando dados empilhados e métodos de fabricação relacionados. Múltiplos dados IC no pacote IC são empilhados e unidos em uma configuração de matriz IC back-to-back, superior e inferior em um módulo de matriz IC, o que pode minimizar a altura do pacote IC. A estrutura de metalização é dividida entre estruturas de metalização superior e inferior separadas adjacentes às respectivas superfícies superior e inferior do módulo de matriz IC para facilitar conexões elétricas externas e die-to-die aos dados. As estruturas de metalização superior e inferior podem ser de dois lados expondo as interconexões do substrato nas respectivas superfícies interna e externa para as respectivas matrizes e interconexões elétricas externas. Em outros aspectos, uma ligação por compressão é incluída entre os dados IC montados juntos em uma configuração back-to-back para minimizar ainda mais a altura total do pacote IC.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US16/910,486 US11456291B2 (en) | 2020-06-24 | 2020-06-24 | Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods |
PCT/US2021/033915 WO2021262368A1 (en) | 2020-06-24 | 2021-05-24 | Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods |
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BR112022025594A2 true BR112022025594A2 (pt) | 2023-01-03 |
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BR112022025594A BR112022025594A2 (pt) | 2020-06-24 | 2021-05-24 | Pacotes de circuito integrado (ic) que empregam estruturas de metalização de dois lados divididas para facilitar um módulo de matriz semicondutora ("matriz") empregando dados empilhados,e métodos de fabricação relacionados |
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US (1) | US11456291B2 (pt) |
EP (1) | EP4173038A1 (pt) |
JP (1) | JP7391247B2 (pt) |
KR (1) | KR102598381B1 (pt) |
CN (1) | CN115699307A (pt) |
BR (1) | BR112022025594A2 (pt) |
TW (1) | TW202201575A (pt) |
WO (1) | WO2021262368A1 (pt) |
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US20230290700A1 (en) * | 2022-03-08 | 2023-09-14 | Mediatek Inc. | Antenna package |
US20230317677A1 (en) * | 2022-04-04 | 2023-10-05 | Qualcomm Incorporated | Three-dimensional (3d) integrated circuit (ic) (3dic) package employing a redistribution layer (rdl) interposer facilitating semiconductor die stacking, and related fabrication methods |
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KR100533673B1 (ko) | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 |
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JP2003234451A (ja) | 2002-02-06 | 2003-08-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6590282B1 (en) * | 2002-04-12 | 2003-07-08 | Industrial Technology Research Institute | Stacked semiconductor package formed on a substrate and method for fabrication |
CN102063584B (zh) | 2006-01-24 | 2012-12-05 | Nds有限公司 | 芯片攻击保护 |
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JP2011165032A (ja) | 2010-02-12 | 2011-08-25 | Buffalo Inc | コンピュータプログラム及びデータバックアップ方法 |
CN103296014A (zh) * | 2012-02-28 | 2013-09-11 | 刘胜 | 扇出晶圆级半导体芯片三维堆叠封装结构及工艺 |
MY178559A (en) | 2014-07-07 | 2020-10-16 | Intel Corp | Package-on-package stacked microelectronic structures |
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US10636773B2 (en) * | 2015-09-23 | 2020-04-28 | Mediatek Inc. | Semiconductor package structure and method for forming the same |
CN109103167B (zh) | 2017-06-20 | 2020-11-03 | 晟碟半导体(上海)有限公司 | 用于存储器装置的异构性扇出结构 |
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- 2020-06-24 US US16/910,486 patent/US11456291B2/en active Active
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2021
- 2021-05-20 TW TW110118241A patent/TW202201575A/zh unknown
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EP4173038A1 (en) | 2023-05-03 |
CN115699307A (zh) | 2023-02-03 |
TW202201575A (zh) | 2022-01-01 |
KR102598381B1 (ko) | 2023-11-06 |
US11456291B2 (en) | 2022-09-27 |
WO2021262368A4 (en) | 2022-02-03 |
JP2023524170A (ja) | 2023-06-08 |
WO2021262368A1 (en) | 2021-12-30 |
JP7391247B2 (ja) | 2023-12-04 |
US20210407979A1 (en) | 2021-12-30 |
KR20230011422A (ko) | 2023-01-20 |
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