CN110998837A - 用于改善堆叠式半导体装置中电力递送及发信的方法及系统 - Google Patents

用于改善堆叠式半导体装置中电力递送及发信的方法及系统 Download PDF

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CN110998837A
CN110998837A CN201880054639.4A CN201880054639A CN110998837A CN 110998837 A CN110998837 A CN 110998837A CN 201880054639 A CN201880054639 A CN 201880054639A CN 110998837 A CN110998837 A CN 110998837A
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semiconductor die
capacitor
metallization
plate
semiconductor
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A·D·韦切斯
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Micron Technology Inc
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Micron Technology Inc
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Priority to CN202210531910.7A priority Critical patent/CN114937657A/zh
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Abstract

本文中揭示包含堆叠式半导体裸片的半导体裸片组合件以及相关联的系统及方法，所述堆叠式半导体裸片具有形成于所述堆叠中的邻近对的半导体裸片之间的平行板电容器。在一个实施例中，半导体裸片组合件包含第一半导体裸片及堆叠于所述第一半导体裸片上方的第二半导体裸片。所述第一半导体裸片包含上面形成有第一电容器板的上部表面，且所述第二半导体裸片包含面向所述第一半导体裸片的所述上部表面且上面形成有第二电容器板的下部表面。介电材料至少部分地形成于所述第一与第二电容器板之间。所述第一电容器板、第二电容器板及介电材料一起形成电容器，所述电容器在所述堆叠内局部地存储电荷且可由所述第一及/或第二半导体裸片存取。

Description

用于改善堆叠式半导体装置中电力递送及发信的方法及系统
技术领域
本发明技术大体来说涉及堆叠式半导体装置。本发明技术的数个实施例涉及通过在堆叠中的邻近的半导体裸片之间形成电容器来改善到堆叠式半导体装置的电力递送。
背景技术
微电子装置(例如存储器装置、微处理器及发光二极管)通常包含安装到衬底且包封于保护性覆盖物中的一或多个半导体裸片。半导体裸片包含功能特征，例如存储器单元、处理器电路、互连电路等。半导体裸片制造商面临减小由半导体裸片占据的体积而增加容量及/或所产生囊封组合件的速度的日益增加的压力。为满足这些需求，半导体裸片制造商通常将多个半导体裸片彼此垂直地上下堆叠以在半导体裸片所安装到的电路板或其它元件上的有限体积内增加微电子装置的容量或性能。在一些半导体裸片堆叠中，使用穿硅通孔(TSV)电互连半导体裸片。TSV使半导体裸片能够彼此接近地堆叠使得邻近的半导体裸片彼此间隔开仅相对小的垂直距离。这连同TSV的相对低电感一起实现较高数据传送速率。并且，由于裸片是垂直堆叠的，因此堆叠的总占据面积对应于堆叠中最大裸片的占据面积。
然而，半导体裸片堆叠的一个问题是电力递送。举例来说，当半导体裸片执行高电力操作时，从堆叠中的半导体裸片汲取的电流可为巨大的，这可导致到(举例来说)堆叠中的最上部半导体裸片的不良电力递送。用于改善半导体裸片堆叠中的电力递送的常规方法包含增加堆叠中的每一半导体裸片的TSV计数以减小电力网络的电阻。然而，增加半导体裸片的TSV计数通常需要增加半导体裸片的大小。因此，此项技术中仍需要用于改善半导体裸片堆叠中的电力递送的方法及系统。
附图说明
图1是根据本发明技术的实施例的半导体裸片组合件的横截面图。
图2A及2B分别是根据本发明技术的实施例配置的半导体裸片的俯视平面图及仰视平面图。
图3A及3B分别是根据本发明技术的另一实施例配置的半导体裸片的俯视平面图及仰视平面图。
图4A到4C是图解说明根据本发明技术的实施例处于各种制造阶段处的半导体裸片的横截面图。
图5是包含根据本发明技术的实施例配置的半导体裸片组合件的系统的示意图。
具体实施方式
下文描述半导体裸片及半导体裸片组合件的数个实施例的特定细节。在下文所描述的数个实施例中，半导体裸片组合件包含半导体裸片堆叠，所述半导体裸片堆叠具有形成于堆叠中的每一邻近对的半导体裸片之间的电容器。在一些实施例中，所述电容器是平行板电容器，所述平行板电容器包含：(a)上部板，其形成于每一邻近对的半导体裸片中的上部者的下部表面上；(b)下部板，其形成于每一邻近对中的下部者的上部表面上；及(c)介电材料，其位于所述上部板与所述下部板之间。平行板电容器可在半导体裸片堆叠内局部地存储电荷。当个别半导体裸片对电力具有其需求尖峰时，个别半导体裸片可从平行板电容器中的一或多者吸引电力以解决所述需求。此外，在某些实施例中，平行板电容器的板可在不给制造工艺添加大量成本或复杂性的情况下作为用于在堆叠式半导体裸片之间形成互连件的现有金属化工艺的一部分而形成。
如本文中所使用，术语“垂直”、“横向”、“上部”及“下部”可指鉴于图中所展示的定向的本文中所描述的半导体裸片及半导体裸片组合件中的特征的相对方向或位置。举例来说，“上部”或“最上部”可指定位为比另一特征更接近于页的顶部的特征。然而，这些术语应广泛地解释为包含具有其它定向(例如翻转或倾斜定向，其中顶部/底部、上方/下方、上面/下面、上/下及左/右可取决于定向而互换)的半导体裸片及半导体裸片组合件。
图1是图解说明根据本发明技术的实施例配置的半导体裸片组合件100(“组合件100”)的横截面图。组合件100包含由封装衬底120承载的半导体裸片110的堆叠105。封装衬底120可包含中介层、印刷电路板、介电间隔件、另一半导体裸片(例如，逻辑裸片)或另一适合衬底。封装衬底120连接到电连接器122(例如，焊料球)，电连接器122将组合件100电耦合到外部电路(未展示)。在一些实施例中，组合件100可在封装衬底120与半导体裸片110中的最下部者之间包含中介层、另一逻辑裸片或其它适合结构。
半导体裸片110可各自具有集成电路或组件、数据存储元件、处理组件及/或制造于半导体衬底上的其它特征。举例来说，半导体裸片110可包含集成存储器电路及/或逻辑电路，所述集成存储器电路及/或逻辑电路可包含各种类型的半导体组件及功能特征，例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件及/或其它半导体特征。在一些实施例中，半导体裸片110可为完全相同的(例如，经制造为具有相同设计及规范的存储器裸片)，但在其它实施例中，半导体裸片110可彼此不同(例如，不同类型的存储器裸片或控制器、逻辑及/或存储器裸片的组合)。此外，尽管组合件100包含堆叠于封装衬底120上的四个半导体裸片110，但在其它实施例中组合件100可包含少于四个半导体裸片(例如，两个裸片或三个裸片)或多于四个裸片(例如，五个裸片，六个裸片、八个裸片、12个裸片、16个裸片、32个裸片等)。
如图1中进一步展示，半导体裸片110各自具有上部表面113a及与上部表面113a相对的下部表面113b(统称为“表面113a、113b”)。半导体裸片110中的一些半导体裸片可进一步包含至少基本上延伸穿过半导体裸片110(例如，穿过其半导体衬底)的多个通孔112(例如，穿硅通孔(TSV))。在一些实施例中，每一通孔112包含完全穿过个别半导体裸片110的导电材料(例如，铜)，及环绕所述导电材料以将通孔112与半导体裸片110的其余部分电隔离的电绝缘材料。更特定来说，通孔112可完全延伸穿过半导体裸片110使得每一通孔112的上部部分在个别半导体裸片110的上部表面113a处暴露出，且通孔112的下部部分在个别半导体裸片110的下部表面113b处暴露出。以此方式，通孔112经配置以用于机械连接及/或电连接到105中的其它半导体裸片110及/或封装衬底120。如图1的实施例中所图解说明，堆叠105中的最上部半导体裸片110可不具备通孔，这是因为经由最上部半导体裸片110的电连接(例如，在最上部半导体裸片110的上部表面113a处)可并非是必要的。在其它实施例中，最上部半导体裸片110也可包含多个通孔112，(举例来说)以准许将最上部半导体裸片110电耦合到最上部半导体裸片110的上部表面113a处的其它电路(例如，额外半导体裸片、较高层级电路等)。在又一些实施例中，可在不使用TSV的情况下使用所属领域的技术人员众所周知的其它互连方法(包含例如搭叠式线接合、面对面互连等)将半导体裸片110电耦合在一起。
组合件100进一步包含在堆叠105中的邻近的半导体裸片110之间延伸且电耦合堆叠105中的邻近的半导体裸片110的多个导电互连件130。互连件130可各自包含上部金属化特征132、下部金属化特征134及耦合上部金属化特征132及下部金属化特征134(统称为“金属化特征132、134”)的导电元件136。导电元件136可包括焊料材料，举例来说锡银、铟或用于在邻近的半导体裸片110上的金属化特征132、134之间形成电连接及机械连接的另一适合焊料材料。在其它实施例中，导电元件136可由其它适合材料制成及/或具有不同结构(例如，铜柱、氮化物结构上凸块等)。
大体来说，金属化特征132、134可为如此项技术中已知的任何适合凸块下金属(UBM)结构且电耦合到半导体裸片110的通孔112中的对应者。上部金属化特征132形成于堆叠105中的一对邻近的半导体裸片110中的上部半导体裸片110的下部表面113b上。类似地，下部金属化特征134形成于所述对邻近的半导体裸片中的下部半导体裸片110的上部表面113a上。更特定来说，如图1中所展示，上部金属化特征132可形成于通孔112在所述对邻近的半导体裸片中的上部半导体裸片110的下部表面113b处暴露出的下部部分上方。同样地，下部金属化特征134可形成于通孔112在所述对邻近的半导体裸片中的下部半导体裸片110的上部表面113a处暴露出的上部部分上方。因此，互连件130(即，上部金属化特征132、导电元件及下部金属化特征134)可与所述对邻近的半导体裸片中的一对通孔112轴向对准且电耦合所述对通孔。然而，在其它实施例中，互连件130不必与通孔112轴向对准。举例来说，所述对邻近的半导体裸片中的下部及/或上部半导体裸片110上的重布层(RDL)或其它导电结构可提供邻近的半导体裸片的通孔112与金属化特征132、134之间的不同对准及耦合。
金属化特征132、134可包括例如铜、镍、金、硅、钨等适合导电材料中的任一者或组合，且可具有约1微米到100微米之间(例如，小于约10微米)的厚度(例如，高度)。此外，金属化特征132、134的形状及尺寸可变化。举例来说，在一些实施例中金属化特征132、134具有基本上圆柱形横截面形状且形成柱状结构。在其它实施例中，金属化特征132、134可具有其它横截面形状，例如矩形、正多边形、不规则多边形、椭圆形等。
组合件100进一步包含多个上部电容器板142及多个下部电容器板144(统称为“电容器板142、144”)。每一上部电容器板142形成于堆叠105中的一对邻近的半导体裸片110中的上部半导体裸片110的下部表面113b上，且每一下部电容器板144形成于所述对邻近的半导体裸片中的下部半导体裸片110的上部表面113a上。如图1的实施例中所图解说明，每一上部电容器板142面向对应下部电容器板144且至少部分地与对应下部电容器板144对准。举例来说，如图1中所展示，每一上部电容器板142叠覆于邻近的下部半导体裸片110上的对应下部电容器板144上方(例如，电容器板142、144基本上围绕在邻近的半导体裸片之间延伸的平面反射对称)。电容器板142、144中的至少一者电耦合到电力供应器而另一者电耦合到接地。举例来说(如图2A及2B中所展示)，电容器板142、144可各自经由形成于半导体裸片110的表面113a、113b上的导电迹线电耦合到互连件130中的一或多者，从而提供电力或接地信号。在其它实施例中，电容器板142、144可使用其它适合电连接器(例如线接合)电耦合到电力供应器或接地。因此，可在形成于堆叠105中的每一对邻近的半导体裸片110之间的对置电容器板142、144之间提供电压差。
如下文参考图4A到4C进一步详细描述，电容器板142、144可作为用于形成金属化特征132、134的金属化工艺的扩展(例如，在相同处理阶段处及/或同时)而形成。因此，由于金属化特征132、134及电容器板142、144可由相同工艺形成，其等的特性中的至少一些特性可为相同的或基本上类似的。举例来说，金属化特征132、134可分别具有与电容器板142、144相同或基本上类似的厚度。类似地，金属化特征132、134可包括与电容器板142、144相同的材料(例如，铜、镍、金、硅、钨等)。
组合件100可进一步包含围绕半导体裸片110、互连件130及电容器板142、144及/或在半导体裸片110、互连件130及电容器板142、144之间沉积或以其它方式形成以电隔离这些组件及/或增强堆叠105中的半导体裸片110之间的机械连接的介电材料150。介电材料150可为非导电环氧树脂膏、毛细管底部填充物、非导电膜、模制底部填充物及/或包含其它适合电绝缘材料。
总之，每一对对置电容器板142、144及其间的介电材料150形成堆叠中电容器(例如，平行板电容器)，所述堆叠中电容器存储堆叠105内的电荷。存储于每一平行板电容器上的电荷与电容器的电容(C)成比例，C＝k∈0A/d，其中“k”是板之间的介电材料的相对介电常数，“∈0”是真空介电常数，“A”是电容器板的面积且“d”是电容器板之间的间隔。在一些实施例中，在组合件100中形成的堆叠中电容器各自具有10到100微微法拉(例如，多于约100微微法拉)的电容。此外，由于电容(及因此由电容器存储的电荷)与电容器板142、144之间的距离成反比，因此电容可随着堆叠105中的半导体裸片110之间的垂直距离(例如，间隔)减小而增加。堆叠105中的半导体裸片110之间的间隔很大程度上取决于互连件130的大小。因此，随着技术发展到减小互连件130的大小且借此减小组合件100的总高度，本文中所描述的堆叠中电容器的电容可相应地增加。此外，在一些实施例中，可基于介电材料150的介电质量(例如，其相对介电常数或其它特性)来选择介电材料150以便增加堆叠中电容器的电容。
大体来说，堆叠105中的每一堆叠中电容器给堆叠105的电力网络添加电容，在需要时所述电容可由半导体裸片110汲取出。举例来说，当堆叠105中的个别半导体裸片110对电力具有其需求尖峰时(例如，当个别半导体裸片110执行电力密集型操作(例如起始存取、读取操作等)时)，个别半导体裸片110可从堆叠中电容器中的一或多者汲取其所需求电力中的一些电力。堆叠中电容器提供比更局部化的电源，所述外部电力供应器的电力必须路由通过封装衬底120且向上通过通孔112及互连件130。因此，堆叠中电容器可快速地解决半导体裸片110的一些短期电力需求，电力供应器对所述短期电力需求的响应可为缓慢的，这取决于堆叠105中的其它半导体裸片110(例如，堆叠中的下部半导体裸片)的电力需求。用以改善半导体裸片堆叠的电力递送的常规方法会增加堆叠中的每一半导体裸片的TSV计数以包含较多电力及接地连接来借此减小电力网络的电阻。然而，增加半导体裸片的TSV计数需要增加半导体裸片的大小。本发明技术有利地在不增加TSV计数及/或半导体裸片110的大小的情况下增加组合件100中的电力网络的电容，使得组合件100可较佳地满足堆叠105中的半导体裸片110的电力需求。
此外，给电力网络添加电容可改善经由堆叠105在通孔112中的一或多者上传输的信号的信号完整性及/或半导体裸片110的性能。举例来说，堆叠中电容器可充当解耦电容器以分流原本可经由堆叠105载运(例如，由堆叠中的其它裸片导致的电压尖峰或接地反弹)且可阻碍半导体裸片110的性能的噪声。堆叠中电容器还可帮助解决电感响铃(例如，由于存储器装置中的封装自电感导致的响铃)问题。举例来说，堆叠中电容器可帮助最小化电力供应及接地连接的电感路径以借此改善半导体裸片110的性能。
如图1中所展示，堆叠中电容器形成于堆叠105中的每一对邻近的半导体裸片110之间。堆叠中电容器可并联或串联或者以其某一组合形式电耦合。然而，在一些实施例中，堆叠105可仅具备一个形成于单一对的邻近的半导体裸片110之间的堆叠中电容器或具备任何其它数目个堆叠中电容器。在一些实施例中，可通过以下操作在封装衬底120与堆叠105中的最下部半导体裸片110之间形成额外电容器：(a)在封装衬底120上提供下部电容器板144、(b)在最下部半导体裸片110的下部表面113b上提供对应上部电容器板142及(c)在下部电容器板144与上部电容器板142之间提供介电材料(例如，介电材料150)。类似地，在一些实施例中，电容器可形成于堆叠105中的最上部半导体裸片110的上部表面113a与连接到其的任何外部组件之间。
图2A及2B分别是根据本发明技术的实施例的图1中所展示的组合件100的半导体裸片110中的一者的俯视平面图及仰视平面图，其中在半导体裸片110的表面113a、113b中的每一者上具有金属化特征及电容器板。所图解说明半导体裸片110可为堆叠105的中部中的半导体裸片110中的一者(例如，在上面及下面均具有邻近的半导体裸片110)，这是因为堆叠105中的最下部半导体裸片110及最顶部半导体裸片110可分别形成为在其下部表面113b及上部表面113a上无电容器板及/或金属化特征(如图1中所图解说明)。
更特定来说，图2A图解说明具有一或多个外围区域216(例如，横向外侧区域)及中心区域218的半导体裸片110的上部表面113a。下部金属化特征134形成于外围区域216上，且下部电容器板144形成于上部表面113a的中心区域218上。下部电容器板144可经由导电迹线238(个别地展示为导电迹线238a及238b)电耦合到下部金属化特征134中的一或多者。举例来说，如图2A的实施例中所图解说明，下部电容器板144可经由导电迹线238a电耦合到第一下部金属化特征134a且经由导电迹线238b电耦合到第二下部金属化特征134b。第一下部金属化特征134a及第二下部金属化特征134b可电耦合到接地或电耦合到电力供应器。在一些实施例中，导电迹线238是作为与下部金属化特征134及下部电容器板144相同的金属化工艺的一部分而形成。
图2B图解说明具有一或多个外围区域226(例如，横向外侧区域)及中心区域228的半导体裸片110的下部表面113b。上部金属化特征132形成于外围区域226上，且上部电容器板142形成于下部表面113b的中心区域228上。上部电容器板142可经由导电迹线248(个别地展示为导电迹线248a及248b)电耦合到上部金属化特征132中的一或多者。举例来说，如图2B的实施例中所图解说明，上部电容器板142可经由导电迹线248a电耦合到第一上部金属化特征132a且经由导电迹线248b电耦合到第二上部金属化特征132b。第一上部金属化特征132a及第二上部金属化特征132b可电耦合到接地或电耦合到电力供应器。在一些实施例中，导电迹线248是作为与上部金属化特征132及上部电容器板142相同的金属化工艺的一部分而形成。
在一些实施例中，电容器板142、144可电耦合到半导体裸片110的相同通孔(图1)。因此，电容器板142、144可既电耦合到接地又电耦合到电力供应器。在此些实施例中，堆叠105中的每一交替半导体裸片110可具备电容器板142、144的相同配置使得在形成于堆叠105中的邻近对的半导体裸片110之间的对置电容器板142、144之间存在电压差。然而，在其它实施例中，半导体裸片110上的电容器板142、144可电耦合到通孔112中的不同者(例如，单独者)使得电容器板142、144中的一者电耦合到接地，而另一者电耦合到电力供应器。举例来说，在此些实施例中，堆叠105中的每一上部电容器板142可电耦合到电力供应器而每一下部电容器板144电耦合到接地。
一起参考图2A及2B两者，电容器板142、144可经形成以分别填充表面113b、113a的相当大的区，所述区未以其它方式由金属化特征132、134占据。举例来说，如图2A及2B两者中所图解说明，半导体裸片110可具有在表面113a、113b的外围区域216、226处布置成行的金属化特征132、134。通过在中心区域218、228上形成电容器板142、144且将其形成为具有矩形横截面(例如，矩形平面形状)，电容器板142、144可占据表面113a、113b的未由金属化特征132、134(其位置可限制于通孔112的位置)占据的相当大的区。举例来说，在一些实施例中，电容器板142、144可分别覆盖大于半导体裸片110的表面113a、113b的表面积的约25％的面积。在一些实施例中，电容器板142、144可覆盖大于表面113a、113b的表面积的约50％的面积。在又一些实施例中，电容器板142、144可覆盖大于表面113a、113b的表面积的约75％的面积。然而，电容器板142、144的覆盖范围不受限制且电容器板142、144可覆盖表面113a、113b的任何适合部分。此外，在某些实施例中，金属化特征132、134可形成于半导体裸片110的不同区域上且可具有不同布置。在此些实施例中，电容器板的大小、形状及定位可经选择以匹配金属化特征132、134的布局。
举例来说，图3A及3B分别是根据本发明技术的另一实施例的组合件100的半导体裸片110中的一者的俯视平面图及仰视平面图，其中在半导体裸片110的表面113a、113b上具有金属化特征与电容器板的不同布置。一起参考图3A及3B两者，金属化特征132、134分别布置成沿着表面113b、113a均匀地间隔开的行。金属化特征132、134可以此方式布置(举例来说)以匹配半导体裸片110的通孔(例如，通孔112)的布置。如图3A中所展示，下部电容器板344于形成半导体裸片110的上部表面113a上且经由导电迹线338(例如，对应于电力或接地)电耦合到下部金属化特征134中的一或多者。类似地，如图3B中所展示，上部电容器板342形成于半导体裸片110的下部表面113b上且经由导电迹线348(例如，对应于电力或接地)电耦合到上部金属化特征132中的一或多者。在一些实施例中，上部电容器板342及下部电容器板344两者均电耦合到半导体裸片110的相同通孔112(图1)(例如，使得两个板均接地或使得两个板均连接到电力供应器)，而在其它实施例中，上部电容器板342及下部电容器板344电耦合到通孔112中的不同者(例如，使得所述板中的一者接地而另一者连接到电力供应器)。此外，上部电容器板342及下部电容器板344两者均具有大体直线形状且形成于围绕金属化特征132、134的开放表面区的相当大的部分上。在给出金属化特征132、134的布局的情况下，此布置通常可允许上部电容器板342及下部电容器板344具有最大面积。
大体来说，本文中所描述的电容器板的大小、形状及定位可经选择以最大化或几乎最大化电容器板的面积，以便增加形成于裸片堆叠中的堆叠中电容器的电容。更特定来说，每一电容器板可形成于半导体裸片的开放表面区上，所述开放表面区将不会以其它方式由金属化特征占据。因此，本文中所描述的电容器板可适用于其形成于上面的半导体裸片的特定配置(例如，适用于通孔、金属化特征及/或其它特征的布置)，同时还给裸片组合件添加少许或不添加额外开销(例如，不增加裸片组合件的平面大小或厚度)。
此外，每一半导体裸片可在其表面上包含单个电容器板(如结合上文的数个实施例所描述)或在其表面上包含多于一个电容器板。举例来说，在给出现有金属化结构的情况下，如本文中所描述的半导体裸片可包含多个离散电容器板以匹配半导体裸片的表面上可用的空间。离散电容器板可为电耦合(例如，经由导电迹线)或电隔离的。在一些实施例中，邻近的半导体裸片可各自在其面向表面上具有多个离散电容器板以便在邻近的半导体裸片之间形成多个离散平行板电容器。多个平行板电容器可独立于彼此操作，或可并联连接、串联连接等。
图4A到4C是图解说明根据本发明技术的实施例制造上面形成有金属化特征及电容器板的半导体裸片的方法中的各种阶段的横截面图。在图4A到4C中所图解说明的实施例中，多个半导体裸片110可形成于衬底组合件400(例如，半导体晶片或面板)的离散区处。衬底组合件400包含半导体材料460及半导体材料460的上部侧上的介电材料462。尽管图4A到4C中仅图解说明单个半导体裸片110，但在实践中衬底组合件400通常具有数百个或甚至超过1,000个个别半导体裸片。
参考图4A，在此处理阶段处，已在半导体材料460中形成通孔112。如所属领域的技术人员将易于理解，可通过将高纵横比孔蚀刻到半导体材料460中且在一或多个沉积及/或镀敷步骤中用一或多种材料填充所述高纵横比孔来制成通孔112。举例来说，在图4A中所展示的实施例中，通孔112包含介电衬里464及介电衬里464内的导电插塞466。如图4A中进一步展示，通孔112的上部部分在半导体裸片110的上部表面113a处暴露出。
图4B图解说明在通孔112的上部部分上方形成下部金属化特征134之后且在半导体裸片110的上部表面113a上形成下部电容器板144之后的衬底组合件400。值得注意地，下部电容器板144可作为用于形成下部金属化特征134的金属化工艺的扩展而形成。金属化工艺可为此项技术中已知的任何适合金属化工艺(例如，前侧金属化或凸块下金属化工艺)。在一些实施例中，举例来说，下部金属化特征134是通过以下操作形成：将铜晶种结构沉积到介电材料462及通孔112的上部部分上、在铜晶种结构上形成具有与通孔112的上部部分对准的开口的掩模、将铜电镀到晶种结构上，及然后在铜上方镀敷一或多种其它材料以形成下部金属化特征134。下部电容器板144可通过将掩模图案调整为包含对应于下部电容器板144的所要形状、位置及大小的一或多个开口及将下部电容器板144连接到下部金属化特征134中的一或多者的任何迹线(例如，图2A中的迹线238)而作为此工艺的一部分形成。在一些实施例中，在形成下部金属化特征134及下部电容器板144(在一些实施例中，以及导电元件136)之后，使用适合湿式蚀刻移除掩模且移除晶种结构的经暴露部分以将下部金属化特征134与下部电容器板144隔离。
图4C图解说明以下操作之后的衬底组合件400：(a)将半导体材料460薄化以暴露半导体裸片110的下部表面113b及通孔112的下部部分(例如，使用背面研磨、干式蚀刻工艺、化学蚀刻工艺、化学机械抛光(CMP)等)；(b)在半导体材料460的下部侧上形成介电材料468；(c)在通孔112的下部部分上方形成上部金属化特征132；及(d)在半导体裸片110的下部表面113b上形成上部电容器板142。上部电容器板142可作为用于形成上部金属化特征132的金属化工艺的扩展而形成，所述金属化工艺可为此项技术中已知的任何适合工艺(例如，背侧金属化或凸块下金属化工艺)。在一些实施例中，用于形成下部金属化特征134及下部电容器板144的金属化工艺可为与用于形成上部金属化特征132及上部电容器板142相同的金属化工艺。在其它实施例中，所述工艺可为不同的。举例来说，不需要针对堆叠中的最上部裸片及最下部裸片执行图4A到4C中所图解说明的阶段中的至少一些阶段，所述最上部裸片及最下部裸片可形成为在至少一个表面不具有电容器板及/或金属化特征。一旦完成对衬底组合件400的处理，便可将半导体裸片110自衬底组合件400单个化且并入到裸片组合件(例如，图1中所展示的组合件100)中。
值得注意地，可在不给用于形成金属化特征132、134的现有方法添加显著额外成本或复杂性的情况下形成电容器板142、144，这是因为电容器板142、144可作为那些方法的扩展而形成。同样地，导电迹线(例如，图2A到3B中所展示的迹线238/248及338/348)也可容易地作为相同方法的一部分而形成，以用于将电容器板142、144电耦合到对应金属化特征132、134以在板之间提供适合电压差。
可将具有上文参考图1到4C所描述的特征的半导体装置中的任一者并入到无数较大及/或较复杂系统中的任何者中，所述系统的代表性实例是图5中示意性地展示的系统500。系统500可包含处理器502、存储器504(例如，SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置505及/或其它子系统或组件508。上文参考图1到4C所描述的半导体裸片组合件100及半导体裸片110可包含于图5中所展示的元件中的任何者中。所得系统500可经配置以执行各种各样的适合计算、处理、存储、感测、成像及/或其它功能中的任何者。因此，系统500的代表性实例包含(但不限于)计算机及/或其它数据处理器，例如桌上型计算机、膝上型计算机、因特网器具、手持式装置(例如，掌上型计算机、可佩戴计算机、蜂窝式或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器或可编程消费性电子器件、网络计算机及小型计算机。系统500的额外代表性实例包含灯、相机、运载工具等。关于这些及其它实例，系统500可装纳于单个单元中或跨越多个经互连单元分布(例如，通过通信网络)。因此，系统500的组件可包含本地及/或远程存储器存储装置及各种各样的适合计算机可读媒体中的任何者。
依据前述内容，将了解，虽然本文中已出于图解说明的目的而描述本发明技术的特定实施例，但可在不背离本发明的情况下做出各种修改。因此，本发明不受除所附权利要求书以外的任何限制。此外，还可在其它实施例中组合或消除在特定实施例的上下文中所描述的新技术的特定方面。此外，尽管已在本新技术的特定实施例的上下文中描述与那些实施例相关联的优点，但其它实施例也可展现此些优点且并非所有实施例均必须展现此些优点以归属于本发明技术的范围内。因此，本发明及相关联技术可囊括本文中未明确展示或描述的其它实施例。

Claims (25)

1.一种半导体裸片组合件，其包括：
第一半导体裸片，其具有下部表面及与所述下部表面相对的上部表面；
第二半导体裸片，其具有下部表面及与所述下部表面相对的上部表面，所述第二半导体裸片堆叠于所述第一半导体上方使得所述第二半导体裸片的所述下部表面面向所述第一半导体裸片的所述上部表面；及
堆叠中电容器，其具有位于所述第一半导体裸片的所述上部表面上的第一电容器板、位于所述第二半导体裸片的所述下部表面上的第二电容器板，及位于所述第一电容器板与所述第二电容器板之间的介电材料。
2.根据权利要求1所述的半导体裸片组合件，其中所述堆叠中电容器是平行板电容器。
3.根据权利要求2所述的半导体裸片组合件，其中所述平行板电容器具有大于约100pF的电容。
4.根据权利要求1所述的半导体裸片组合件，其进一步包括：
至少一个第一穿硅通孔TSV，其延伸穿过所述第一半导体裸片；
第一金属化特征，其位于所述第一半导体裸片的所述上部表面上且电耦合到所述第一TSV；及
第二金属化特征，其位于所述第二半导体裸片的所述下部表面上且电耦合到所述第一金属化特征。
5.根据权利要求4所述的半导体裸片组合件，其中所述第一金属化特征是由与所述第一电容器板相同的金属材料制成，且其中所述第二金属化特征是由与所述第二电容器板相同的金属材料制成。
6.根据权利要求4所述的半导体裸片组合件，其中所述第一金属化特征具有与所述第一电容器板基本上相同的厚度，且其中所述第二金属化特征具有与所述第二电容器板基本上相同的厚度。
7.根据权利要求4所述的半导体裸片组合件，其进一步包括延伸穿过所述第二半导体裸片的至少一个第二TSV，其中所述第二金属化特征电耦合到所述第二TSV。
8.根据权利要求7所述的半导体裸片组合件，其中所述第一TSV、所述第二TSV、所述第一金属化特征及所述第二金属化特征轴向对准。
9.根据权利要求1所述的半导体裸片组合件，其中所述第一电容器板及所述第二电容器板具有围绕在其间延伸的平面反射对称的矩形平面形状。
10.根据权利要求1所述的半导体裸片组合件，其中所述第一电容器板具有大于所述第一半导体裸片的所述上部表面的面积的约25％的表面积。
11.根据权利要求1所述的半导体裸片组合件，其进一步包括：
第三半导体裸片，其具有下部表面及与所述下部表面相对的上部表面，所述第三半导体堆叠于所述第二半导体上方使得所述第二半导体裸片的所述上部表面面向所述第三半导体裸片的所述下部表面；及
另一堆叠中电容器，其具有位于所述第二半导体裸片的所述上部表面上的第三电容器板、位于所述第三半导体裸片的所述下部表面上的第四电容器板，及位于所述第三电容器板与所述第四电容器板之间的介电材料。
12.一种半导体裸片组合件，其包括：
半导体裸片堆叠；及
在所述半导体裸片堆叠中的每一邻近对的半导体裸片之间：
多个互连件，其电耦合至少所述邻近对的半导体裸片，及
平行板电容器，其包含：上部板，所述上部板形成于所述邻近对中的上部者的下部表面上；下部板，所述下部板形成于所述邻近对中的下部者的上部表面上；及介电材料，其位于所述上部板与所述下部板之间。
13.根据权利要求12所述的半导体裸片组合件，其中所述上部板电耦合到电力供应器，且其中所述下部板电耦合到接地。
14.根据权利要求12所述的半导体裸片组合件，其中每一上部板电耦合到所述互连件中的至少第一者，且其中每一下部板电耦合到所述互连件中的至少第二者。
15.根据权利要求12所述的半导体裸片组合件，其中每一互连件包含：上部金属化特征，所述上部金属化特征形成于所述邻近对中的所述上部者的所述下部表面上；及下部金属化特征，所述下部金属化特征形成于所述邻近对中的所述下部者的所述上部表面上。
16.根据权利要求15所述的半导体裸片组合件，其中所述上部金属化特征是由与所述上部板相同的材料制成，且其中所述下部金属化特征是由与所述下部板相同的材料制成。
17.根据权利要求15所述的半导体裸片组合件，其中：
所述上部金属化特征形成于所述邻近对中的所述上部者的所述下部表面的外围区域上，且所述上部板形成于所述邻近对中的所述上部者的所述下部表面的中心区域上，且
所述下部金属化特征形成于所述邻近对中的所述下部者的所述上部表面的外围区域上，且所述下部板形成于所述邻近对中的所述下部者的所述上部表面的中心区域上。
18.根据权利要求15所述的半导体裸片组合件，其中每一互连件的所述上部金属化特征与所述互连件的所述下部金属化特征对准，且其中每一互连件进一步包括将所述上部金属化特征耦合到所述下部金属化特征的焊料球或焊料凸块。
19.根据权利要求12所述的半导体裸片组合件，其中每一个别半导体裸片经由所述互连件电耦合到所述平行板电容器及所述电力供应器中的至少一者，且其中所述至少一个平行板电容器提供比所述电力供应器更接近于所述个别半导体裸片的电源。
20.根据权利要求12所述的半导体裸片组合件，其包含至少八个半导体裸片。
21.一种制造半导体裸片组合件的方法，其包括：
在第一半导体裸片的表面上形成多个第一金属化特征，所述第一金属化特征电耦合到延伸穿过所述第一半导体裸片的穿硅通孔TSV；
在形成所述多个第一金属化特征的同时，在所述第一半导体裸片的所述表面上形成第一电容器板，所述第一电容器板电耦合到所述第一金属化特征中的至少一者；
在第二半导体裸片的表面上形成多个第二金属化特征；
在形成所述多个第二金属化特征的同时，在所述第二半导体裸片的所述表面上形成第二电容器板，所述第二电容器板电耦合到所述第二金属化特征中的至少一者；
将所述第二半导体裸片堆叠于所述第一半导体上方使得所述第二电容器板的至少一部分位于所述第一电容器板上方；及
至少部分地在所述第一电容器板与所述第二电容器板之间形成介电材料。
22.根据权利要求21所述的方法，其进一步包括经由安置于所述第一金属化特征与所述第二金属化特征之间的多个电连接器将所述第一金属化特征电耦合到所述第二金属化特征，其中所述电连接器是焊料球或焊料接头中的至少一者。
23.根据权利要求21所述的方法，其中：
所述第一半导体裸片的所述表面包含第一部分及第二部分，所述第一金属化特征形成于所述第一半导体裸片的所述表面的所述第一部分上，且所述第一电容器板形成于所述第一半导体裸片的所述表面的基本上全部的所述第二部分上；且
所述第二半导体裸片的所述表面包含第一部分及第二部分，所述第二金属化特征形成于所述第二半导体裸片的所述表面的所述第一部分上，且所述第二电容器板形成于所述第二半导体裸片的所述表面的基本上全部的所述第二部分上。
24.一种制造半导体裸片组合件的方法，其包括：
提供第一半导体裸片，所述第一半导体裸片具有形成于所述第一半导体裸片的表面上的第一金属结构；
在所述第一半导体裸片上方堆叠第二半导体裸片使得形成于所述第二半导体裸片的表面上的第二金属结构至少部分地与所述第一金属结构对准；及
至少部分地在所述第一金属结构与所述第二金属结构之间形成介电材料，其中所述第一金属结构、所述第二金属结构及所述介电材料一起形成平行板电容器。
25.根据权利要求24所述的方法，其进一步包括：
在所述第一半导体裸片与所述第二半导体裸片之间形成多个互连件，其中每一互连件包含形成于所述第一半导体裸片的所述表面上的第一金属化特征及形成于所述第二半导体裸片的所述表面上的第二金属化特征，其中所述第一金属化特征与第二金属化特征轴向对准且经由安置于其间的电连接器而电耦合，其中所述第一金属化特征与所述第一金属结构是由相同材料制成，且其中所述第二金属化特征与所述第二金属结构是由相同材料制成。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115699307A (zh) * 2020-06-24 2023-02-03 高通股份有限公司 采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法
CN116259620A (zh) * 2022-08-09 2023-06-13 中国科学院自动化研究所 一种无线互连装置及系统

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10134712B1 (en) 2017-08-23 2018-11-20 Micron Technology, Inc. Methods and systems for improving power delivery and signaling in stacked semiconductor devices
CN110945652A (zh) * 2019-04-15 2020-03-31 长江存储科技有限责任公司 堆叠三维异质存储器件及其形成方法
KR20220028741A (ko) * 2020-08-31 2022-03-08 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
CN112166501B (zh) * 2020-09-02 2024-01-09 长江存储科技有限责任公司 半导体器件中的片上电容器结构
US11552055B2 (en) * 2020-11-20 2023-01-10 Qualcomm Incorporated Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116558A1 (en) * 2006-11-21 2008-05-22 Samsung Electronics Co., Ltd. Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package
TW201037812A (en) * 2008-12-17 2010-10-16 Qualcomm Inc Stacked die parallel plate capacitor
US20130087887A1 (en) * 2010-02-03 2013-04-11 SK Hynix Inc. Stack package
US8697567B2 (en) * 2012-05-22 2014-04-15 International Business Machines Corporation Implementing decoupling devices inside a TSV DRAM stack
WO2017058422A1 (en) * 2015-09-28 2017-04-06 Invensas Corporation Capacitive coupling of integrated circuit die components

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611419B1 (en) * 2000-07-31 2003-08-26 Intel Corporation Electronic assembly comprising substrate with embedded capacitors
US8247288B2 (en) * 2009-07-31 2012-08-21 Alpha & Omega Semiconductor Inc. Method of integrating a MOSFET with a capacitor
KR20120068216A (ko) 2010-12-17 2012-06-27 에스케이하이닉스 주식회사 반도체 집적회로
JP5947387B2 (ja) 2011-09-30 2016-07-06 インテル・コーポレーション ３ｄ集積回路積層体の層間通信
US9502336B2 (en) * 2013-03-13 2016-11-22 Intel Corporation Coreless substrate with passive device pads
US10134712B1 (en) * 2017-08-23 2018-11-20 Micron Technology, Inc. Methods and systems for improving power delivery and signaling in stacked semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116558A1 (en) * 2006-11-21 2008-05-22 Samsung Electronics Co., Ltd. Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package
TW201037812A (en) * 2008-12-17 2010-10-16 Qualcomm Inc Stacked die parallel plate capacitor
US20130087887A1 (en) * 2010-02-03 2013-04-11 SK Hynix Inc. Stack package
US8697567B2 (en) * 2012-05-22 2014-04-15 International Business Machines Corporation Implementing decoupling devices inside a TSV DRAM stack
WO2017058422A1 (en) * 2015-09-28 2017-04-06 Invensas Corporation Capacitive coupling of integrated circuit die components

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115699307A (zh) * 2020-06-24 2023-02-03 高通股份有限公司 采用分离的、双面的金属化结构来促进采用堆叠裸片的半导体裸片(“裸片”)模块的集成电路(ic)封装以及相关的制造方法
CN116259620A (zh) * 2022-08-09 2023-06-13 中国科学院自动化研究所 一种无线互连装置及系统
CN116259620B (zh) * 2022-08-09 2023-10-31 中国科学院自动化研究所 一种无线互连装置及系统

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