TWI664740B - 用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統 - Google Patents

用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統 Download PDF

Info

Publication number
TWI664740B
TWI664740B TW107122444A TW107122444A TWI664740B TW I664740 B TWI664740 B TW I664740B TW 107122444 A TW107122444 A TW 107122444A TW 107122444 A TW107122444 A TW 107122444A TW I664740 B TWI664740 B TW I664740B
Authority
TW
Taiwan
Prior art keywords
semiconductor die
metallization
capacitor
semiconductor
capacitor plate
Prior art date
Application number
TW107122444A
Other languages
English (en)
Other versions
TW201914039A (zh
Inventor
安東尼 Ｄ 威雀斯
Original Assignee
美商美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商美光科技公司 filed Critical 美商美光科技公司
Publication of TW201914039A publication Critical patent/TW201914039A/zh
Application granted granted Critical
Publication of TWI664740B publication Critical patent/TWI664740B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06531—Non-galvanic coupling, e.g. capacitive coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本文中揭示包含堆疊式半導體晶粒之半導體晶粒總成以及相關聯系統及方法，該等堆疊式半導體晶粒具有形成於該堆疊中之毗鄰對之半導體晶粒之間的平行板電容器。在一項實施例中，一半導體晶粒總成包含一第一半導體晶粒及堆疊於該第一半導體晶粒上方之一第二半導體晶粒。該第一半導體晶粒包含其上形成有一第一電容器板之一上部表面，且該第二半導體晶粒包含面向該第一半導體晶粒之該上部表面且其上形成有一第二電容器板之一下部表面。一介電材料至少部分地形成於該第一電容器板與該第二電容器板之間。該等第一電容器板、第二電容器板及介電材料一起形成一電容器，該電容器在該堆疊內局域地儲存電荷且可由該等第一半導體晶粒及/或第二半導體晶粒存取。

Description

用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統
本技術一般而言係關於堆疊式半導體裝置。本技術之數項實施例係關於藉由在堆疊中之毗鄰半導體晶粒之間形成電容器來改善至堆疊式半導體裝置之功率傳送。
微電子裝置(諸如記憶體裝置、微處理器及發光二極體)通常包含安裝至一基板且包封於一保護性覆蓋物中之一或多個半導體晶粒。半導體晶粒包含功能特徵，諸如記憶體單元、處理器電路、互連電路等。半導體晶粒製造商在日益增加之壓力下減小由半導體晶粒佔據之體積而增加容量及/或產生經囊封總成之速度。為滿足此等需求，半導體晶粒製造商通常將多個半導體晶粒垂直地堆疊於彼此之頂部上以增加一微電子裝置在半導體晶粒所安裝至之電路板或其他元件上之有限體積內之容量或效能。在某些半導體晶粒堆疊中，半導體晶粒使用矽導通孔(TSV)電互連。TSV使半導體晶粒能夠接近於彼此堆疊使得毗鄰半導體晶粒彼此間隔開僅相對較小垂直距離。此連同TSV之相對較低電感一起達成較高資料傳送速率。並且，由於晶粒係垂直堆疊的，因此堆疊之總佔據面積對應於堆疊中 最大晶粒之佔據面積。
然而，半導體晶粒堆疊之一個問題係功率傳送。舉例而言，當半導體晶粒執行高功率操作時，自堆疊中之半導體晶粒汲取之電流可係巨大的，此可導致至(舉例而言)堆疊中之最上部半導體晶粒之不良功率傳送。用於改善半導體晶粒堆疊中之功率傳送之習用方法包含增加堆疊中之每一半導體晶粒之TSV計數以減小功率網路之電阻。然而，增加半導體晶粒之TSV計數通常需要增加半導體晶粒之大小。因此，此項技術中仍需要用於改善半導體晶粒堆疊中之功率傳送之方法及系統。
本發明係關於一種半導體晶粒總成，其包括：一第一半導體晶粒，其具有一下部表面及與該下部表面對置之一上部表面；一第二半導體晶粒，其具有一下部表面及與該下部表面對置之一上部表面，該第二半導體晶粒堆疊於該第一半導體晶粒上方使得該第二半導體晶粒之該下部表面面向該第一半導體晶粒之該上部表面；及一堆疊中間電容器，其具有位於該第一半導體晶粒之該上部表面上之一第一電容器板，位於該第二半導體晶粒之該下部表面上之一第二電容器板，及位於該第一電容器板與該第二電容器板之間的一介電材料。
本發明進一步係關於一半導體晶粒總成，其包括：一半導體晶粒堆疊；及在該半導體晶粒堆疊中之每一毗鄰對之半導體晶粒之間：複數個互連件，其電耦合至少該毗鄰對之半導體晶粒，及一平行板電容器，其包含形成於該毗鄰對中之一上部者之一下部表面上之一上部板，形成於該毗鄰對中之一下部者之一上部表面上之一下部板，及位於該上部板及該下部板之間的一介電材料。
本發明進一步係關於一種製造一半導體晶粒總成之方法，該方法包括：在一第一半導體晶粒之一表面上形成複數個第一金屬化特徵，該等第一金屬化特徵電耦合至延伸穿過該第一半導體晶粒之矽導通孔(TSV)；在形成該複數個第一金屬化特徵時，在該第一半導體晶粒之該表面上形成一第一電容器板，該第一電容器板電耦合至該等第一金屬化特徵中之至少一者；在一第二半導體晶粒之一表面上形成複數個第二金屬化特徵；在形成該複數個第二金屬化特徵時，在該第二半導體晶粒之該表面上形成一第二電容器板，該第二電容器板電耦合至該等第二金屬化特徵中之至少一者；將該第二半導體晶粒堆疊於該第一半導體上方使得該第二電容器板之至少一部分位於該第一電容器板上方；及至少部分地在該第一電容器板與該第二電容器板之間形成一介電材料。
本發明進一步係關於一種製造一半導體晶粒總成之方法，其包括：提供一第一半導體晶粒，該第一半導體晶粒具有形成於該第一半導體晶粒之一表面上之一第一金屬結構；在該第一半導體晶粒上方堆疊一第二半導體晶粒使得形成於該第二半導體晶粒之一表面上之一第二金屬結構至少部分地與該第一金屬結構對準；及至少部分地在該第一金屬結構與該第二金屬結構之間形成一介電材料，其中該等第一金屬結構、第二金屬結構及介電材料一起形成一平行板電容器。
100‧‧‧半導體晶粒總成/總成
105‧‧‧堆疊
110‧‧‧半導體晶粒/最上部半導體晶粒/上部半導體晶粒/下部半導體晶粒/最下部半導體晶粒/最頂部半導體晶粒/交替半導體晶粒
112‧‧‧導通體
113a‧‧‧上部表面/表面
113b‧‧‧下部表面/表面
122‧‧‧電連接器
130‧‧‧導電互連件/互連件
132‧‧‧上部金屬化特徵/金屬化特徵
132a‧‧‧第一上部金屬化特徵
132b‧‧‧第二上部金屬化特徵
134‧‧‧下部金屬化特徵/金屬化特徵
134a‧‧‧第一下部金屬化特徵
134b‧‧‧第二下部金屬化特徵
136‧‧‧導電元件
142‧‧‧上部電容器板/電容器板
144‧‧‧下部電容器板/電容器板
150‧‧‧介電材料
216‧‧‧周邊區域
218‧‧‧中心區域
226‧‧‧周邊區域
228‧‧‧中心區域
238a‧‧‧導電跡線
238b‧‧‧導電跡線
248a‧‧‧導電跡線
248b‧‧‧導電跡線
338‧‧‧導電跡線/跡線
342‧‧‧上部電容器板
344‧‧‧下部電容器板
348‧‧‧導電跡線/跡線
400‧‧‧基板總成
460‧‧‧半導體材料
462‧‧‧介電材料
464‧‧‧介電襯裡
466‧‧‧導電插塞
468‧‧‧介電材料
500‧‧‧系統
502‧‧‧處理器
504‧‧‧記憶體
505‧‧‧輸入/輸出裝置
508‧‧‧子系統/組件
圖1係根據本技術之一實施例之一半導體晶粒總成之一剖面圖。
圖2A及圖2B分別係根據本技術之一實施例組態之一半導體晶粒之一俯視平面圖及仰視平面圖。
圖3A及圖3B分別係根據本技術之另一實施例組態之一半導體晶粒之一俯視平面圖及仰視平面圖。
圖4A至圖4C係根據本技術之一實施例之圖解說明處於各種製造階段處之一半導體晶粒之剖面圖。
圖5係根據本技術之實施例組態之包含一半導體晶粒總成之一系統之一示意圖。
下文闡述半導體晶粒及半導體晶粒總成之數項實施例之具體細節。在下文所闡述之數項實施例中，一半導體晶粒總成包含一半導體晶粒堆疊，該半導體晶粒堆疊具有形成於堆疊中之每一毗鄰對之半導體晶粒之間的一電容器。在某些實施例中，電容器係平行板電容器，該等平行板電容器包含：(a)一上部板，其形成於每一毗鄰對之半導體晶粒中之一上部者之一下部表面上；(b)一下部板，其形成於每一毗鄰對中之一下部者之一上部表面上；及(c)一介電材料，其位於該等上部板與下部板之間。平行板電容器可儲存局域地位於半導體晶粒堆疊內之電荷。當一個別半導體晶粒對功率具有一需求尖峰時，個別半導體晶粒可自平行板電容器中之一或多者拉挽功率以解決彼需求。此外，在特定實施例中，平行板電容器之板可在不給製造程序添加大量成本或複雜性之情況下形成為現有金屬化程序之部分以用於形成堆疊式半導體晶粒之間的互連。
如本文中所使用，術語「垂直」、「橫向」、「上部」及「下部」可係指鑒於圖中所展示之定向之半導體晶粒及半導體晶粒總成中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可係指經定位比另一特徵更接近於一頁之頂部之一特徵。然而，此等術語應廣泛地解 釋為包含具有其他定向之半導體晶粒及半導體晶粒總成，諸如翻轉或傾斜定向，其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換。
圖1係根據本技術之一實施例組態之一半導體晶粒總成100(「總成100」)之一剖面圖。總成100包含由一封裝基板120載運之半導體晶粒110之一堆疊105。封裝基板120可包含一中介層、一印刷電路板、一介電間隔件、另一半導體晶粒(例如，一邏輯晶粒)或另一適合基板。封裝基板120連接至將總成100電耦合至外部電路(未展示)之電連接器122(例如，焊料球)。在某些實施例中，總成100可在封裝基板120與半導體晶粒110中之一最下部者之間包含一中介層、另一邏輯晶粒或其他適合結構。
半導體晶粒110可各自具有積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他特徵。舉例而言，半導體晶粒110可包含積體記憶體電路及/或邏輯電路，該等積體記憶體電路及/或邏輯電路可包含各種類型之半導體組件及功能特徵，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體特徵。在某些實施例中，半導體晶粒110可係完全相同的(例如，經製造具有相同設計及規範之記憶體晶粒)，但在其他實施例中，半導體晶粒110可彼此不同(例如，不同類型之記憶體晶粒或控制器晶粒、邏輯晶粒及/或記憶體晶粒之一組合)。此外，儘管總成100包含堆疊於封裝基板120上之四個半導體晶粒110，但在其他實施例中總成100可包含少於四個半導體晶粒(例如，2個晶粒或3個晶粒)或多於4個晶粒(例如，5個晶粒，6個晶粒、8個晶粒、12個晶粒、16個晶粒、32個晶粒等)。
如圖1中進一步展示，半導體晶粒110各自具有一上部表面113a及與上部表面113a對置之一下部表面113b(統稱為「表面113a、113b」)。半導體晶粒110中之某些半導體晶粒可進一步包含至少實質上延伸穿過半導體晶粒110(例如，穿過其一半導體基板)之複數個導通體112(例如，矽導通孔(TSV))。在某些實施例中，每一導通體112包含完全穿過一個別半導體晶粒110之一導電材料(例如，銅)，及環繞導電材料以將導通體112與其餘半導體晶粒110電隔離之一電絕緣材料。更特定而言，導通體112可完全延伸穿過半導體晶粒110使得每一導通體112之一上部部分暴露在一個別半導體晶粒110之上部表面113a處，且導通體112之一下部部分暴露在個別半導體晶粒110之下部表面113b處。以此方式，導通體112經組態以用於機械連接及/或電連接至堆疊105中之其他半導體晶粒110及/或封裝基板120。如圖1之實施例中所圖解說明，堆疊105中之最上部半導體晶粒110可不具備導通體，此乃因穿過最上部半導體晶粒110之電連接(例如，位於最上部半導體晶粒110之上部表面113a處)可係不必要的。在其他實施例中，最上部半導體晶粒110亦可包含複數個導通體112，(舉例而言)以准許將最上部半導體晶粒110電耦合至最上部半導體晶粒110之上部表面113a處之其他電路(例如，額外半導體晶粒、較高階電路等)。在又其他實施例中，可在不使用TSV之情況下使用熟習此項技術者眾所周知之其他互連方法(包含例如搭迭式線接合、面對面互連等)將半導體晶粒110電耦合在一起。
總成100進一步包含在堆疊105中之毗鄰半導體晶粒110之間延伸且電耦合堆疊105中之毗鄰半導體晶粒110之複數個導電互連件130。互連件130可各自包含一上部金屬化特徵132、一下部金屬化特徵 134及耦合上部金屬化特徵132及下部金屬化特徵134(統稱為「金屬化特徵132、134」)之一導電元件136。導電元件136可包括一焊料材料，舉例而言錫銀、銦或用於在毗鄰半導體晶粒110上之金屬化特徵132、134之間形成一電連接及機械連接之另一適合焊料材料。在其他實施例中，導電元件136可由其他適合材料製成及/或具有不同結構(例如，銅柱、凸塊上氮化物結構等)。
大體而言，金屬化特徵132、134可係如此項技術中已知之任何適合凸塊下金屬(UBM)結構且電耦合至半導體晶粒110之導通體112中之對應者。上部金屬化特徵132形成於堆疊105中之一對毗鄰半導體晶粒110中之一上部半導體晶粒110之下部表面113b上。類似地，下部金屬化特徵134形成於該對毗鄰半導體晶粒中之一下部半導體晶粒110之上部表面113a上。更特定而言，如圖1中所展示，上部金屬化特徵132可形成於導通體112之下部部分上方、在該對毗鄰半導體晶粒中之上部半導體晶粒110之下部表面113b處暴露出。同樣地，下部金屬化特徵134可形成於導通體112之上部部分上方、在該對毗鄰半導體晶粒中之下部半導體晶粒110之上部表面113a處暴露出。因此，互連件130(亦即，上部金屬化特徵132、導電元件及下部金屬化特徵134)可與該對毗鄰半導體晶粒中之一對導通體112軸向對準且電耦合該對導通體。然而，在其他實施例中，互連件130未必與導通體112軸向對準。舉例而言，該對毗鄰半導體晶粒中之下部及/或上部半導體晶粒110上之一重佈層(RDL)或其他導電結構可提供毗鄰半導體晶粒之導通體112與金屬化特徵132、134之間的一不同對準及耦合。
金屬化特徵132、134可包括諸如(舉例而言)銅、鎳、金、 矽、鎢等適合導電材料中之任一者或組合，且可具有約1微米至100微米(例如，小於約10微米)之間的一厚度(例如，高度)。此外，金屬化特徵132、134之形狀及尺寸可變化。舉例而言，在某些實施例中金屬化特徵132、134具有一實質上圓柱形剖面形狀且形成柱狀結構。在其他實施例中，金屬化特徵132、134可具有其他剖面形狀，諸如矩形、正多邊形、不規則多邊形、橢圓形等。
總成100進一步包含複數個上部電容器板142及複數個下部電容器板144(統稱為「電容器板142、144」)。每一上部電容器板142形成於堆疊105中之一對毗鄰半導體晶粒110中之一上部半導體晶粒110之下部表面113b上，且每一下部電容器板144形成於該對毗鄰半導體晶粒中之一下部半導體晶粒110之上部表面113a上。如圖1之實施例中所圖解說明，每一上部電容器板142面向一對應下部電容器板144且至少部分地與對應下部電容器板144對準。舉例而言，如圖1中所展示，每一上部電容器板142疊加於毗鄰下部半導體晶粒110上之對應下部電容器板144上方(例如，電容器板142、144實質上關於在毗鄰半導體晶粒之間延伸之一平面反射對稱)。電容器板142、144中之至少一者電耦合至一電源供應器而另一者電耦合至接地。舉例而言(如圖2A及圖2B中所展示)，電容器板142、144可各自經由形成於半導體晶粒110之表面113a、113b上之導電跡線電耦合至互連件130中之一或多者，從而提供一功率或接地信號。在其他實施例中，電容器板142、144可使用其他適合電連接器(諸如線接合)電耦合至電源供應器或接地。因此，可在形成於堆疊105中之每一對毗鄰半導體晶粒110之間的相對電容器板142、144之間提供一電壓差。
如下文參考圖4A至圖4C進一步闡述，電容器板142、144 可作為用於形成金屬化特徵132、134(例如，在相同處理階段處及/或同時)之金屬化程序一擴展而形成。因此，由於其可由相同程序形成，金屬化特徵132、134及電容器板142、144之特性中之至少某些特性可係相同的或實質上類似。舉例而言，金屬化特徵132、134可分別具有與電容器板142、144相同或實質上類似之一厚度。類似地，金屬化特徵132、134可包括與電容器板142、144相同之材料(例如，銅、鎳、金、矽、鎢等)。
總成100可進一步包含圍繞及/或在半導體晶粒110、互連件130及電容器板142、144之間沈積或以其他方式形成以電隔離此等組件及/或增強堆疊105中之半導體晶粒110之間的機械連接之一介電材料150。介電材料150可係一非導電環氧樹脂膏、一毛細管底部填充物、一非導電膜、一模製底部填充物及/或包含其他適合電絕緣材料。
總之，每一對相對電容器板142、144及其間之介電材料150形成一堆疊中間電容器(例如，一平行板電容器)，該堆疊中間電容器儲存堆疊105內之電荷。儲存於每一平行板電容器上之電荷與電容器之電容(C)成比例，C=k A/d，其中「k」係板之間的介電材料之相對介電常數，「」係真空介電常數，「A」係電容器板之面積且「d」係電容器板之間的間隔。在某些實施例中，總成100中形成之堆疊中間電容器各自具有10's至100's微微法拉(例如，多於約100微微法拉)之一電容。此外，由於電容(及因此由電容器儲存之電荷)與電容器板142、144之間的距離成反比，因此電容可隨著堆疊105中之半導體晶粒110之間的垂直距離(例如，間隔)減小而增加。堆疊105中之半導體晶粒110之間的間隔很大程度上取決於互連件130之大小。因此，隨著技術發展到減小互連件130之大小且藉此減小總成100之總高度，本文中所闡述之堆疊中間電容器之電容 可相應地增加。此外，在某些實施例中，可基於介電材料150之介電品質(例如，其相對介電常數或其他特性)來選擇介電材料150以便增加堆疊中間電容器之電容。
一般而言，堆疊105中之每一堆疊中間電容器給堆疊105之功率網路添加電容，在需要時該電容可由半導體晶粒110汲取出。舉例而言，當堆疊105中之一個別半導體晶粒110對功率具有一需求尖峰時(例如，當個別半導體晶粒110執行一功率密集型操作(諸如起始一存取、讀取操作等)時)，個別半導體晶粒110可自堆疊中間電容器中之一或多者汲取其所需求功率中之某些功率。堆疊中間電容器提供比一外部電源供應器更局域化之一電源，該電源之功率必須路由通過封裝基板120且向上通過導通體112及互連件130。因此，堆疊中間電容器可快速地解決半導體晶粒110之某些短期功率需求，回應於此，電源供應器可取決於堆疊105中之其他半導體晶粒110(例如，堆疊中之下部半導體晶粒)之功率需求而變慢。用以改善一半導體晶粒堆疊之功率傳送之習用方法會增加堆疊中之每一半導體晶粒之TSV計數以包含較多功率及接地連接以藉此減小功率網路之電阻。然而，增加半導體晶粒之TSV計數需要增加半導體晶粒之大小。本技術有利地在不增加TSV計數及/或半導體晶粒110之大小之情況下增加總成100中之功率網路之電容使得總成100可較佳地滿足堆疊105中之半導體晶粒110之功率需求。
此外，給功率網路添加電容可改善傳輸穿過位於導通體112中之一或多者上之堆疊105之信號之信號完整性及/或半導體晶粒110之效能。舉例而言，堆疊中間電容器可充當解耦電容器以分流否則可透過堆疊105載運(例如，電壓尖峰或由堆疊中之其他晶粒導致之接地反射)且可 阻礙半導體晶粒110之效能之雜訊。堆疊中間電容器亦可幫助解決電感響鈴(例如，由於記憶體裝置中之封裝自電感之響鈴)問題。舉例而言，堆疊中間電容器可幫助最小化電源供應器及接地連接之導電路徑藉此改善半導體晶粒110之效能。
如圖1中所展示，一堆疊中間電容器形成於堆疊105中之每一對毗鄰半導體晶粒110之間。堆疊中間電容器可並聯或串聯或者以其某種組合形式電耦合。然而，在某些實施例中，堆疊105可僅具備一個形成於一單個對之毗鄰半導體晶粒110之間的堆疊中間電容器或具備任何其他數目個堆疊中間電容器。在某些實施例中，可藉由以下操作在封裝基板120與堆疊105中之最下部半導體晶粒110之間形成一額外電容器：(a)在封裝基板120上提供一下部電容器板144、(b)在最下部半導體晶粒110之下部表面113b上提供一對應上部電容器板142及(c)在下部電容器板144與上部電容器板142之間提供一介電材料(例如，介電材料150)。類似地，在某些實施例中，一電容器可形成於堆疊105中之最上部半導體晶粒110之上部表面113a與連接至其之任何外部組件之間。
圖2A及圖2B分別係根據本技術之實施例之圖1中所展示之總成100之半導體晶粒110中之一者之一俯視平面圖及仰視平面圖，其中在半導體晶粒110之表面113a、113b中之每一者上具有金屬化特徵及一電容器板。所圖解說明半導體晶粒110可係堆疊105之中間中之半導體晶粒110中之一者(例如，在上面及下面皆具有一毗鄰半導體晶粒110)，此乃因堆疊105中之最下部半導體晶粒110及最頂部半導體晶粒110可分別經形成在其下部表面113b及上部表面113a上無一電容器板及/或金屬化特徵(如圖1中所圖解說明)。
更特定而言，圖2A圖解說明具有一或多個周邊區域216(例如，橫向外側區域)及一中心區域218的半導體晶粒110之上部表面113a。下部金屬化特徵134形成於周邊區域216上，且下部電容器板144形成於上部表面113a之中心區域218上。下部電容器板144可經由導電跡線238(個別地展示為導電跡線238a及238b)電耦合至下部金屬化特徵134中之一或多者。舉例而言，如圖2A之實施例中所圖解說明，下部電容器板144可經由導電跡線238a電耦合至一第一下部金屬化特徵134a且經由導電跡線238b電耦合至一第二下部金屬化特徵134b。第一下部金屬化特徵134a及第二下部金屬化特徵134b可電耦合至接地或電耦合至一電源供應器。在某些實施例中，導電跡線238形成為與下部金屬化特徵134及下部電容器板144相同之金屬化程序之部分。
圖2B圖解說明具有一或多個周邊區域226(例如，橫向外側區域)及一中心區域228之半導體晶粒110之下部表面113b。上部金屬化特徵132形成於周邊區域226上，且上部電容器板142形成於下部表面113b之中心區域228上。上部電容器板142可經由導電跡線248(個別地展示為導電跡線248a及248b)電耦合至上部金屬化特徵132中之一或多者。舉例而言，如圖2B之實施例中所圖解說明，上部電容器板142可經由導電跡線248a電耦合至一第一上部金屬化特徵132a且經由導電跡線248b電耦合至一第二上部金屬化特徵132b。第一上部金屬化特徵132a及第二上部金屬化特徵132b可電耦合至接地或電耦合至一電源供應器。在某些實施例中，導電跡線248形成為與上部金屬化特徵132及上部電容器板142相同之金屬化程序之部分。
在某些實施例中，電容器板142、144可電耦合至半導體晶 粒110之相同導通體(圖1)。因此，電容器板142、144可即電耦合至接地又電耦合至電源供應器。在此等實施例中，堆疊105中之每一交替半導體晶粒110可具備電容器板142、144之相同組態使得在形成於堆疊105中之毗鄰對之半導體晶粒110之間的相對電容器板142、144之間存在一電壓差。然而，在其他實施例中，半導體晶粒110上之電容器板142、144可電耦合至導通體112中之不同者(例如，單獨者)使得電容器板142、144中之一者電耦合至接地，而另一者電耦合至電源供應器。舉例而言，在此等實施例中，堆疊105中之每一上部電容器板142可電耦合至電源供應器而每一下部電容器板144電耦合至接地。
一起參考圖2A及圖2B兩者，電容器板142、144可經形成以分別填充尚未由金屬化特徵132、134佔據之表面113b、113a之一實質區。舉例而言，如圖2A及圖2B兩者中所圖解說明，半導體晶粒110可具有在表面113a、113b之周邊區域216、226處配置成列之金屬化特徵132、134。藉由在中心區域218、228上形成電容器板142、144且具有一矩形剖面(例如，一矩形平面形狀)，電容器板142、144可佔據未由金屬化特徵132、134(其位置可限制於導通體112之一位置)佔據之表面113a、113b之一實質區。舉例而言，在某些實施例中，電容器板142、144可分別覆蓋大於半導體晶粒110之表面113a、113b之表面面積之約25%之一面積。在某些實施例中，電容器板142、144可覆蓋大於表面113a、113b之表面面積之約50%之一面積。在又其他實施例中，電容器板142、144可覆蓋大於表面113a、113b之表面面積之約75%之一面積。然而，電容器板142、144之覆蓋範圍不受限制且電容器板142、144可覆蓋表面113a、113b之任何適合部分。此外，在特定實施例中，金屬化特徵132、134可形成於半 導體晶粒110之一不同區域上且可具有不同配置。在此等實施例中，電容器板之大小、形狀及定位可經選擇以匹配金屬化特徵132、134之佈局。
舉例而言，圖3A及圖3B分別係根據本技術之另一實施例之總成100之半導體晶粒110中之一者之一俯視平面圖及仰視平面圖，其中在半導體晶粒110之表面113a、113b上具有金屬化特徵與電容器板之一不同配置。一起參考圖3A及圖3B兩者，金屬化特徵132、134分別配置成沿著表面113b、113a均勻地間隔開之列。金屬化特徵132、134可以此方式配置(舉例而言)以匹配半導體晶粒110之導通體(例如，導通體112)之配置。如圖3A中所展示，一下部電容器板344於形成半導體晶粒110之上部表面113a上且經由導電跡線338電耦合至下部金屬化特徵134中之一或多者(例如，對應於功率或接地)。類似地，如圖3B中所展示，一上部電容器板342形成於半導體晶粒110之下部表面113b上且經由導電跡線348電耦合至上部金屬化特徵132中之一或多者(例如，對應於功率或接地)。在某些實施例中，上部電容器板342及下部電容器板344兩者皆電耦合至半導體晶粒110之相同導通體112(圖1)(例如，使得兩個板皆接地或使得兩個板皆連接至一電源供應器)，而在其他實施例中，上部電容器板342及下部電容器板344電耦合至導通體112中之不同者(例如，使得該等板中之一者接地而另一者連接至電源供應器)。此外，上部電容器板342及下部電容器板344兩者皆具有一大體直線形狀且圍繞金屬化特徵132、134形成於開口表面面積之一實質部分上。假定金屬化特徵132、134之佈局，此一配置通常可允許上部電容器板342及下部電容器板344具有最大面積。
一般而言，本文中所闡述之電容器板之大小、形狀及定位可經選擇以最大化或幾乎最大化電容器板之面積，以便增加形成於一晶粒 堆疊中之堆疊中間電容器之電容。更特定而言，每一電容器板可形成於尚未由金屬化特徵佔據的一半導體晶粒之開口表面區上。因此，本文中所闡述之電容器板可適用於其形成於上面之半導體晶粒之特定組態(例如，適用於導通體、金屬化特徵及/或其他特徵之配置)，同時亦給晶粒總成添加少許或不附加額外負荷(例如，不增加晶粒總成之平面大小或厚度)。
此外，每一半導體晶粒可在其一表面上包含一單個電容器板(如結合上文之數項實施例所闡述)或在其一表面上包含一個以上電容器板。舉例而言，假定現有金屬化結構，如本文中所闡述之一半導體晶粒可包含多個離散電容器板以匹配半導體晶粒之表面上可用之空間。離散電容器板可係電耦合(例如，經由導電跡線)或電隔離的。在某些實施例中，毗鄰半導體晶粒可各自在其面向表面上具有多個離散電容器板以便在毗鄰半導體晶粒之間形成多個離散平行板電容器。多個平行板電容器可獨立於彼此操作，或可並聯連接、串聯連接等。
圖4A至圖4C係根據本技術之實施例之圖解說明製造其上形成有金屬化特徵及電容器板之一半導體晶粒之一方法中之各種階段之剖面圖。在圖4A至圖4C中所圖解說明之實施例中，複數個半導體晶粒110可形成於一基板總成400之離散區處(例如，一半導體晶圓或面板)。基板總成400包含一半導體材料460及半導體材料460之一上部側上之一介電材料462。儘管圖4A至圖4C中僅圖解說明一單個半導體晶粒110，但在實踐中基板總成400通常具有數百個或甚至超過1,000個個別半導體晶粒。
參考圖4A，在此處理階段處，半導體材料460中已形成導通體112。如熟習此項技術者將易於理解，可藉由將一高縱橫比孔蝕刻至半導體材料460中且在一或多個沈積及/或電鍍步驟中用一或多種材料填充 該高縱橫比孔來製成導通體112舉例而言，在圖4A中所展示之實施例中，導通體112包含一介電襯裡464及介電襯裡464內之一導電插塞466。如圖4A中進一步展示，導通體112之上部部分暴露在半導體晶粒110之上部表面113a處。
圖4B圖解說明在導通體112之上部部分上方形成下部金屬化特徵134及在半導體晶粒110之上部表面113a上形成下部電容器板144之後之基板總成400。值得注意地，下部電容器板144可作為用於形成下部金屬化特徵134之金屬化程序之一擴展而形成。金屬化程序可係此項技術中已知之任何適合金屬化程序(例如，一前側金屬化或凸塊下金屬化程序)。舉例而言，在某些實施例中，下部金屬化特徵134係藉由以下操作形成：將一銅晶種結構沈積至介電材料462及導通體112之上部部分上、在具有與導通體112之上部部分對準之開口之銅晶種結構上形成一遮罩、將銅電鍍至晶種結構上、且然後在銅上方電鍍一或多種其他材料以形成下部金屬化特徵134。下部電容器板144可藉由調整遮罩圖案以包含對應於下部電容器板144之一所要形狀、位置及大小之一或多個開口及將下部電容器板144連接至下部金屬化特徵134中之一或多者之任何跡線(例如，圖2A中之跡線238)而形成為此一程序之部分。在某些實施例中，在形成下部金屬化特徵134及下部電容器板144(在某些實施例中，以及導電元件136)之後，移除遮罩且使用一適合濕式蝕刻移除晶種結構之經暴露部分以將下部金屬化特徵134與下部電容器板144隔離。
圖4C圖解說明以下操作之後之基板總成400：(a)將半導體材料460薄化以暴露半導體晶粒110之下部表面113b及導通體112之下部部分(例如，使用背面研磨、乾式蝕刻程序、化學蝕刻程序、化學機械拋光 (CMP)等)；(b)在半導體材料460之一下部側上形成一介電材料468；(c)在導通體112之下部部分上方形成上部金屬化特徵132；及(d)在半導體晶粒110之下部表面113b上形成上部電容器板142。上部電容器板142可作為用於形成上部金屬化特徵132之金屬化程序之一擴展而形成，該金屬化程序可係此項技術中已知之任何適合程序(例如，一背側金屬化或凸塊下金屬化程序)。在某些實施例中，用於形成下部金屬化特徵134及下部電容器板144之金屬化程序可係與用於形成上部金屬化特徵132及上部電容器板142相同之金屬化程序。在其他實施例中，該等程序可係不同的。舉例而言，不需要針對堆疊中之最上部晶粒及最下部晶粒執行圖4A至圖4C中所圖解說明之階段中之至少某些階段，該等最上部晶粒及最下部晶粒可經形成在至少一個表面不具有電容器板及/或金屬化特徵。一旦完成對基板總成400之處理，半導體晶粒110便可自基板總成400單粒化且併入至一晶粒總成(例如，圖1中所展示之總成100)中。
值得注意地，可在不給用於形成金屬化特徵132、134之現有方法添加顯著額外成本或複雜性之情況下形成電容器板142、144，此乃因電容器板142、144可作為彼等方法之一擴展而形成。同樣地，導電跡線(例如，圖2A至圖3B中所展示之跡線238/248及338/348)亦可容易地形成為相同方法之部分，以用於將電容器板142、144電耦合至對應金屬化特徵132、134以在板之間提供一適合電壓差。
可將具有上文參考圖1至圖4C所闡述之特徵之半導體裝置中之任一者併入至無數較大及/或較複雜系統中之任何者中，該等系統之一代表性實例係圖5中示意性地展示之系統500。系統500可包含一處理器502、一記憶體504(例如，SRAM、DRAM、快閃及/或其他記憶體裝 置)、輸入/輸出裝置505及/或其他子系統或組件508。上文參考圖1至圖4C所闡述之半導體晶粒總成100及半導體晶粒110可包含於圖5中所展示之元件中之任何者中。所得系統500可經組態以執行各種各樣之適合計算、處理、儲存、感測、成像及/或其他功能中之任何者。因此，系統500之代表性實例包含(但不限於)電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路器具、手持式裝置(例如，掌上型電腦、隨身電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器或可程式化消費性電子器件、網路電腦及小型電腦。系統500之額外代表性實例包含燈、相機、運載工具等。關於此等及其他實例，系統500可裝納於一單個單元中或跨越多個經互連單元分佈(例如，透過一通信網路)。因此，系統500之組件可包含本端及/或遠端記憶體儲存裝置及各種各樣之適合電腦可讀媒體中之任何者。
依據前述內容，將瞭解，雖然本文中已出於圖解說明的目的而闡述本技術之特定實施例，但可在不背離本發明之情況下做出各種修改。因此，本發明不受除所附申請專利範圍以外之任何限制。此外，亦可在其他實施例中組合或消除在特定實施例之內容脈絡中所闡述之新技術之特定態樣。此外，儘管已在本新技術之特定實施例之內容脈絡中闡述與彼等實施例相關聯之優點，但其他實施例亦可展現此等優點且並非所有實施例皆必須展現此等優點以歸屬於本技術之範疇內。因此，本發明及相關聯技術可囊括本文中未明確展示或闡述之其他實施例。

Claims (25)

  1. 一種半導體晶粒總成，其包括： 一第一半導體晶粒，其具有一下部表面及與該下部表面對置之一上部表面； 一第二半導體晶粒，其具有一下部表面及與該下部表面對置之一上部表面，該第二半導體晶粒堆疊於該第一半導體晶粒上方使得該第二半導體晶粒之該下部表面面向該第一半導體晶粒之該上部表面；及 一堆疊中間電容器，其具有位於該第一半導體晶粒之該上部表面上之一第一電容器板，位於該第二半導體晶粒之該下部表面上之一第二電容器板，及位於該第一電容器板與該第二電容器板之間的一介電材料。
  2. 如請求項1之半導體晶粒總成，其中該堆疊中間電容器係一平行板電容器。
  3. 如請求項2之半導體晶粒總成，其中該平行板電容器具有大於約100 pF之一電容。
  4. 如請求項1之半導體晶粒總成，其進一步包括： 至少一個第一矽導通孔(TSV)，其延伸穿過該第一半導體晶粒； 一第一金屬化特徵，其位於該第一半導體晶粒之該上部表面上且電耦合至該第一TSV；及 一第二金屬化特徵，其位於該第二半導體晶粒之該下部表面上且電耦合至該第一金屬化特徵。
  5. 如請求項4之半導體晶粒總成，其中該第一金屬化特徵係由與該第一電容器板相同之金屬材料製成，且其中該第二金屬化特徵係由與該第二電容器板相同之金屬材料製成。
  6. 如請求項4之半導體晶粒總成，其中該第一金屬化特徵具有與該第一電容器板實質上相同之厚度，且其中該第二金屬化特徵具有與該第二電容器板實質上相同之厚度。
  7. 如請求項4之半導體晶粒總成，其進一步包括延伸穿過該第二半導體晶粒之至少一個第二TSV，其中該第二金屬化特徵電耦合至該第二TSV。
  8. 如請求項7之半導體晶粒總成，其中該等第一TSV、第二TSV、第一金屬化特徵及第二金屬化特徵軸向對準。
  9. 如請求項1之半導體晶粒總成，其中該第一電容器板及該第二電容器板具有關於在其間延伸之一平面反射對稱之矩形平面形狀。
  10. 如請求項1之半導體晶粒總成，其中該第一電容器板具有大於該第一半導體晶粒之該上部表面之一面積之約25％之一表面面積。
  11. 如請求項1之半導體晶粒總成，其進一步包括： 一第三半導體晶粒，其具有一下部表面及與該下部表面對置之一上部表面，該第三半導體晶粒堆疊於該第二半導體晶粒上方使得該第二半導體晶粒之該上部表面面向該第三半導體晶粒之該下部表面；及 另一堆疊中間電容器，其具有位於該第二半導體晶粒之該上部表面上之一第三電容器板，位於該第三半導體晶粒之該下部表面上之一第四電容器板，及位於該第三電容器板與該第四電容器板之間的一介電材料。
  12. 一種半導體晶粒總成，其包括： 一半導體晶粒堆疊；及 在該半導體晶粒堆疊中之每一毗鄰對之半導體晶粒之間， 複數個互連件，其電耦合至少該毗鄰對之半導體晶粒，及一平行板電容器，其包含：一上部板，該上部板形成於該毗鄰對之半導體晶粒中之一上部者之一下部表面上；一下部板，該下部板形成於該毗鄰對之半導體晶粒中之一下部者之一上部表面上；及一介電材料，其位於該上部與該下部板之間。
  13. 如請求項12之半導體晶粒總成，其中該等上部板電耦合至一電源供應器，且其中該等下部板電耦合至接地。
  14. 如請求項12之半導體晶粒總成，其中每一上部板電耦合至該等互連件中之至少一第一者，且其中每一下部板電耦合至該等互連件中之至少一第二者。
  15. 如請求項12之半導體晶粒總成，其中每一互連件包含：一上部金屬化特徵，該上部金屬化特徵形成於該毗鄰對之半導體晶粒中之該上部者之該下部表面上；及一下部金屬化特徵，該下部金屬化特徵形成於該毗鄰對之半導體晶粒中之該下部者之該上部表面上。
  16. 如請求項15之半導體晶粒總成，其中該等上部金屬化特徵係由與該上部板相同之材料製成，且其中該等下部金屬化特徵係由與該下部板相同之材料製成。
  17. 如請求項15之半導體晶粒總成，其中： 該等上部金屬化特徵形成於該毗鄰對之半導體晶粒中之該上部者之該下部表面之一周邊區域上，且該上部板形成於該毗鄰對之半導體晶粒中之該上部者之該下部表面之一中心區域上，且 該等下部金屬化特徵形成於該毗鄰對之半導體晶粒中之該下部者之該上部表面之一周邊區域上，且該下部板形成於該毗鄰對之半導體晶粒中之該下部者之該上部表面之一中心區域上。
  18. 如請求項15之半導體晶粒總成，其中每一互連件之該上部金屬化特徵與該互連件之該下部金屬化特徵對準，且其中每一互連件進一步包括將該上部金屬化特徵耦合至該下部金屬化特徵之一焊料球或一焊料凸塊。
  19. 如請求項12之半導體晶粒總成，其中每一個別半導體晶粒經由該等互連件電耦合至該等平行板電容器及該電源供應器中之至少一者，且其中該至少一個平行板電容器提供比該電源供應器更接近於該個別半導體晶粒之一電源。
  20. 如請求項12之半導體晶粒總成，其包含至少8個半導體晶粒。
  21. 一種製造一半導體晶粒總成之方法，其包括： 在一第一半導體晶粒之一表面上形成複數個第一金屬化特徵，該等第一金屬化特徵電耦合至延伸穿過該第一半導體晶粒之矽導通孔(TSV)； 在形成該複數個第一金屬化特徵時，在該第一半導體晶粒之該表面上形成一第一電容器板，該第一電容器板電耦合至該等第一金屬化特徵中之至少一者； 在一第二半導體晶粒之一表面上形成複數個第二金屬化特徵； 在形成該複數個第二金屬化特徵時，在該第二半導體晶粒之該表面上形成一第二電容器板，該第二電容器板電耦合至該等第二金屬化特徵中之至少一者； 將該第二半導體晶粒堆疊於該第一半導體上方使得該第二電容器板之至少一部分位於該第一電容器板上方；及 至少部分地在該第一電容器板與該第二電容器板之間形成一介電材料。
  22. 如請求項21之方法，其進一步包括經由安置於該等第一金屬化特徵與該等第二金屬化特徵之間的複數個電連接器將該等第一金屬化特徵電耦合至該等第二金屬化特徵，其中該等電連接器係焊料球或焊料接頭中之至少一者。
  23. 如請求項21之方法，其中： 該第一半導體晶粒之該表面包含一第一部分及一第二部分，該等第一金屬化特徵形成於該第一半導體晶粒之該表面之該第一部分上，且該第一電容器板形成於該第一半導體晶粒之該表面之實質上所有該第二部分上；且 該第二半導體晶粒之該表面包含一第一部分及一第二部分，該等第二金屬化特徵形成於該第二半導體晶粒之該表面之該第一部分上，且該第二電容器板形成於該第二半導體晶粒之該表面之實質上所有該第二部分上。
  24. 一種製造一半導體晶粒總成之方法，其包括： 提供一第一半導體晶粒，該第一半導體晶粒具有形成於該第一半導體晶粒之一表面上之一第一金屬結構； 在該第一半導體晶粒上方堆疊一第二半導體晶粒使得形成於該第二半導體晶粒之一表面上之一第二金屬結構至少部分地與該第一金屬結構對準；及 至少部分地在該第一金屬結構與該第二金屬結構之間形成一介電材料，其中該等第一金屬結構、第二金屬結構及介電材料一起形成一平行板電容器。
  25. 如請求項24之方法，其進一步包括： 在該第一半導體晶粒與該第二半導體晶粒之間形成複數個互連件，其中每一互連件包含形成於該第一半導體晶粒之該表面上之一第一金屬化特徵及形成於該第二半導體晶粒之該表面上之一第二金屬化特徵，其中該等第一金屬化特徵及第二金屬化特徵軸向對準且經由安置於其間之一電連接器電耦合，其中該第一金屬化特徵及該第一金屬結構係由相同材料製成，且其中該第二金屬化特徵及該第二金屬結構係由相同材料製成。
TW107122444A 2017-08-23 2018-06-29 用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統 TWI664740B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/684,703 2017-08-23
US15/684,703 US10134712B1 (en) 2017-08-23 2017-08-23 Methods and systems for improving power delivery and signaling in stacked semiconductor devices

Publications (2)

Publication Number Publication Date
TW201914039A TW201914039A (zh) 2019-04-01
TWI664740B true TWI664740B (zh) 2019-07-01

Family

ID=64176789

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107122444A TWI664740B (zh) 2017-08-23 2018-06-29 用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統

Country Status (4)

Country Link
US (4) US10134712B1 (zh)
CN (2) CN114937657A (zh)
TW (1) TWI664740B (zh)
WO (1) WO2019040145A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10134712B1 (en) 2017-08-23 2018-11-20 Micron Technology, Inc. Methods and systems for improving power delivery and signaling in stacked semiconductor devices
CN110945652A (zh) * 2019-04-15 2020-03-31 长江存储科技有限责任公司 堆叠三维异质存储器件及其形成方法
US11456291B2 (en) * 2020-06-24 2022-09-27 Qualcomm Incorporated Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
KR20220028741A (ko) * 2020-08-31 2022-03-08 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
CN112166501B (zh) * 2020-09-02 2024-01-09 长江存储科技有限责任公司 半导体器件中的片上电容器结构
US11552055B2 (en) * 2020-11-20 2023-01-10 Qualcomm Incorporated Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods
CN115377085A (zh) * 2022-08-09 2022-11-22 中国科学院自动化研究所 一种无线互连装置及系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110059593A1 (en) * 2009-07-31 2011-03-10 Yan Xun Xue Method of Integrating a MOSFET with a Capacitor
US20140268612A1 (en) * 2013-03-13 2014-09-18 Qinglei Zhang Coreless substrate with passive device pads

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611419B1 (en) * 2000-07-31 2003-08-26 Intel Corporation Electronic assembly comprising substrate with embedded capacitors
KR100881182B1 (ko) 2006-11-21 2009-02-05 삼성전자주식회사 웨이퍼 사이에 형성된 디커플링 커패시터, 그 디커플링커패시터를 포함하는 웨이퍼 스택 패키지, 및 그 패키지제조 방법
US8310061B2 (en) 2008-12-17 2012-11-13 Qualcomm Incorporated Stacked die parallel plate capacitor
KR101046394B1 (ko) 2010-02-03 2011-07-05 주식회사 하이닉스반도체 스택 패키지
KR20120068216A (ko) 2010-12-17 2012-06-27 에스케이하이닉스 주식회사 반도체 집적회로
KR101589843B1 (ko) 2011-09-30 2016-01-28 인텔 코포레이션 3d 집적 회로 적층을 위한 층간 통신들
US8697567B2 (en) * 2012-05-22 2014-04-15 International Business Machines Corporation Implementing decoupling devices inside a TSV DRAM stack
US10032751B2 (en) * 2015-09-28 2018-07-24 Invensas Corporation Ultrathin layer for forming a capacitive interface between joined integrated circuit components
US10134712B1 (en) * 2017-08-23 2018-11-20 Micron Technology, Inc. Methods and systems for improving power delivery and signaling in stacked semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110059593A1 (en) * 2009-07-31 2011-03-10 Yan Xun Xue Method of Integrating a MOSFET with a Capacitor
US20140268612A1 (en) * 2013-03-13 2014-09-18 Qinglei Zhang Coreless substrate with passive device pads

Also Published As

Publication number Publication date
US10134712B1 (en) 2018-11-20
WO2019040145A1 (en) 2019-02-28
CN110998837A (zh) 2020-04-10
US10304809B2 (en) 2019-05-28
CN114937657A (zh) 2022-08-23
TW201914039A (zh) 2019-04-01
US11728315B2 (en) 2023-08-15
US20220122943A1 (en) 2022-04-21
US20190252355A1 (en) 2019-08-15
US20190067252A1 (en) 2019-02-28
US11239200B2 (en) 2022-02-01

Similar Documents

Publication Publication Date Title
TWI664740B (zh) 用於改善堆疊式半導體裝置中功率傳送及發信之方法及系統
US9870982B2 (en) Distributed on-chip decoupling apparatus and method using package interconnect
US20120319293A1 (en) Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package
US11990446B2 (en) Semiconductor assemblies with redistribution structures for die stack signal routing
US11652101B2 (en) Trench capacitor assembly for high capacitance density
US20220189934A1 (en) Backside Interconnection Interface Die For Integrated Circuits Package
US20240047326A1 (en) Fan-out packaging structure and method for manufacturing same
US20120168933A1 (en) Wafer level molding structure
CN110544673B (zh) 一种多层次融合的三维系统集成结构
US10615248B1 (en) On-die capacitor for a VLSI chip with backside metal plates
US20230207546A1 (en) Stacking power delivery device dies
CN116114396A (zh) 前道工艺互连结构以及相关联的系统和方法
CN116075927A (zh) 前段工艺互连结构以及相关联系统和方法
CN114188480A (zh) 一种电容器结构及其形成电容器结构的方法
US11562987B2 (en) Semiconductor devices with multiple substrates and die stacks
CN112530879B (zh) 微电子装置和微电子装置制造
US20240072022A1 (en) Stacked capacitors for semiconductor devices and associated systems and methods
US20230055854A1 (en) Hybrid metallic structures in stacked semiconductor devices and associated systems and methods
US20220037258A1 (en) Semiconductor devices with thermal buffer structures
US20230060594A1 (en) Castellation, hatching, and other surface patterns in dielectric surfaces for hybrid bonding with increased surface area, bond strength, and alignment
TW202230653A (zh) 具有經整合構件之電子構件封裝件