CN115580994A - Control method for improving etching precision of bonding IC - Google Patents
Control method for improving etching precision of bonding IC Download PDFInfo
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- CN115580994A CN115580994A CN202211443146.4A CN202211443146A CN115580994A CN 115580994 A CN115580994 A CN 115580994A CN 202211443146 A CN202211443146 A CN 202211443146A CN 115580994 A CN115580994 A CN 115580994A
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- 238000005530 etching Methods 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004088 simulation Methods 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 47
- 229910052802 copper Inorganic materials 0.000 claims description 47
- 239000010949 copper Substances 0.000 claims description 47
- 239000002253 acid Substances 0.000 claims description 8
- 238000012360 testing method Methods 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 4
- 230000002378 acidificating effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 238000005553 drilling Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000006087 Brown hydroboration reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention belongs to the technical field of PCBs (printed circuit boards), and provides a control method for improving etching precision of a bonding IC (integrated circuit). The control method comprises the following steps: s1, establishing a simulation compensation model according to the etching form change of a bound IC; s2, setting bonding IC compensation; performing at least three-level gradient compensation on the bonding IC bonding pad according to the simulation compensation model; s3, etching the bonding IC; including performing two etches. According to the method, the simulation model is established according to the etching form of the bonding IC, and then three-level gradient compensation is carried out on the top position of the bonding IC according to the simulation model, and the equidistant dummy pads are added on the outermost side, so that the problems of thin etching lines, top end needle point effect and the like of the bonding IC are solved, the etching precision of the bonding IC is improved, and the product yield is improved from 50% to more than 98%.
Description
Technical Field
The invention belongs to the technical field of PCBs, and particularly relates to a control method for improving etching precision of a bonding IC.
Background
Bonding is a wire bonding method in chip production process, and is generally used for connecting a chip internal circuit with a package pin or an IC gold-plated pad of a PCB (printed circuit board) by using a gold wire or an aluminum wire before packaging. Along with the increase of PCB wiring density, bonding IC pad size becomes more and more meticulous, pad size 12 mils of length 4 mils wide has become conventional design, PCB printed board to this kind of design bonding IC, if carry out linewidth compensation and conventional etching parameter according to conventional processing mode and produce, bonding IC position is easy the line thin, it is basically below the negative tolerance to go up the linewidth, especially conventional equal width compensation, easily form "needle point" effect in IC top position after the etching, cause the influence to the middle 50% core position (3-9 mil region) of bonding pad, and then influence follow-up bonding quality, can't satisfy bonding IC's high accuracy processing requirement.
The PCB product with the bonding IC designed in the board adopts the existing engineering design and processing parameters, and mainly faces the following problems:
1. the position of the bonded IC is designed according to conventional equal-width compensation of engineering data (as shown in figure 1), the position of the bonded IC is easy to have a thin line after etching, the top position of the IC is easy to form a 'needle point' effect (as shown in figure 3), and the high-precision requirement of the line width of the bonded IC cannot be met.
2. In the etching process, the outermost IC bonding pad is affected by the flow rate of the etching solution, and the position with large space is easy to be over-etched, so that the outer IC bonding pad is smaller than the inner bonding pad with the same width by about 0.5mil, and the requirement of the consistency of the line width of the bonded IC (plus or minus 10%) cannot be met.
Disclosure of Invention
In view of the above, the present invention provides a control method for improving etching accuracy of bonded ICs.
The technical scheme of the invention is as follows:
a control method for improving etching precision of a bonding IC is characterized by comprising the following steps:
s1, establishing a simulation compensation model according to the etching form change of a bonding IC;
s2, setting bonding IC compensation; performing at least three-level gradient compensation on the bonding IC bonding pad according to the simulation compensation model;
s3, etching the bonding IC; including performing two etches.
By the processing method, etching line fineness of the bonded IC can be improved, a needle point effect formed at the top of the IC can be solved, and etching precision and consistency of the bonded IC can be effectively improved.
Further, in step S1, the method for establishing the simulation compensation model includes the following steps:
s11, testing the IC pad in a segmented mode; measuring the etched bonding pad in sections, and measuring data 1 time at intervals of 1.0mil in the range of 12 mils in the windowing area;
and S12, establishing a graded gradient compensation model according to the IC line width etching change trend measured in the step S11 and by combining the etching difference value between 1 and 6mil intervals of the top of the IC.
Further, step S2 includes bonding the outermost region of the IC with equidistant dummy pads. In the invention, the outermost pad of the bonded IC is influenced by peripheral wiring, and an unequal-distance design may exist, and the unequal-distance design influences the etching uniformity during etching, so that the outermost pad is over-etched and has a thin line, and therefore, equidistant dummy pads need to be added in the outermost area of the IC or the extremely difference of the IC distance is controlled within 0.5 mil.
Further, in step S2, the method for bonding IC compensation includes the following steps:
s21, firstly, carrying out 1 st-level compensation according to the etching line width lateral etching amount, and integrally compensating the circuit and the IC bonding pad for 1.5-2mil according to the copper thickness difference;
and S22, performing multi-stage compensation on the 1-6mil area at the top of the bonding IC pad according to the simulation compensation model.
Further, step S22 includes 6 levels of refinement compensation, and each additional compensation is performed by 0.1-0.2mil.
Further, step S22 includes simplified compensation of 3 stages, and the compensation is added by 0.2-0.4mil each time one stage is added.
Further, step S3 includes a first etching step and a second precise etching step using vacuum acid.
Further, the spraying pressure of the vacuum acid primary etching is set to be 1-1.5kg/cm 2， Thereby improving the etching factor and reducing the line width side etching.
Further, the etching speed matched with the copper thickness is selected through secondary accurate etching, after the first etching is finished, the copper thickness tester is used for detecting the residual copper thickness on the board surface, the etching parameters are adjusted according to the copper thickness, and the overturning surface carries out secondary accurate etching backwards, so that the requirements of consistency and high-precision tolerance of the line width of the bound IC are met.
Further, step S3 includes the following steps: selecting a matched etching speed according to the copper thickness, adopting a twice fine etching process, etching according to 80-90% of the copper thickness for the first time, detecting the residual copper thickness on the surface by using a copper thickness tester after etching, adjusting etching parameters according to the copper thickness, and performing second-time precise etching after the surface is turned over, thereby meeting the requirements of the consistency and the high-precision tolerance of the line width of the bound IC.
The invention has the beneficial effects that:
according to the method, the simulation model is established according to the etching form of the bonded IC, and then three-level gradient compensation is carried out on the top position of the bonded IC according to the simulation model, and the equidistant dummy bonding pad is added on the outermost side, so that the problems of thin etching lines, top end needle point effect and the like of the bonded IC are solved, the etching precision of the bonded IC is improved, and the yield of products is improved from 50% to more than 98%.
Drawings
FIG. 1 is a schematic structural diagram of a prior art equal-width etching method;
FIG. 2 is a schematic structural diagram of a compensation etching method according to the present invention;
FIG. 3 is a schematic structural diagram of a product prepared by a prior art equal-width etching method;
FIG. 4 is a schematic structural diagram of a product manufactured by the compensation etching method of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Example 1
A control method for improving etching precision of a bonding IC is characterized by comprising the following steps:
s1, establishing a simulation compensation model according to the etching form change of a bound IC;
s2, setting bonding IC compensation; performing at least three-level gradient compensation on the bonding IC bonding pad according to the simulation compensation model;
s3, etching the bonding IC; including performing two etches.
By the processing method, etching line fineness of the bonded IC can be improved, a needle point effect formed at the top of the IC can be solved, and etching precision and consistency of the bonded IC can be effectively improved.
Further, in step S1, the method for establishing the simulation compensation model includes the following steps:
s11, testing the IC pad in a segmented mode; measuring the etched bonding pad in sections, and measuring data 1 time at intervals of 1.0mil in the range of 12 mils in the windowing area; the test results obtained are shown in table 1 below:
TABLE 1 bonding IC etching precision test result table
From a trend chart, the length of the bonding IC pad is 12 mils, the change is small in the range of 7-12 mils, the bonding IC pad can be adjusted through 1-level compensation, the bonding IC pad is gradually decreased in the range of 1-6 mils at the top, and the needle point effect can be improved only by adopting a multi-level compensation mode.
And S12, establishing a graded gradient compensation model according to the IC line width etching change trend measured in the step S11 and by combining the etching difference value between 1 and 6mil intervals of the top of the IC.
Further, step S2 includes bonding the outermost region of the IC with equidistant dummy pads. In the invention, the outermost pad of the bonded IC is influenced by peripheral wiring, and an unequal-distance design may exist, and the unequal-distance design influences the etching uniformity during etching, so that the outermost pad is over-etched and has a thin line, and therefore, equidistant dummy pads need to be added in the outermost area of the IC or the extremely difference of the IC distance is controlled within 0.5 mil.
Further, in step S2, the method for bonding IC compensation includes the following steps:
s21, firstly, carrying out 1 st-level compensation according to the etching line width lateral etching amount, and integrally compensating the circuit and the IC bonding pad for 1.5-2mil according to the copper thickness difference;
and S22, performing multi-stage compensation on the 1-6mil area at the top of the bonding IC pad according to the simulation compensation model.
Further, step S22 includes 6 levels of refinement compensation, and each additional compensation is performed by 0.1-0.2mil.
Further, step S3 includes a first etching step and a second precise etching step using vacuum acid.
Further, the spraying pressure of the vacuum acid primary etching is set to be 1-1.5kg/cm 2， Thereby improving the etching factor and reducing the line width side etching.
Further, the etching speed matched with the copper thickness is selected through secondary accurate etching, after the first etching is finished, the copper thickness tester is used for detecting the residual copper thickness on the board surface, the etching parameters are adjusted according to the copper thickness, and the overturning surface carries out secondary accurate etching backwards, so that the requirements of consistency and high-precision tolerance of the line width of the bound IC are met.
Further, step S3 includes the following steps: selecting a matched etching speed according to the copper thickness, adopting a twice fine etching process, etching according to 80-90% of the copper thickness for the first time, detecting the residual copper thickness on the board surface by using a copper thickness tester after etching, adjusting etching parameters according to the copper thickness, and performing second accurate etching after turning the board surface backwards, thereby meeting the requirements of the consistency and high-precision tolerance of the wire width of the bonded IC.
Example 2
This embodiment provides a control method for improving the etching accuracy of bonded ICs similar to embodiment 1, except that in step S22, a simplified compensation of 3 stages is included, and a compensation of 0.2-0.4mil is added for each stage.
Example 3
A control method for improving etching precision of a bonding IC is characterized by comprising the following steps:
s1, establishing a simulation compensation model according to the etching form change of a bound IC;
s2, setting bonding IC compensation; performing three-level gradient compensation on the bonding IC bonding pad according to the simulation compensation model;
s3, etching the bonding IC; including performing two etches.
By the processing method, etching line fineness of the bonded IC can be improved, a needle point effect formed at the top of the IC can be solved, and etching precision and consistency of the bonded IC can be effectively improved.
Further, in step S1, the etching morphology change was changed from 4.0mil before compensation to 5.5mil after compensation.
Further, step S2 includes bonding the outermost region of the IC with equidistant dummy pads.
Further, in step S2, the three-stage gradient compensation includes:
performing first-stage compensation according to the line width lateral erosion amount;
performing second-stage compensation according to the etching needle point effect;
and adding compensation on the basis of the second-stage compensation, and performing third-stage compensation.
Further, the first stage compensation is from 4.0mil line width to 5.7mil.
Furthermore, the second-stage compensation is enlarged to 6.1mil from the position 3.0-6.0mil away from the top of the IC, namely, the second-stage compensation is added with 0.4mil on the basis of the first-stage compensation.
Furthermore, the third-stage compensation is enlarged to 6.5mil from the position of 0-3.0mil from the top of the IC, namely, the compensation is additionally added to 0.4mil on the basis of the second-stage compensation.
Further, step S3 includes a first etching step and a second precision etching step using vacuum acid.
Further, the spraying pressure of the vacuum acidic primary etching is set to be 1-1.5kg/cm 2， Thereby improving the etching factor and reducing the line width side etching.
Further, the etching speed matched with the copper thickness is selected through secondary accurate etching, after the first etching is finished, the copper thickness tester is used for detecting the residual copper thickness on the board surface, the etching parameters are adjusted according to the copper thickness, and the overturning surface carries out secondary accurate etching backwards, so that the requirements of consistency and high-precision tolerance of the line width of the bound IC are met.
Example 4
A control method for improving etching precision of a bonding IC comprises the following steps: 1, cutting: and cutting according to the requirements of the laminated structure, the size and the quantity of the engineering MI.
2. Baking the plate: according to the conventional baking parameters: baking at 150 deg.C for 2-4 hr.
3. Inner layer pretreatment: and coarsening and cleaning the copper surface by adopting an inner layer coarsening mode.
4. Manufacturing an inner layer circuit: and (3) pasting dry films on two sides, transferring the patterns according to MI inner layer circuit files in an LDI laser imaging mode, and developing to obtain inner layer circuit patterns.
5. Inner layer etching: and selecting matched parameters for etching according to the thickness of the copper of the MI inner layer, and etching the copper surface without the dry film protection.
6. Inner layer film removing: and after the inner layer is etched, the film removing machine is horizontally arranged to remove the surface dry film.
7. Inner layer corrosion detection: and (4) removing the protective frame, and then using an AOI machine to inspect the internal wiring after etching and film stripping.
8. Brown oxidation of the inner layer: and the copper surface is coarsened and cleaned after passing through the brown oxide line of the inner layer, so that the lamination binding force is improved.
9. Pre-stacking and riveting: pre-stacking according to the MI laminated structure, riveting, and riveting all the tool holes on the edges of the plate during riveting.
10. And (3) laminating: and selecting a matched pressing program to perform vacuum pressing according to the PP characteristics.
11. Drilling: and (4) according to the project MI drilling file, drilling the pressed printed board.
12. Copper deposition and electroplating: the copper plate is manufactured according to the requirements of the engineering MI, the requirements of the copper plate and the hole copper of a client are met, and the thickness tolerance of the copper plate is controlled according to +/-5 microns.
13. Outer layer circuit: and (3) pasting a dry film on both sides, transferring the pattern according to the MI external line data file by adopting an LDI laser imaging mode, and developing to obtain an outer layer circuit pattern.
14. Acid etching: A. producing by adopting an acid vacuum etching machine; B. before etching, the upper and lower etching pressures were adjusted to 1.2kg/cm 2 Adjusting the etching speed according to the thickness of copper on different surfaces; C. in the secondary accurate etching mode, after the primary etching is finished, the thickness of the residual copper on the board surface is detected by using a copper thickness tester, and then the board surface is turned backwards to perform secondary accurate etching according to the copper thickness adjusting parameter; D. the IC etching precision is measured after etching, and the line width is controlled by a tolerance of plus 0 to plus 0.4mil, such as the standard value of 4.0mil, and the value after etching is 4.1-4.4mil.
15. And subsequently, processing according to the conventional PCB flow until a finished product is inspected.
Effect testing
By the processing method, the original negative tolerance of the line width on the IC is changed into the positive tolerance of the line width on the IC, the problems of thin etching line, top end needle point effect and the like of the bound IC are effectively solved, the etching precision of the bound IC is improved, and the yield of products is improved from 50% to more than 98%.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art. It should be noted that the technical features not described in detail in the present invention can be implemented by any prior art.
Claims (10)
1. A control method for improving etching precision of a bonding IC is characterized by comprising the following steps:
s1, establishing a simulation compensation model according to the etching form change of a bound IC;
s2, setting bonding IC compensation; performing at least three-level gradient compensation on the bonding IC bonding pad according to the simulation compensation model;
s3, etching the bonding IC; including performing two etches.
2. The control method for improving etching precision of a bonded IC according to claim 1, wherein in step S1, the method for establishing the simulation compensation model includes the following steps:
s11, testing the IC pad in a segmented mode; measuring the etched bonding pad in sections, and measuring data 1 time at intervals of 1.0mil in the range of 12 mils in the windowing area;
and S12, establishing a graded gradient compensation model by combining the etching difference value between 1 and 6mil intervals at the top of the IC according to the IC line width etching change trend measured in the step S11.
3. The control method for improving etching precision of bonding ICs, according to claim 1, wherein step S2 further comprises bonding the dummy pads at the outermost region of the ICs with equal spacing.
4. The control method for improving etching precision of bound ICs according to claim 2, wherein in step S2, the method for compensating bound ICs includes the following steps:
s21, firstly, carrying out 1 st-level compensation according to the etching line width lateral etching amount, and integrally compensating the circuit and the IC bonding pad for 1.5-2mil according to the copper thickness difference;
and S22, performing multi-stage compensation on the 1-6mil area at the top of the bonding IC bonding pad according to the simulation compensation model.
5. The control method for improving etching precision of bonding IC according to claim 4, wherein step S22 includes 6 levels of fine compensation, and each additional level of compensation is 0.1-0.2mil.
6. The control method for improving etching precision of bonding IC according to claim 4, wherein step S22 includes 3 stages of simplified compensation, and each additional stage of simplified compensation is added by 0.2-0.4mil.
7. The control method for improving bonding IC etching precision according to claim 1, wherein step S3 includes a first etching step and a second etching step using vacuum acid.
8. The control method for improving bonding IC etching precision of claim 7, wherein the vacuum acidic primary etching sets a spraying pressure of 1-1.5kg/cm 2 。
9. The control method for improving etching precision of a bonding IC according to claim 8, wherein the second precision etching selects a matched etching speed according to the copper thickness, after the first etching is finished, the copper thickness tester is used for detecting the residual copper thickness on the board surface, then the etching parameters are adjusted according to the copper thickness, and the second precision etching is carried out after the board surface is turned over.
10. The control method for improving etching precision of bonding IC according to claim 1, wherein step S3 includes the following steps: selecting a matched etching speed according to the copper thickness, adopting a twice fine etching process, etching according to 80-90% of the copper thickness for the first time, detecting the residual copper thickness on the surface by using a copper thickness tester after etching, adjusting etching parameters according to the copper thickness, and performing second-time precise etching after the surface is turned over, thereby meeting the requirements of the consistency and the high-precision tolerance of the line width of the bound IC.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211443146.4A CN115580994A (en) | 2022-11-18 | 2022-11-18 | Control method for improving etching precision of bonding IC |
| PCT/CN2022/138618 WO2024103472A1 (en) | 2022-11-18 | 2022-12-13 | Control method for improving bonding ic etching precision |
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| CN202211443146.4A CN115580994A (en) | 2022-11-18 | 2022-11-18 | Control method for improving etching precision of bonding IC |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200428913A (en) * | 2003-06-11 | 2004-12-16 | Phoenix Prec Technology Corp | Circuit board having patterned trace with enhanced precision and method for fabricating the same |
| JP2013258351A (en) * | 2012-06-14 | 2013-12-26 | Shindo Denshi Kogyo Kk | Wiring board and manufacturing method of the same |
| CN104010445A (en) * | 2014-05-09 | 2014-08-27 | 东莞市五株电子科技有限公司 | Dynamic compensation manufacturing method for fine circuit |
| CN106455325A (en) * | 2016-09-27 | 2017-02-22 | 惠州市金百泽电路科技有限公司 | Manufacturing method of 77Ghz high-precision radio radar printed circuit board |
| CN106973514A (en) * | 2017-03-10 | 2017-07-21 | 江门崇达电路技术有限公司 | PAD preparation method in a kind of PCB |
| CN113093469A (en) * | 2020-01-08 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for correcting target pattern, manufacturing mask and forming semiconductor structure |
| CN114423168A (en) * | 2021-12-10 | 2022-04-29 | 西安金百泽电路科技有限公司 | Control method for etching line width of thick copper circuit board |
| CN217721592U (en) * | 2022-06-21 | 2022-11-01 | 珠海市凯诺微电子有限公司 | FPC prevents pad overetching's pad structure in IC paster position |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573309A (en) * | 2012-01-13 | 2012-07-11 | 东莞生益电子有限公司 | Method for improving graphic precision of substractive process printed circuit board (PCB) by adopting dynamic etching compensation method |
| CN110119061B (en) * | 2018-02-06 | 2022-08-23 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method and manufacturing method of mask |
-
2022
- 2022-11-18 CN CN202211443146.4A patent/CN115580994A/en active Pending
- 2022-12-13 WO PCT/CN2022/138618 patent/WO2024103472A1/en unknown
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200428913A (en) * | 2003-06-11 | 2004-12-16 | Phoenix Prec Technology Corp | Circuit board having patterned trace with enhanced precision and method for fabricating the same |
| JP2013258351A (en) * | 2012-06-14 | 2013-12-26 | Shindo Denshi Kogyo Kk | Wiring board and manufacturing method of the same |
| CN104010445A (en) * | 2014-05-09 | 2014-08-27 | 东莞市五株电子科技有限公司 | Dynamic compensation manufacturing method for fine circuit |
| CN106455325A (en) * | 2016-09-27 | 2017-02-22 | 惠州市金百泽电路科技有限公司 | Manufacturing method of 77Ghz high-precision radio radar printed circuit board |
| CN106973514A (en) * | 2017-03-10 | 2017-07-21 | 江门崇达电路技术有限公司 | PAD preparation method in a kind of PCB |
| CN113093469A (en) * | 2020-01-08 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for correcting target pattern, manufacturing mask and forming semiconductor structure |
| CN114423168A (en) * | 2021-12-10 | 2022-04-29 | 西安金百泽电路科技有限公司 | Control method for etching line width of thick copper circuit board |
| CN217721592U (en) * | 2022-06-21 | 2022-11-01 | 珠海市凯诺微电子有限公司 | FPC prevents pad overetching's pad structure in IC paster position |
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| WO2024103472A1 (en) | 2024-05-23 |
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Application publication date: 20230106 |