WO2024103472A1 - Control method for improving bonding ic etching precision - Google Patents

Control method for improving bonding ic etching precision Download PDF

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WO2024103472A1
WO2024103472A1 PCT/CN2022/138618 CN2022138618W WO2024103472A1 WO 2024103472 A1 WO2024103472 A1 WO 2024103472A1 CN 2022138618 W CN2022138618 W CN 2022138618W WO 2024103472 A1 WO2024103472 A1 WO 2024103472A1
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etching
bonding
compensation
control method
improving
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PCT/CN2022/138618
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French (fr)
Chinese (zh)
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徐得刚
唐宏华
樊廷慧
王斌
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惠州市金百泽电路科技有限公司
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

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  • the invention belongs to the technical field of PCB, and in particular relates to a control method for improving the etching accuracy of bonding IC.
  • Bonding is a wire bonding method in the chip production process. It is generally used to connect the internal circuit of the chip with the package pin or the IC gold-plated pad of the PCB with gold wire or aluminum wire before packaging. With the increase in PCB wiring density, the size of the bonding IC pad is becoming more and more refined. The pad size of 12mil long and 4mil wide has become a conventional design. For this type of PCB printed boards with bonded ICs, if the line width compensation and conventional etching parameters are used for production according to conventional processing methods, the bonding IC part is prone to thin lines, and the upper line width is basically below the negative tolerance.
  • the engineering data is designed according to the conventional equal width compensation (as shown in Figure 1). After etching, the bonding IC position is prone to thin lines, and the top position of the IC is prone to form a "needle tip" effect (as shown in Figure 3), which cannot meet the high-precision requirements of the bonding IC line width.
  • the outermost IC pads are affected by the flow rate of the etching solution, and the positions with large spacing are prone to over-etching, resulting in the outer IC pads being about 0.5 mil smaller than the inner pads of the same width, which cannot meet the consistency requirements of the bonding IC line width ( ⁇ 10%).
  • the present invention provides a control method for improving the etching accuracy of bonding ICs.
  • a control method for improving the etching accuracy of a bonding IC characterized by comprising the following steps:
  • the processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
  • step S1 the method for establishing the simulation compensation model includes the following:
  • S11, IC pad segment test perform segmented measurement on the bonding pad after etching, and measure the data once every 1.0mil interval within the 12mil window area;
  • step S12 according to the IC line width etching variation trend measured in step S11, combined with the etching difference value in the range of 1-6 mil at the top of the IC, a graded gradient compensation model is established.
  • step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC.
  • the outermost pads of the bonding IC may be unequally spaced due to the influence of the surrounding wiring. Such unequally spaced designs may affect the etching uniformity during etching, thereby causing the outermost pads to have excessive side etching and thin lines. Therefore, it is necessary to add equidistant dummy pads to the outermost area of the IC or control the IC spacing range to be within 0.5 mil.
  • step S2 the method of bonding IC compensation includes the following:
  • step S22 6 levels of refined compensation are included, and each additional level provides additional compensation of 0.1-0.2 mil.
  • step S22 three levels of simplified compensation are included, and each additional level provides an additional compensation of 0.2-0.4 mil.
  • step S3 includes vacuum acid primary etching and secondary precision etching.
  • the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
  • the secondary precision etching selects a matching etching speed according to the copper thickness.
  • a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness.
  • the surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
  • step S3 includes the following steps: selecting a matching etching speed according to the copper thickness, adopting two fine etching processes, etching at 80-90% of the copper thickness for the first time, using a copper thickness tester to detect the residual copper thickness on the board surface after etching, and then adjusting the etching parameters according to the copper thickness, flipping the surface back and performing a second precise etching, so as to meet the consistency and high-precision tolerance requirements of the bonded IC line width.
  • the present invention establishes a simulation model according to the bonding IC etching morphology, and then performs three-level gradient compensation + adding equidistant false pads on the outermost side at the top of the bonding IC according to the simulation model, thereby improving the problems of thin bonding IC etching line and top needle tip effect, and improving the bonding IC etching accuracy, and the product yield is increased from 50% to more than 98%.
  • FIG1 is a schematic structural diagram of a conventional equal-width etching method
  • FIG2 is a schematic structural diagram of a compensating etching method according to the present invention.
  • FIG3 is a schematic diagram of a product structure prepared by a conventional equal-width etching method
  • FIG. 4 is a schematic diagram of the product structure prepared by the compensating etching method of the present invention.
  • a control method for improving the etching accuracy of a bonding IC characterized by comprising the following steps:
  • the processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
  • step S1 the method for establishing the simulation compensation model includes the following:
  • the length of the bonding IC pad is 12 mil, with little variation in the range of 7-12 mil. It can be adjusted through 1-level compensation and decreases gradually in the top range of 1-6 mil. Multi-level compensation is required to improve the "needle tip" effect.
  • step S12 According to the IC line width etching variation trend measured in step S11, a graded gradient compensation model is established in combination with the etching difference value in the 1-6 mil range at the top of the IC.
  • step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC.
  • the outermost pads of the bonding IC may be unequally spaced due to the influence of the surrounding wiring. Such unequally spaced designs may affect the etching uniformity during etching, thereby causing the outermost pads to have excessive side etching and thin lines. Therefore, it is necessary to add equidistant dummy pads to the outermost area of the IC or control the IC spacing range to be within 0.5 mil.
  • step S2 the method of bonding IC compensation includes the following:
  • step S22 6 levels of refined compensation are included, and each additional level provides additional compensation of 0.1-0.2 mil.
  • step S3 includes vacuum acid primary etching and secondary precision etching.
  • the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
  • the secondary precision etching selects a matching etching speed according to the copper thickness.
  • a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness.
  • the surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
  • step S3 includes the following steps: selecting a matching etching speed according to the copper thickness, adopting two fine etching processes, etching at 80-90% of the copper thickness for the first time, using a copper thickness tester to detect the residual copper thickness on the board surface after etching, and then adjusting the etching parameters according to the copper thickness, flipping the surface back and performing a second precise etching, so as to meet the consistency and high-precision tolerance requirements of the bonded IC line width.
  • This embodiment provides a control method for improving the etching accuracy of bonding ICs that is the same as that of Embodiment 1, except that, further, in step S22, three levels of simplified compensation are included, and each additional level provides an additional compensation of 0.2-0.4 mil.
  • a control method for improving the etching accuracy of a bonding IC characterized by comprising the following steps:
  • the processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
  • step S1 the etching morphology changes from 4.0 mil before compensation to 5.5 mil after compensation.
  • step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC.
  • step S2 the three-level gradient compensation includes:
  • the second level compensation is carried out
  • Additional compensation will be made on the basis of the second level compensation to provide the third level compensation.
  • the first level compensation is to compensate the line width from 4.0 mil to 5.7 mil.
  • the second level compensation is increased to 6.1 mil at a position 3.0-6.0 mil from the top of the IC, that is, an additional compensation of 0.4 mil is added on the basis of the first level compensation.
  • the third level compensation is increased to 6.5 mil at a position 0-3.0 mil from the top of the IC, that is, an additional compensation of 0.4 mil is added on the basis of the second level compensation.
  • step S3 includes vacuum acid primary etching and secondary precision etching.
  • the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
  • the secondary precision etching selects a matching etching speed according to the copper thickness.
  • a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness.
  • the surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
  • a control method for improving the etching accuracy of bonding IC includes the following steps: 1. Cutting: cutting is performed according to the stacking structure and the size and quantity requirements of the engineering MI.
  • Baking plate follow the conventional baking plate parameters: bake at 150°C for 2-4 hours.
  • Inner layer pretreatment Use inner layer roughening method to roughen and clean the copper surface.
  • Inner layer circuit production double-sided dry film, according to the MI inner layer circuit file, use LDI laser imaging method to transfer the pattern, and get the inner layer circuit pattern after development.
  • Inner layer etching According to the inner layer copper thickness of MI, select matching parameters for etching to corrode the copper surface without dry film protection.
  • Inner layer stripping After the inner layer is etched, it is passed through a horizontal stripping machine to remove the dry film on the surface.
  • Inner layer etching inspection Remove the protective frame, and then use the AOI machine to inspect the inner line after etching and film stripping.
  • Inner layer browning Through the inner layer browning line, the copper surface is roughened and cleaned to improve the bonding strength of the lamination.
  • Pre-stack and rivet Pre-stack according to the MI stacking structure, and then rivet. When riveting, all encrypted tool holes on the edge of the plate are riveted.
  • Pressing According to the characteristics of PP, select the matching pressing program for vacuum pressing.
  • Drilling Drill holes on the laminated printed circuit board according to the engineering MI drilling file.
  • Copper plating and electroplating Made according to the engineering MI requirements to meet the customer's surface copper and hole copper requirements. The surface copper thickness tolerance is controlled at ⁇ 5um.
  • Outer circuit Double-sided dry film is applied, and the pattern is transferred by LDI laser imaging according to the MI outer line data file, and the outer circuit pattern is obtained after development.
  • Acid etching A. Use acid vacuum etcher for production; B. Adjust the upper and lower pressures of etching to 1.2kg/ cm2 before etching, and adjust the etching speed according to the copper thickness on different surfaces; C. Secondary precision etching method. After the first etching, use a copper thickness tester to detect the residual copper thickness on the board surface, and then adjust the parameters according to the copper thickness, flip the surface back for the second precision etching; D. Measure the IC etching accuracy after etching, and control the upper line width with a tolerance of +0 to +0.4mil. For example, the standard value is 4.0mil, and the value after etching is 4.1-4.4mil.
  • the original negative tolerance of the line width on the IC is changed to a positive tolerance of the line width on the IC, which effectively improves the problems of thin IC etching lines and top needle tip effect, improves the etching accuracy of the IC bonding, and increases the product yield from 50% to more than 98%.

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Abstract

A control method for improving bonding IC etching precision, comprising the following steps: S1, establishing a simulation compensation model according to a bonding IC etching form change; S2, setting bonding IC compensation, and performing at least three stages of gradient compensation on a bonding IC pad according to the simulation compensation model; and S3, performing bonding IC etching, comprising two etchings.

Description

一种提高邦定IC蚀刻精度的控制方法A control method for improving IC bonding etching accuracy 技术领域Technical Field
本发明属于PCB技术领域，具体涉及一种提高邦定IC蚀刻精度的控制方法。The invention belongs to the technical field of PCB, and in particular relates to a control method for improving the etching accuracy of bonding IC.
背景技术Background technique
邦定是芯片生产工艺中一种打线的方式，一般用于封装前将芯片内部电路用金线或铝线与封装管脚或PCB的IC镀金焊盘连接。随着PCB布线密度增加，邦定IC焊盘尺寸越来越精细化，长12mil*宽4mil的焊盘尺寸，已成为常规化设计，针对此类设计有邦定IC的PCB印制板，如按常规加工方式进行线宽补偿及常规蚀刻参数进行生产，邦定IC部位容易线细，上线宽基本在负公差以下，尤其常规等宽补偿，蚀刻后在IC顶部位置易形成“针尖”效应，对邦定焊盘的中间50％核心部位(3-9mil区域)造成影响，进而影响后续邦定质量，无法满足邦定IC的高精度加工要求。Bonding is a wire bonding method in the chip production process. It is generally used to connect the internal circuit of the chip with the package pin or the IC gold-plated pad of the PCB with gold wire or aluminum wire before packaging. With the increase in PCB wiring density, the size of the bonding IC pad is becoming more and more refined. The pad size of 12mil long and 4mil wide has become a conventional design. For this type of PCB printed boards with bonded ICs, if the line width compensation and conventional etching parameters are used for production according to conventional processing methods, the bonding IC part is prone to thin lines, and the upper line width is basically below the negative tolerance. Especially with conventional equal width compensation, it is easy to form a "needle tip" effect at the top of the IC after etching, which affects the middle 50% core part (3-9mil area) of the bonding pad, and then affects the subsequent bonding quality, and cannot meet the high-precision processing requirements of the bonded IC.
针对板内设计有邦定IC的PCB产品，采用现有工程设计及加工参数，主要面临以下问题：For PCB products with bonded ICs designed in the board, the following problems are faced by using existing engineering design and processing parameters:
1、邦定IC位置，工程资料按常规等宽补偿进行设计(如图1所示)，蚀刻后邦定IC位置容易出现线细，IC顶部位置易形成“针尖”效应(如图3所示)，无法满足邦定IC线宽的高精度要求。1. For the bonding IC position, the engineering data is designed according to the conventional equal width compensation (as shown in Figure 1). After etching, the bonding IC position is prone to thin lines, and the top position of the IC is prone to form a "needle tip" effect (as shown in Figure 3), which cannot meet the high-precision requirements of the bonding IC line width.
2、蚀刻过程中，最外侧的IC焊盘，受蚀刻液流速影响，间距大的位置容易过蚀刻，导致外侧的IC焊盘比内侧等宽的焊盘偏小约0.5mil，无法满足邦定IC线宽的一致性要求(±10％)。2. During the etching process, the outermost IC pads are affected by the flow rate of the etching solution, and the positions with large spacing are prone to over-etching, resulting in the outer IC pads being about 0.5 mil smaller than the inner pads of the same width, which cannot meet the consistency requirements of the bonding IC line width (±10%).
发明内容Summary of the invention
有鉴于此，本发明提供一种提高邦定IC蚀刻精度的控制方法。In view of this, the present invention provides a control method for improving the etching accuracy of bonding ICs.
本发明的技术方案为：The technical solution of the present invention is:
一种提高邦定IC蚀刻精度的控制方法，其特征在于，包括以下步骤：A control method for improving the etching accuracy of a bonding IC, characterized by comprising the following steps:
S1、跟据邦定IC蚀刻形态变化建立仿真补偿模型；S1. Establish a simulation compensation model according to the changes in the bonding IC etching morphology;
S2、设置邦定IC补偿；根据仿真补偿模型，对邦定IC焊盘进行至少三级梯度补偿；S2. Set bonding IC compensation; perform at least three levels of gradient compensation on the bonding IC pad according to the simulation compensation model;
S3、进行邦定IC蚀刻；包括进行两次蚀刻。S3, performing bonding IC etching; including performing two etching steps.
通过本发明的加工方法，可以改善邦定IC蚀刻线细及解决IC顶部位置形成的针尖效应，有效提升邦定IC蚀刻精度及一致性。The processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
进一步的，步骤S1中，仿真补偿模型建立的方法包括以下：Furthermore, in step S1, the method for establishing the simulation compensation model includes the following:
S11、IC焊盘分段测试；对蚀刻后的邦定焊盘进行分段测量，在开窗区域12mil范围内，每间 隔1.0mil测量1次数据；S11, IC pad segment test: perform segmented measurement on the bonding pad after etching, and measure the data once every 1.0mil interval within the 12mil window area;
S12、根据步骤S11中测得的IC线宽蚀刻变化趋势，结合IC顶部1-6mil区间的蚀刻差异值建立分级梯度补偿模型。S12, according to the IC line width etching variation trend measured in step S11, combined with the etching difference value in the range of 1-6 mil at the top of the IC, a graded gradient compensation model is established.
进一步的，步骤S2中，还包括邦定IC最外侧区域增加等距的假焊盘。本发明中，邦定IC最外侧焊盘，受周边布线影响，可能存在不等距设计，此类不等距设计，在蚀刻时会影响蚀刻均匀性，进而造成最外侧焊盘出现侧蚀过大线细，因此需在IC最外侧区域增加等距的假焊盘或控制IC间距极差在0.5mil以内。Furthermore, step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC. In the present invention, the outermost pads of the bonding IC may be unequally spaced due to the influence of the surrounding wiring. Such unequally spaced designs may affect the etching uniformity during etching, thereby causing the outermost pads to have excessive side etching and thin lines. Therefore, it is necessary to add equidistant dummy pads to the outermost area of the IC or control the IC spacing range to be within 0.5 mil.
进一步的，步骤S2中，邦定IC补偿的方法包括以下：Further, in step S2, the method of bonding IC compensation includes the following:
S21、先根据蚀刻线宽侧蚀量进行第1级补偿，视铜厚差异，线路及IC焊盘整体补偿1.5-2mil；S21, firstly make the first level compensation according to the etching line width side etching amount, and according to the difference in copper thickness, the circuit and IC pad are compensated by 1.5-2mil as a whole;
S22、根据仿真补偿模型，对邦定IC焊盘顶部位置1-6mil区域进行多级补偿。S22. Perform multi-level compensation on the 1-6 mil area at the top of the bonding IC pad according to the simulation compensation model.
进一步的，步骤S22中，包括6级的精细化补偿，每增加一级，追加补偿0.1-0.2mil。Furthermore, in step S22, 6 levels of refined compensation are included, and each additional level provides additional compensation of 0.1-0.2 mil.
进一步的，步骤S22中，包括3级的简化补偿，每增加一级，追加补偿0.2-0.4mil。Furthermore, in step S22, three levels of simplified compensation are included, and each additional level provides an additional compensation of 0.2-0.4 mil.
进一步的，步骤S3中，包括采用真空酸性一次蚀刻以及二次精准蚀刻。Furthermore, step S3 includes vacuum acid primary etching and secondary precision etching.
进一步的，所述真空酸性一次蚀刻设置喷淋压力为1-1.5kg/cm 2，从而提升蚀刻因子，减少线宽侧蚀。 Furthermore, the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
进一步的，所述二次精准蚀刻，根据铜厚选择匹配的蚀刻速度，第一次蚀刻完后，使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。Furthermore, the secondary precision etching selects a matching etching speed according to the copper thickness. After the first etching, a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness. The surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
进一步的，步骤S3中，包括以下步骤：根据铜厚选择匹配的蚀刻速度，采用两次精蚀工艺，第一次按铜厚的80-90％进行蚀刻，蚀刻完后使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。Furthermore, step S3 includes the following steps: selecting a matching etching speed according to the copper thickness, adopting two fine etching processes, etching at 80-90% of the copper thickness for the first time, using a copper thickness tester to detect the residual copper thickness on the board surface after etching, and then adjusting the etching parameters according to the copper thickness, flipping the surface back and performing a second precise etching, so as to meet the consistency and high-precision tolerance requirements of the bonded IC line width.
本发明的有益效果在于：The beneficial effects of the present invention are:
本发明根据邦定IC蚀刻形态建立仿真模型，然后按仿真模型在邦定IC顶部位置进行三级梯度补偿+最外侧增加等距假焊盘方式，从而改善邦定IC蚀刻线细及顶端针尖效应等问题，提升邦定IC蚀刻精度，产品良率由50％提高到98％以上。The present invention establishes a simulation model according to the bonding IC etching morphology, and then performs three-level gradient compensation + adding equidistant false pads on the outermost side at the top of the bonding IC according to the simulation model, thereby improving the problems of thin bonding IC etching line and top needle tip effect, and improving the bonding IC etching accuracy, and the product yield is increased from 50% to more than 98%.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为现有技术等宽蚀刻方法的结构示意图；FIG1 is a schematic structural diagram of a conventional equal-width etching method;
图2为本发明补偿蚀刻方法的结构示意图；FIG2 is a schematic structural diagram of a compensating etching method according to the present invention;
图3为现有技术等宽蚀刻方法制备的产品结构示意图；FIG3 is a schematic diagram of a product structure prepared by a conventional equal-width etching method;
图4为本发明补偿蚀刻方法制备的产品结构示意图。FIG. 4 is a schematic diagram of the product structure prepared by the compensating etching method of the present invention.
具体实施方式Detailed ways
下面将结合实施例对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
实施例1Example 1
一种提高邦定IC蚀刻精度的控制方法，其特征在于，包括以下步骤：A control method for improving the etching accuracy of a bonding IC, characterized by comprising the following steps:
S1、跟据邦定IC蚀刻形态变化建立仿真补偿模型；S1. Establish a simulation compensation model according to the changes in the bonding IC etching morphology;
S2、设置邦定IC补偿；根据仿真补偿模型，对邦定IC焊盘进行至少三级梯度补偿；S2, setting bonding IC compensation; performing at least three levels of gradient compensation on the bonding IC pad according to the simulation compensation model;
S3、进行邦定IC蚀刻；包括进行两次蚀刻。S3, performing bonding IC etching; including performing two etching steps.
通过本发明的加工方法，可以改善邦定IC蚀刻线细及解决IC顶部位置形成的针尖效应，有效提升邦定IC蚀刻精度及一致性。The processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
进一步的，步骤S1中，仿真补偿模型建立的方法包括以下：Furthermore, in step S1, the method for establishing the simulation compensation model includes the following:
S11、IC焊盘分段测试；对蚀刻后的邦定焊盘进行分段测量，在开窗区域12mil范围内，每间隔1.0mil测量1次数据；所得的测试结果如下表1所示：S11, IC pad segment test: The etched bonding pad is segmented and measured once every 1.0 mil within the 12 mil window area. The test results are shown in Table 1 below:
表1邦定IC蚀刻精度测试结果表Table 1 Bonding IC etching accuracy test results
Figure PCTCN2022138618-appb-000001
Figure PCTCN2022138618-appb-000001
从趋势图看，邦定IC焊盘长度12mil，在7-12mil范围内变化较小，可通过1级补偿调整，在顶部1-6mil范围内呈梯度递减，需采用多级补偿方式才能改善“针尖”效应。From the trend chart, the length of the bonding IC pad is 12 mil, with little variation in the range of 7-12 mil. It can be adjusted through 1-level compensation and decreases gradually in the top range of 1-6 mil. Multi-level compensation is required to improve the "needle tip" effect.
S12、根据步骤S11中测得的IC线宽蚀刻变化趋势，结合IC顶部1-6mil区间的蚀刻 差异值建立分级梯度补偿模型。S12. According to the IC line width etching variation trend measured in step S11, a graded gradient compensation model is established in combination with the etching difference value in the 1-6 mil range at the top of the IC.
进一步的，步骤S2中，还包括邦定IC最外侧区域增加等距的假焊盘。本发明中，邦定IC最外侧焊盘，受周边布线影响，可能存在不等距设计，此类不等距设计，在蚀刻时会影响蚀刻均匀性，进而造成最外侧焊盘出现侧蚀过大线细，因此需在IC最外侧区域增加等距的假焊盘或控制IC间距极差在0.5mil以内。Furthermore, step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC. In the present invention, the outermost pads of the bonding IC may be unequally spaced due to the influence of the surrounding wiring. Such unequally spaced designs may affect the etching uniformity during etching, thereby causing the outermost pads to have excessive side etching and thin lines. Therefore, it is necessary to add equidistant dummy pads to the outermost area of the IC or control the IC spacing range to be within 0.5 mil.
进一步的，步骤S2中，邦定IC补偿的方法包括以下：Further, in step S2, the method of bonding IC compensation includes the following:
S21、先根据蚀刻线宽侧蚀量进行第1级补偿，视铜厚差异，线路及IC焊盘整体补偿1.5-2mil；S21, firstly make the first level compensation according to the etching line width side etching amount, and according to the difference in copper thickness, the circuit and IC pad are compensated by 1.5-2mil as a whole;
S22、根据仿真补偿模型，对邦定IC焊盘顶部位置1-6mil区域进行多级补偿。S22. Perform multi-level compensation on the 1-6 mil area at the top of the bonding IC pad according to the simulation compensation model.
进一步的，步骤S22中，包括6级的精细化补偿，每增加一级，追加补偿0.1-0.2mil。Furthermore, in step S22, 6 levels of refined compensation are included, and each additional level provides additional compensation of 0.1-0.2 mil.
进一步的，步骤S3中，包括采用真空酸性一次蚀刻以及二次精准蚀刻。Furthermore, step S3 includes vacuum acid primary etching and secondary precision etching.
进一步的，所述真空酸性一次蚀刻设置喷淋压力为1-1.5kg/cm 2，从而提升蚀刻因子，减少线宽侧蚀。 Furthermore, the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
进一步的，所述二次精准蚀刻，根据铜厚选择匹配的蚀刻速度，第一次蚀刻完后，使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。Furthermore, the secondary precision etching selects a matching etching speed according to the copper thickness. After the first etching, a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness. The surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
进一步的，步骤S3中，包括以下步骤：根据铜厚选择匹配的蚀刻速度，采用两次精蚀工艺，第一次按铜厚的80-90％进行蚀刻，蚀刻完后使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。Furthermore, step S3 includes the following steps: selecting a matching etching speed according to the copper thickness, adopting two fine etching processes, etching at 80-90% of the copper thickness for the first time, using a copper thickness tester to detect the residual copper thickness on the board surface after etching, and then adjusting the etching parameters according to the copper thickness, flipping the surface back and performing a second precise etching, so as to meet the consistency and high-precision tolerance requirements of the bonded IC line width.
实施例2Example 2
本实施例提供一种与实施例1相同的提高邦定IC蚀刻精度的控制方法，所不同的是，进一步的，步骤S22中，包括3级的简化补偿，每增加一级，追加补偿0.2-0.4mil。This embodiment provides a control method for improving the etching accuracy of bonding ICs that is the same as that of Embodiment 1, except that, further, in step S22, three levels of simplified compensation are included, and each additional level provides an additional compensation of 0.2-0.4 mil.
实施例3Example 3
一种提高邦定IC蚀刻精度的控制方法，其特征在于，包括以下步骤：A control method for improving the etching accuracy of a bonding IC, characterized by comprising the following steps:
S1、跟据邦定IC蚀刻形态变化建立仿真补偿模型；S1. Establish a simulation compensation model according to the changes in the bonding IC etching morphology;
S2、设置邦定IC补偿；根据仿真补偿模型，对邦定IC焊盘进行三级梯度补偿；S2. Set bonding IC compensation; perform three-level gradient compensation on bonding IC pads according to the simulation compensation model;
S3、进行邦定IC蚀刻；包括进行两次蚀刻。S3, performing bonding IC etching; including performing two etching steps.
通过本发明的加工方法，可以改善邦定IC蚀刻线细及解决IC顶部位置形成的针尖效应，有效提升邦定IC蚀刻精度及一致性。The processing method of the present invention can improve the bonding IC etching line thickness and solve the needle tip effect formed at the top of the IC, thereby effectively improving the bonding IC etching accuracy and consistency.
进一步的，步骤S1中，蚀刻形态变化为由补偿前的4.0mil变化为补偿后的5.5mil。Furthermore, in step S1, the etching morphology changes from 4.0 mil before compensation to 5.5 mil after compensation.
进一步的，步骤S2中，还包括邦定IC最外侧区域增加等距的假焊盘。Furthermore, step S2 also includes adding equidistant dummy pads to the outermost area of the bonding IC.
进一步的，步骤S2中，三级梯度补偿包括：Furthermore, in step S2, the three-level gradient compensation includes:
根据线宽侧蚀量，进行第一级补偿；Perform the first level compensation based on the line width side erosion amount;
根据蚀刻针尖效应，进行第二级补偿；According to the etching needle tip effect, the second level compensation is carried out;
在第二级补偿基础上再追加补偿，进行第三级补偿。Additional compensation will be made on the basis of the second level compensation to provide the third level compensation.
进一步的，所述第一级补偿，由4.0mil线宽补偿到5.7mil。Furthermore, the first level compensation is to compensate the line width from 4.0 mil to 5.7 mil.
进一步的，所述第二级补偿，在距IC顶部3.0-6.0mil位置加大至6.1mil，即在第一级补偿基础上追加补偿0.4mil。Furthermore, the second level compensation is increased to 6.1 mil at a position 3.0-6.0 mil from the top of the IC, that is, an additional compensation of 0.4 mil is added on the basis of the first level compensation.
进一步的，所述第三级补偿，在距IC顶部0-3.0mil位置加大至6.5mil，即在第二级补偿基础上再追加补偿0.4mil。Furthermore, the third level compensation is increased to 6.5 mil at a position 0-3.0 mil from the top of the IC, that is, an additional compensation of 0.4 mil is added on the basis of the second level compensation.
进一步的，步骤S3中，包括采用真空酸性一次蚀刻以及二次精准蚀刻。Furthermore, step S3 includes vacuum acid primary etching and secondary precision etching.
进一步的，所述真空酸性一次蚀刻设置喷淋压力为1-1.5kg/cm 2，从而提升蚀刻因子，减少线宽侧蚀。 Furthermore, the vacuum acid primary etching sets the spray pressure to 1-1.5 kg/cm 2, thereby increasing the etching factor and reducing line width side etching.
进一步的，所述二次精准蚀刻，根据铜厚选择匹配的蚀刻速度，第一次蚀刻完后，使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。Furthermore, the secondary precision etching selects a matching etching speed according to the copper thickness. After the first etching, a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness. The surface is flipped back and a second precision etching is performed, thereby meeting the consistency and high-precision tolerance requirements of the bonded IC line width.
实施例4Example 4
一种提高邦定IC蚀刻精度的控制方法，包括以下步骤：1.开料：按叠层结构及工程MI尺寸、数量要求进行开料作业。A control method for improving the etching accuracy of bonding IC includes the following steps: 1. Cutting: cutting is performed according to the stacking structure and the size and quantity requirements of the engineering MI.
2.烤板：按常规烤板参数：150℃烘烤2-4小时。2. Baking plate: follow the conventional baking plate parameters: bake at 150℃ for 2-4 hours.
3.内层前处理：采用内层粗化方式，对铜面进行粗化及清洁。3. Inner layer pretreatment: Use inner layer roughening method to roughen and clean the copper surface.
4.内层线路制作：双面贴干膜，按MI内层线路文件，采用LDI激光成像方式进行图形转移，显影后得到内层线路图形。4. Inner layer circuit production: double-sided dry film, according to the MI inner layer circuit file, use LDI laser imaging method to transfer the pattern, and get the inner layer circuit pattern after development.
5.内层蚀刻：根据MI内层铜厚，选择匹配的参数进行蚀刻，将无干膜保护的铜面腐蚀掉。5. Inner layer etching: According to the inner layer copper thickness of MI, select matching parameters for etching to corrode the copper surface without dry film protection.
6.内层退膜：内层蚀刻后，过水平退膜机，退除表面干膜。6. Inner layer stripping: After the inner layer is etched, it is passed through a horizontal stripping machine to remove the dry film on the surface.
7.内层蚀检：拆除保护框，然后用AOI机对蚀刻退膜后的内线线路进行检查。7. Inner layer etching inspection: Remove the protective frame, and then use the AOI machine to inspect the inner line after etching and film stripping.
8.内层棕化：过内层棕化线，对铜面进行粗化及清洁，提高层压的结合力。8. Inner layer browning: Through the inner layer browning line, the copper surface is roughened and cleaned to improve the bonding strength of the lamination.
9.预叠铆合：按MI叠层结构进行预叠，然后进行铆合，铆合时板边所有加密的工具孔均打上铆钉。9. Pre-stack and rivet: Pre-stack according to the MI stacking structure, and then rivet. When riveting, all encrypted tool holes on the edge of the plate are riveted.
10.压合：根据PP特性，选择匹配的压合程序进行真空压合。10. Pressing: According to the characteristics of PP, select the matching pressing program for vacuum pressing.
11.钻孔：按工程MI钻孔文件，对压合后的印制板进行钻孔作业。11. Drilling: Drill holes on the laminated printed circuit board according to the engineering MI drilling file.
12.沉铜、电镀：按工程MI要求制作，满足客户面铜及孔铜要求，面铜厚度公差按±5um进行管控。12. Copper plating and electroplating: Made according to the engineering MI requirements to meet the customer's surface copper and hole copper requirements. The surface copper thickness tolerance is controlled at ±5um.
13.外层线路：双面贴干膜，按MI外线资料文件，采用LDI激光成像方式进行图形转移，显影后得到外层线路图形。13. Outer circuit: Double-sided dry film is applied, and the pattern is transferred by LDI laser imaging according to the MI outer line data file, and the outer circuit pattern is obtained after development.
14.酸性蚀刻：A、采用酸性真空蚀刻机生产；B、蚀刻前将蚀刻上下压力调整到1.2kg/cm 2,按照不同面铜厚度调整蚀刻速度；C、二次精准蚀刻方式，完成第一次蚀刻后，使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整参数，翻转面向后进行第二次精准蚀刻；D、蚀刻后测量IC蚀刻精度，上线宽按﹢0至﹢0.4mil公差管控，如标准值4.0mil，蚀刻后为4.1-4.4mil。 14. Acid etching: A. Use acid vacuum etcher for production; B. Adjust the upper and lower pressures of etching to 1.2kg/ cm2 before etching, and adjust the etching speed according to the copper thickness on different surfaces; C. Secondary precision etching method. After the first etching, use a copper thickness tester to detect the residual copper thickness on the board surface, and then adjust the parameters according to the copper thickness, flip the surface back for the second precision etching; D. Measure the IC etching accuracy after etching, and control the upper line width with a tolerance of +0 to +0.4mil. For example, the standard value is 4.0mil, and the value after etching is 4.1-4.4mil.
15.后续按PCB常规流程加工至成品检验即可。15. Then follow the normal PCB process to process and inspect the finished product.
效果测试Effect test
Figure PCTCN2022138618-appb-000002
Figure PCTCN2022138618-appb-000002
通过本发明的加工方法，由原来的IC上线宽负公差变为IC上线宽正公差，有效改善邦定IC蚀刻线细及顶端针尖效应等问题，提升邦定IC蚀刻精度，产品良率由50％提高到98％以上。Through the processing method of the present invention, the original negative tolerance of the line width on the IC is changed to a positive tolerance of the line width on the IC, which effectively improves the problems of thin IC etching lines and top needle tip effect, improves the etching accuracy of the IC bonding, and increases the product yield from 50% to more than 98%.
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背 离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects, and the scope of the present invention is defined by the appended claims rather than the foregoing description, and it is intended that all changes within the meaning and scope of the equivalent elements of the claims be included in the present invention.
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。需注意的是，本发明中所未详细描述的技术特征，均可以通过任一现有技术实现。In addition, it should be understood that although this specification is described in accordance with the implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art. It should be noted that the technical features not described in detail in the present invention can be realized by any existing technology.

Claims (10)

  1. 一种提高邦定IC蚀刻精度的控制方法，其特征在于，包括以下步骤：A control method for improving the etching accuracy of a bonding IC, characterized by comprising the following steps:
    S1、跟据邦定IC蚀刻形态变化建立仿真补偿模型；S1. Establish a simulation compensation model according to the changes in the bonding IC etching morphology;
    S2、设置邦定IC补偿；根据仿真补偿模型，对邦定IC焊盘进行至少三级的梯度补偿；S2. Set bonding IC compensation; perform at least three levels of gradient compensation on the bonding IC pads according to the simulation compensation model;
    S3、进行邦定IC蚀刻；包括进行两次蚀刻。S3, performing bonding IC etching; including performing two etching steps.
  2. 根据权利要求1所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S1中，仿真补偿模型建立的方法包括以下：The control method for improving the bonding IC etching accuracy according to claim 1 is characterized in that in step S1, the method for establishing the simulation compensation model includes the following:
    S11、IC焊盘分段测试；对蚀刻后的邦定焊盘进行分段测量，在开窗区域12mil范围内，每间隔1.0mil测量1次数据；S11, IC pad segment test: perform segmented measurement on the bonding pad after etching, and measure the data once every 1.0 mil interval within the 12 mil window area;
    S12、根据步骤S11中测得的IC线宽蚀刻变化趋势，结合IC顶部1-6mil区间的蚀刻差异值建立分级梯度补偿模型。S12, according to the IC line width etching variation trend measured in step S11, combined with the etching difference value in the range of 1-6 mil at the top of the IC, a graded gradient compensation model is established.
  3. 根据权利要求1所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S2中，还包括邦定IC最外侧区域增加等距的假焊盘。The control method for improving the etching accuracy of the bonding IC according to claim 1 is characterized in that, in step S2, it also includes adding equidistant dummy pads to the outermost area of the bonding IC.
  4. 根据权利要求2所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S2中，邦定IC补偿的方法包括以下：The control method for improving bonding IC etching accuracy according to claim 2 is characterized in that in step S2, the bonding IC compensation method includes the following:
    S21、先根据蚀刻线宽侧蚀量进行第1级补偿，视铜厚差异，线路及IC焊盘整体补偿1.5-2mil；S21, firstly make the first level compensation according to the etching line width side etching amount, and according to the difference in copper thickness, the circuit and IC pad are compensated by 1.5-2mil as a whole;
    S22、根据仿真补偿模型，对邦定IC焊盘顶部位置1-6mil区域进行多级补偿。S22. Based on the simulation compensation model, multi-level compensation is performed on the 1-6 mil area at the top of the bonding IC pad.
  5. 根据权利要求4所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S22中，包括6级的精细化补偿，每增加一级，追加补偿0.1-0.2mil。The control method for improving the bonding IC etching accuracy according to claim 4 is characterized in that, in step S22, 6 levels of fine compensation are included, and each additional level is compensated by 0.1-0.2 mil.
  6. 根据权利要求4所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S22中，包括3级的简化补偿，每增加一级，追加补偿0.2-0.4mil。The control method for improving the bonding IC etching accuracy according to claim 4 is characterized in that, in step S22, three levels of simplified compensation are included, and each additional level is compensated by 0.2-0.4 mil.
  7. 根据权利要求1所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S3中，包括采用真空酸性一次蚀刻以及二次精准蚀刻。The control method for improving the etching accuracy of bonding ICs according to claim 1 is characterized in that step S3 includes using vacuum acid primary etching and secondary precision etching.
  8. 根据权利要求7所述的提高邦定IC蚀刻精度的控制方法，其特征在于，所述真空酸性一次蚀刻设置喷淋压力为1-1.5kg/cm 2。 The control method for improving etching accuracy of bonding IC according to claim 7, characterized in that the spray pressure of the vacuum acid primary etching is set to 1-1.5 kg/cm 2 .
  9. 根据权利要求8所述的提高邦定IC蚀刻精度的控制方法，其特征在于，所述二次精准蚀刻，根据铜厚选择匹配的蚀刻速度，第一次蚀刻完后，使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻。According to the control method for improving the etching accuracy of the bonding IC as described in claim 8, it is characterized in that the secondary precision etching selects a matching etching speed according to the copper thickness, and after the first etching is completed, a copper thickness tester is used to detect the residual copper thickness on the board surface, and then the etching parameters are adjusted according to the copper thickness, and the second precision etching is performed by flipping the surface backward.
  10. 根据权利要求1所述的提高邦定IC蚀刻精度的控制方法，其特征在于，步骤S3中，包括以下步骤：根据铜厚选择匹配的蚀刻速度，采用两次精蚀工艺，第一次按铜厚的80-90％进行蚀刻，蚀刻完后使用铜厚测试仪对板面残留铜厚进行检测，再根据铜厚调整蚀刻参数，翻转面向后进行第二次精准蚀刻，从而满足邦定IC线宽的一致性及高精度公差要求。According to claim 1, the control method for improving the bonding IC etching accuracy is characterized in that step S3 includes the following steps: selecting a matching etching speed according to the copper thickness, using two fine etching processes, etching at 80-90% of the copper thickness for the first time, using a copper thickness tester to detect the residual copper thickness on the board surface after etching, and then adjusting the etching parameters according to the copper thickness, flipping the surface back and performing a second precise etching, thereby meeting the consistency and high-precision tolerance requirements of the bonding IC line width.
PCT/CN2022/138618 2022-11-18 2022-12-13 Control method for improving bonding ic etching precision WO2024103472A1 (en)

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