JP4391671B2 - Electronic component mounting substrate and manufacturing method thereof - Google Patents

Electronic component mounting substrate and manufacturing method thereof Download PDF

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Publication number
JP4391671B2
JP4391671B2 JP2000198183A JP2000198183A JP4391671B2 JP 4391671 B2 JP4391671 B2 JP 4391671B2 JP 2000198183 A JP2000198183 A JP 2000198183A JP 2000198183 A JP2000198183 A JP 2000198183A JP 4391671 B2 JP4391671 B2 JP 4391671B2
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Japan
Prior art keywords
plating layer
nickel
nickel plating
electronic component
component mounting
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JP2000198183A
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JP2002016100A (en
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英夫 吉田
武馬 足立
敬 犬塚
昌留 高田
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品搭載用基板及びその製造方法に関するものである。
【０００２】
【従来の技術】
従来、絶縁基板の片面または両面に配線パターンやボンディングパッド等を形成してなる電子部品搭載用基板がよく知られている。このような電子部品搭載用基板は、例えば下記の手順を経て製造される。
【０００３】
まず、サブトラクティブ法等によって、後に配線パターンやボンディングパッドとなる銅パターンを絶縁基板上に形成する。次に、電解ニッケルめっきを行い、銅パターン上にりんを含むニッケルめっき層を形成する。引き続き電解金めっきを行い、前記ニッケルめっき層上に金めっき層を形成する。以上の結果、３種の金属からなる配線パターン及びボンディングパッドを備えるプリント配線板が得られる。次に、プリント配線板におけるダイエリアにＬＳＩチップ等の電子部品を搭載した後、ワイヤボンディングを行う。その結果、金等からなるボンディングワイヤを介して、ボンディングパッドとチップ側のパッドとを接続する。そしてこの後、熱硬化性のポッティング樹脂を用いたポッティングを必要に応じて行う。これによりダイエリアが封止され、電子部品搭載用基板が完成する。
【０００４】
【発明が解決しようとする課題】
ところが、上記従来の電子部品搭載用基板の場合、ボンディングパッドに対するボンディングワイヤの接合強度が弱く、その部分の接続信頼性に劣るという問題がある。なお、その理由は以下のように考えられる。
【０００５】
即ち、ワイヤボンディング後にポッティングを行った場合、ボンディングパッド及びボンディングワイヤ中の各成分（即ち銅、ニッケル、金等）がポッティング樹脂の加熱硬化時に熱拡散する。このとき、特にニッケルめっき層の中のニッケルが金めっき層側に素早く移動して、同層の中に熱拡散する。それゆえ、ニッケルめっき層の上層部分にニッケルめっき層中のりんが取り残され、当該部分に高濃度りん層が生じてしまう。そして、このような高濃度りん層の発生により接合強度の低下がもたらされるのである。
【０００６】
本発明は上記の課題に鑑みてなされたものであり、その目的は、ボンディング部の接続信頼性に優れた電子部品搭載用基板及びその製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
上記の課題を解決すべく本願発明者が鋭意研究を行った結果、ニッケルめっき層中のニッケルの結晶サイズに着目し、これが小さいと他金属層へのニッケルの移動が起こりやすくなる傾向があることを新たに知見した。そこで、本願発明者はかかる知見に基づいてさらにそれを発展させ、最終的に下記の発明を想到するに至ったのである。
【０００８】
そこで、請求項１に記載の発明では、絶縁基板の表面に形成された導体層をニッケルめっき層と金めっき層とによって被覆してなるボンディング部に対し、ボンディングワイヤが接合される電子部品搭載用基板において、前記ニッケルめっき層が電解めっきにより前記導体層の上面と側面を全体的に被覆するように形成されているとともに前記金めっき層が電解めっきにより当該ニッケルめっき層上を全体的に被覆するように形成され、前記ニッケルめっき層中のニッケルの結晶サイズの平均値が２μｍ以上であることを特徴とする電子部品搭載用基板をその要旨とする。
【０００９】
請求項２に記載の発明は、請求項１において、前記ニッケルめっき層の厚さは３μｍ〜５μｍであるとした。
請求項３に記載の発明では、請求項１または請求項２において、前記絶縁基板にはめっきスルーホールが貫通形成され、前記ボンディング部を構成する導体層が前記めっきスルーホールのランドに延びて接続するように形成されている。
請求項４に記載の発明では、請求項３において、前記めっきスルーホールには端子ピンが嵌着されている。
請求項５に記載の発明では、導体層上に電解ニッケルめっき及び電解金めっきを行うことによってボンディング部を形成した後、そのボンディング部に対するワイヤボンディングを行う電子部品搭載用基板の製造方法において、前記導体層の上面と側面を全体的に被覆するようにニッケルめっき層を形成するとともに当該ニッケルめっき層上を全体的に被覆するように金めっき層を形成し、前記ニッケルめっき層中のニッケルの結晶サイズの平均値が２μｍ以上となるような条件で前記電解ニッケルめっきを行うことを特徴とする電子部品搭載用基板の製造方法をその要旨とする。
【００１０】
以下、本発明の「作用」について説明する。
請求項１〜５に記載の発明によると、ニッケルめっき層中のニッケルの結晶サイズが２μｍ以上になると、ニッケルめっき層の内部欠陥が減少し、その内部欠陥を通り抜けてニッケルが金めっき層側へ移動することが阻害される。従って、ニッケルめっき層の上層部分における高濃度りん層の発生が回避され、高濃度りん層の発生による接合強度の低下を防ぐことができる。その結果、ボンディング部の接続信頼性を向上させることができる。また、電解めっきにより形成された金めっき層は、無電解めっきにより形成されたもの比べて硬質になる。このことは金めっき層の耐磨耗性の向上、ひいてはボンディングパッドの接合強度の向上にとってプラスに作用する。
【００１１】
この場合、ニッケルめっき層の厚さを３μｍ〜５μｍにすることが好ましい。ニッケルめっき層が薄すぎると、導体層を構成する金属の溶解等によってパターン形状が悪化するおそれがあり、この場合にはボンディング部の平坦性悪化によって接続強度が低下するおそれがある。一方、ニッケルめっき層が厚すぎると、上記の問題は起こらない反面、めっきに要する時間が長くなって生産性やコスト性が低下してしまう。
【００１２】
【発明の実施の形態】
以下、本発明を具体化した一実施形態の電子部品搭載用基板及びその製造方法を図１〜図３に基づき詳細に説明する。
【００１３】
図１に示されるように、この電子部品搭載用基板Ｐ１を構成するプリント配線板１の絶縁基板２の表裏両面には、配線パターン３、ボンディング部としてのボンディングパッド４、ダイパッド５等が形成されている。従って、このプリント配線板１は、いわゆる両面板となっている。なお、絶縁基板２の表裏面においてボンディングパッド４やダイパッド５を除く箇所は、図示しないソルダーレジストによって被覆されている。
【００１４】
絶縁基板２における外周部には、めっきスルーホール６が貫通形成されている。絶縁基板２の両面における配線パターン３同士は、これらのめっきスルーホール６を介して互いに導通している。また、めっきスルーホール６の下面側開口部には、導電性金属材料からなる端子ピン７が嵌着されている。従って、この電子部品搭載用基板Ｐ１を図示しないマザーボード上に実装したとき、端子ピン７を介して電子部品搭載用基板Ｐ１側とマザーボード側とが電気的に接続される。以上のことから、本実施形態の電子部品搭載用基板Ｐ１は、半導体パッケージの一種であるＰＧＡ（ピングリッドアレイ）の形態を備えたものとなっている。
【００１５】
前記ダイパッド５は矩形状に形成されており、絶縁基板２の上面側中央部に配置されている。このダイパッド５上には、電子部品としてのＬＳＩチップ（ベアチップ）８が図示しない接着剤を介して接着されている。なお、ダイパッド５を形成せずに直接ＬＳＩチップ８を接着してもよい。配線パターン３に接続された複数のボンディングパッド４は、絶縁基板２の上面側においてダイパッド５を包囲するように配列されている。ボンディングパッド４の数は、ＬＳＩチップ８の上面外周部に形成されたパッド９の数に対応している。
【００１６】
ボンディングパッド４とＬＳＩチップ８側のパッド９とは、金からなるボンディングワイヤ１０によって互いに接続されている。その結果、プリント配線板１側とＬＳＩチップ８側とが電気的に接続される。なお、金ワイヤに代えてアルミニウムワイヤ等を使用することも可能である。
【００１７】
絶縁基板２の上面側においてダイエリア及びその周辺部は、ポッティング樹脂１１によって封止されている。本実施形態では、ポッティング樹脂１１としてエポキシ樹脂等のような熱硬化性樹脂が用いられている。
【００１８】
図３（ｃ）に示されるように、本実施形態のプリント配線板１における配線パターン３、ボンディングパッド４、ダイパッド５は、いずれも３種の金属、即ち銅、ニッケル及び金からなる。より具体的にいうと、ボンディングパッド４等は、大まかにいって銅パターン２１、ニッケルめっき層２２及び金めっき層２３の３種からなる。
【００１９】
導体層としての銅パターン２１は絶縁基板２に対して密着しており、詳細には３層構造を有している。銅パターン２１における第１層は、厚さ約１８μｍの銅箔２１ａであり、第２層は厚さ約１０μｍのパネル銅めっき層２１ｂであり、第３層は厚さ約１５μｍのパターン銅めっき層２１ｃである。なお、銅パターン２１は、トータルで厚さが４０μｍ〜６０μｍ程度となるように形成されることが好ましい。
【００２０】
ニッケルめっき層２２は、銅パターン２１を被覆するように形成されている。ここで、ニッケルめっき層２２中のニッケルの結晶サイズとは、断面写真に現れた結晶の直線距離のうち最も長い部分を結晶毎に測定し、その平均をとったものをいう。前記結晶サイズの値は、２μｍ以上であることが必要であり、さらには２μｍ〜１０μｍであることがよく、２μｍ〜７μｍであることが最もよい。
【００２１】
ニッケルの結晶サイズが２μｍ以上になると、ニッケルめっき層２２の内部欠陥が相対的に減少するからである。その結果、内部欠陥を通り抜けてニッケルが金めっき層２３側へ移動することが阻害される。逆に、ニッケルの結晶サイズが２μｍよりも小さくなると、ニッケルめっき層２２に内部欠陥が依然として多く存在し、その内部欠陥をニッケルが容易に通過可能となってしまう。ゆえに、ニッケルが金めっき層２３側へ移動してしまい、ニッケルめっき層２２の上層部分に、接合強度低下の原因となる高濃度りん層が発生しやすくなる。
【００２２】
また、ニッケルの結晶サイズを１０μｍ以上にすること自体は、ニッケルめっき層２２の内部欠陥の低減にとっては好適である、その反面、結晶サイズを大型化するための好適なめっき条件を、生産性の低下を伴うことなく設定することが難しくなるおそれがある。
【００２３】
ニッケルめっき層２２は、厚さが３μｍ〜５μｍとなるように形成されることがよい。ニッケルめっき層２２が薄すぎると、ニッケルめっき層２２によって銅パターン２１を完全に被覆することができなくなり、金めっきを施す際に銅が溶解して、パターン形状が悪化するおそれがある。この場合、ボンディングパッド４の平坦性が悪化して、ボンディングパッド４に対するボンディングワイヤ１０の接続強度が低下するおそれがある。一方、ニッケルめっき層２２が厚すぎると、上記の問題は起こらない反面、めっきに要する時間が長くなって生産性やコスト性が低下してしまう。
【００２４】
本実施形態のニッケルめっき層２２には、ニッケルの他に少量のりんが含まれている。従って、このニッケルめっき層２２においては、ニッケルが主成分になっていて、りんが副成分となっている。ニッケルめっき層２２中に少量のりんが含まれているのは、以下の理由による。
【００２５】
第１の理由は、ニッケルめっき層２２と金めっき層２３との密着性が高くなるからである。第２の理由は、金めっきを行う際に金の析出速度が速くなり、生産性の向上にとって好都合だからである。
【００２６】
より具体的にいうと、ニッケルめっき層２２において、りんは３重量％〜１２重量％、さらには５重量％〜９重量％含まれていることが好ましい。
りんの含有量が３重量％未満であると、金の析出速度が速くなり生産性の向上にとって有利になる。その反面、ニッケルめっき層２２と金めっき層２３との密着性が低下し、ひいてはボンディングパッド４に対するボンディングワイヤ１０の接続強度が低下するおそれがある。
【００２７】
一方、りんの含有量が１２重量％を超える場合には、ニッケルめっき層２２と金めっき層２３との密着性は高くなる反面、金めっき層２３を形成する際の金の析出速度が遅くなり、生産性が低下してしまう。
【００２８】
これに加えて、そもそもりん含有量が多くなる結果、ニッケルの結晶サイズの大型化を図ったとしても、ポッティング樹脂１１の加熱硬化時にニッケルめっき層２２中の上層部分に高濃度りん層が形成される場合がある。
【００２９】
ニッケルめっき層２２を被覆する金めっき層２３は、厚さが０．３μｍ〜０．５μｍ程度となるように形成されることがよい。金めっき層２３が薄すぎると、ワイヤボンディング時の打撃により磨耗が生じ、その磨耗部分からニッケルめっき層２２が部分的に露出してしまうおそれがある。一方、金めっき層２３が厚すぎると、金という高価なめっき材料が多く必要になる結果、必然的に製造コストが高くなってしまう。
【００３０】
次に、図２，図３に基づいて、このような電子部品搭載用基板Ｐ１を製造する手順について説明する。
まず、絶縁基板２の両面に厚さ１８μｍの銅箔２１ａを有する銅張積層板を用意する。銅張積層板における絶縁基板２の材料としては、例えばガラスクロスにエポキシ樹脂等の樹脂を含浸させたもの等が用いられる。エポキシ樹脂に代え、ポリイミド樹脂やビスマレイミドトリアジン樹脂（ＢＴ樹脂）等を用いてもよい。
【００３１】
この銅張積層板における外周部にスルーホール形成用孔を透設した後、銅箔２１ａの全面にパネルめっきを施し、パネル銅めっき層２１ｂを形成する。続いて、めっきレジスト３１をパネル銅めっき層２１ｂ上にラミネートする（図２（ａ）参照）。この状態でパターン銅めっきを施し、パターン銅めっき層２１ｃを形成する。さらに、パターン銅めっき層２１ｃ上にはんだめっきを施して、はんだめっき層３２を形成する（図２（ｂ）参照）。ここで、剥離液（水酸化カリウム水溶液）を用いてめっきレジスト３１を剥離し、パネル銅めっき層２１ｂを露出させる（図２（ｃ）参照）。その後、エッチングを行って、パターン銅めっき層２１ｃと対応する箇所以外のパネル銅めっき層２１ｂ及び銅箔２１ａを除去する（図３（ａ）参照）。その後、銅を食刻しない剥離液ではんだめっき層３２を剥離し、銅パターン２１を完成させる。なお、上記のめっき工程を経ることによって、スルーホール形成用孔内にも銅めっきが析出し、これによりめっきスルーホール６が形成される。
【００３２】
次いで、電解ニッケルめっきを行うことによって、銅パターン２１上に電解ニッケルを析出させ、銅パターン２１をニッケルめっき層２２によって全体的に被覆する。本実施形態においては、電解ニッケルめっき浴として例えば硫酸ニッケル浴等が使用される。この場合、析出するニッケルの結晶サイズの平均値が２μｍ以上となるようなめっき条件が設定される。
【００３３】
さらに、電解金めっきを行うことによって、ニッケルめっき層２２上に電解金を析出させ、ニッケルめっき層２２を金めっき層２３によって全体的に被覆する。本実施形態においては、電解金めっき浴として例えばシアン化金カリウム浴等が使用される。
【００３４】
以上の結果、図３（ｂ）に示されるように、３種の金属からなる配線パターン３、ボンディングパッド４及びダイパッド５を備えるプリント配線板１が得られる。
【００３５】
次に、プリント配線板１におけるダイエリアにＬＳＩチップ８をダイボンドした後、金からなるボンディングワイヤ１０を用いてワイヤボンディングを行う。この場合のワイヤボンディングは、ネイルヘッドボンディングであってもよいほか、ウェッジボンディング等であってもよい。その結果、ボンディングワイヤ１０を介して、ボンディングパッド４とＬＳＩチップ８側のパッド９とが接続される（図３（ｃ）参照）。
【００３６】
そしてこの後、熱硬化性のポッティング樹脂１１を用いたポッティングを行う。これによりダイエリアが封止される。そして最後にピン立てを行うことにより、電子部品搭載用基板Ｐ１が完成する。
【００３７】
以下、本実施形態における実施例及び比較例を紹介する。
【００３８】
【実施例及び比較例】
実施例１では、上記の製造手順に沿って電子部品搭載用基板Ｐ１を製造するにあたり、銅パターン２１の厚さを５０μｍ、ニッケルめっき層２２の厚さを７μｍ、金めっき層２３の厚さを０．３μｍにそれぞれ設定した。ニッケルめっき層２２は、ニッケル９３重量％及びりん７重量％からなるものとした。
【００３９】
また、実施例１では、ニッケルめっき層２２中のニッケルの結晶サイズの平均値が２μｍとなるように、下記の浴を用いるとともに下記の条件にてめっきを行った。
＜電解ニッケルめっき浴の組成＞
・硫酸ニッケル： ３００ｇ／ｌ、
・塩化ニッケル： ５５ｇ／ｌ、
・ホウ酸： ４０ｇ／ｌ、
・光沢剤： ０．０２５重量％、
・ピット防止剤： ０．１６７重量％、
＜めっき条件＞
・めっき時間： ３０分、
・めっき温度： ６０℃、
・電流密度： ２．７Ａ／ｄｍ2、
・ｐＨ： ４．７。
【００４０】
この後、シアン化金カリウム浴を用いて常法に従って電解金めっきを行った後、ダイボンディング、ワイヤボンディング、ポッティング及びピン立ての各工程を行った。なお、ポッティング工程では、２５０℃、２４０秒の加熱硬化処理を行った。
【００４１】
また、実施例２では、めっき時間を３０分、めっき温度を６０℃、電流密度を２．０Ａ／ｄｍ2に設定することにより、結晶サイズの平均値が５μｍとなるようにした。
【００４２】
実施例３では、めっき時間を４０分、めっき温度を６０℃、電流密度を２．７Ａ／ｄｍ2に設定することにより、結晶サイズの平均値が７μｍとなるようにした。
【００４３】
実施例４では、めっき時間を４０分、めっき温度を６０℃、電流密度を２．０Ａ／ｄｍ2に設定することにより、結晶サイズの平均値が１２μｍとなるようにした。
【００４４】
比較例では、めっき時間を１０分、めっき温度を６０℃、電流密度を４．０Ａ／ｄｍ2に設定することにより、結晶サイズの平均値が１μｍとなるようにした。
【００４５】
以上のようにして作製された５種の電子部品搭載用基板Ｐ１を対象として、比較調査を行った。
まず、従来公知の手法によってボンディングワイヤ１０の引っ張り試験を行うことにより、ボンディングパッド４に対するボンディングワイヤ１０の接合強度（ｋｇｆ）をそれぞれ測定した。さらに、電子部品搭載用基板Ｐ１をボンディングパッド４の部分でカットした後、そのカット断面のＳＥＭ観察を実施するとともに成分分析も実施した。そして、これに基づいてニッケルめっき層２２の上層部分における高濃度りん層の有無を調査するとともに、同層が存在する場合にはさらにその厚さ（μｍ）を測定した。ここでは、高濃度りん層が０．１μｍ未満であれば「無」、それを超えるものであれば「有」と判定することとした。なお、調査結果は表１に示すとおりである。
【００４６】
【表１】

Figure 0004391671
従って、本実施形態によれば以下のような効果を得ることができる。
【００４７】
（１）本実施形態では、ニッケルめっき層２２中のニッケルの結晶サイズが２μｍ以上になっているため、ニッケルめっき層２２の上層部分における高濃度りん層の発生を回避することができる。ゆえに、ボンディングパッド４に対するボンディングワイヤ１０の接合強度の低下を防ぐことができる。その結果、ボンディングパッド４の接続信頼性を確実に向上させることができる。
【００４８】
（２）本実施形態では、ニッケルめっき層２２の厚さが３μｍ〜５μｍという好適範囲内にて設定されるとともに、金めっき層２３の厚さが０．３μｍ〜０．５μｍという好適範囲内にて設定されている。従って、生産性やコスト性の低下を伴うことなく、確実に接続信頼性の向上を図ることができる。
【００４９】
（３）本実施形態では、ニッケルめっき層２２及び金めっき層２３の形成にあたり、電解めっきを実施している。従って、無電解めっきを実施した場合に比べて、ニッケルめっき層２２及び金めっき層２３を短時間のうちに厚く形成することができる。従って、生産性の低下を来すことがない。また、電解めっきにより形成された金めっき層２３は、無電解めっきにより形成されたもの比べて硬質になる。このことは金めっき層２３の耐磨耗性の向上、ひいてはボンディングパッド４の接合強度の向上にとってプラスに作用する。
【００５０】
なお、本発明の実施形態は以下のように変更してもよい。
・ プリント配線板１を構成する絶縁基板２は、実施形態にて例示したようなプラスティック材料からなるもののみに限定されることはなく、例えばアルミナや窒化アルミニウム等のセラミック材料からなるものであってもよい。また、表面に絶縁処理を施した金属基板を絶縁基板２として用いてもよい。
【００５１】
・ プリント配線板１は両面板に限定されることはなく、片面板や多層板であっても構わない。
・ 銅パターン２１の形成する方法として、実施形態のようなサブトラクティブ法に代わって、アディティブ法を実施してもよい。
【００５２】
・ 銅パターン２１はめっき法を利用して形成されたものに限定されず、例えば絶縁基板２上への銅ペーストの印刷・焼成により形成されたものや、スパッタリング等のような物理的成膜法により形成されたものであってもよい。
【００５３】
・ 導体層として、銅以外の導電性金属からなるパターンを形成することもできる。
・ ニッケルめっき層２２や金めっき層２３を無電解めっきにより形成してもよい。この場合、ボンディングパッド４等の厚さが極めて均一になる。また、電気めっき用のリードが不要になるため、電気的なノイズが発生しにくくなることに加え、高密度で微細なパターンを得ることができる。
【００５４】
・ ダイエリアに搭載される電子部品はＬＳＩチップ８のみに限定されることはなく、ＣＬＣＣやＰＬＣＣ等のようなリードのない半導体パッケージや、ドーターボード等であってもよい。また、ダイエリアは、プリント配線板１の裏面側にあってもよく、さらには表裏両面にあってもよい。
【００５５】
・ ボンディング部は配線パターン３に接続されたボンディングパッド４のみに限定されることはなく、例えばめっきスルーホール６のランド６ａであってもよい。
【００５６】
次に、特許請求の範囲に記載された技術的思想のほかに、前述した実施形態によって把握される技術的思想を以下に列挙する。
【００５７】
（１） 請求項１，２のいずれか１つにおいて、前記ニッケルめっき層は、りんを含むものであること。
（２） 銅パターンをりんを含む電解ニッケルめっき層と電解金めっき層とによって被覆してなるボンディング部に対し、ボンディングワイヤが接合される電子部品搭載用基板において、前記電解ニッケルめっき層中のニッケルの結晶サイズの平均値が２μｍ〜１０μｍに設定されていることを特徴とする電子部品搭載用基板。
【００５８】
【発明の効果】
以上詳述したように、請求項１に記載の発明によれば、無電解ニッケルめっきのときに比べて、結晶の成長速度が速くなり、生産性の向上が図られるとともに、ボンディング部の接続信頼性に優れた電子部品搭載用基板を提供することができる。
【００５９】
請求項２に記載の発明によれば、生産性の低下を伴うことなく確実に接続信頼性の向上を図ることができる。
請求項５に記載の発明によれば、無電解ニッケルめっきのときに比べて、結晶の成長速度が速くなり、生産性の向上が図られるとともに、ボンディング部の接続信頼性に優れた電子部品搭載用基板の製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明を具体化した一実施形態の電子部品搭載用基板の全体断面図。
【図２】（ａ）〜（ｃ）は、同電子部品搭載用基板の製造手順を説明するための要部拡大断面図。
【図３】（ａ）〜（ｃ）は、同電子部品搭載用基板の製造手順を説明するための要部拡大断面図。
【符号の説明】
２１…導体層としての銅パターン、２２…ニッケルめっき層、２３…金めっき層、４…ボンディング部としてのボンディングパッド、１０…ボンディングワイヤ、Ｐ１…電子部品搭載用基板。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component mounting substrate and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an electronic component mounting substrate in which a wiring pattern, a bonding pad, or the like is formed on one or both sides of an insulating substrate is well known. Such an electronic component mounting board is manufactured through, for example, the following procedure.
[0003]
First, a copper pattern that will later become a wiring pattern or a bonding pad is formed on an insulating substrate by a subtractive method or the like. Next, electrolytic nickel plating is performed to form a nickel plating layer containing phosphorus on the copper pattern. Subsequently, electrolytic gold plating is performed to form a gold plating layer on the nickel plating layer. As a result, a printed wiring board having wiring patterns and bonding pads made of three kinds of metals can be obtained. Next, after electronic components such as LSI chips are mounted on the die area of the printed wiring board, wire bonding is performed. As a result, the bonding pad and the chip-side pad are connected via a bonding wire made of gold or the like. Thereafter, potting using a thermosetting potting resin is performed as necessary. As a result, the die area is sealed, and the electronic component mounting substrate is completed.
[0004]
[Problems to be solved by the invention]
However, in the case of the conventional electronic component mounting substrate, there is a problem that the bonding strength of the bonding wire to the bonding pad is weak and the connection reliability of the portion is inferior. The reason is considered as follows.
[0005]
That is, when potting is performed after wire bonding, each component (that is, copper, nickel, gold, etc.) in the bonding pad and the bonding wire is thermally diffused when the potting resin is heated and cured. At this time, especially nickel in the nickel plating layer quickly moves to the gold plating layer side and thermally diffuses in the same layer. Therefore, phosphorus in the nickel plating layer is left behind in the upper layer portion of the nickel plating layer, and a high-concentration phosphorus layer is generated in that portion. The generation of such a high-concentration phosphorus layer results in a decrease in bonding strength.
[0006]
The present invention has been made in view of the above problems, and an object thereof is to provide an electronic component mounting substrate excellent in connection reliability of a bonding portion and a manufacturing method thereof.
[0007]
[Means for Solving the Problems]
As a result of intensive studies by the inventors of the present invention to solve the above problems, attention is paid to the crystal size of nickel in the nickel plating layer, and if this is small, nickel tends to easily move to other metal layers. Newly discovered. Therefore, the inventor of the present application further developed it based on such knowledge, and finally came up with the following invention.
[0008]
Therefore, in the invention described in claim 1, for mounting an electronic component in which a bonding wire is bonded to a bonding portion formed by covering a conductor layer formed on the surface of an insulating substrate with a nickel plating layer and a gold plating layer. In the substrate, the nickel plating layer is formed so as to entirely cover the upper surface and side surfaces of the conductor layer by electrolytic plating, and the gold plating layer entirely covers the nickel plating layer by electrolytic plating. it is formed so as, as its gist the electronic component carrier, wherein the average crystal size of nickel of the nickel plating layer is 2μm or more.
[0009]
According to a second aspect of the present invention, in the first aspect, the nickel plating layer has a thickness of 3 μm to 5 μm.
According to a third aspect of the present invention, in the first or second aspect, a plated through hole is formed through the insulating substrate, and a conductor layer constituting the bonding portion extends to a land of the plated through hole for connection. It is formed to do.
According to a fourth aspect of the present invention, in the third aspect, terminal pins are fitted into the plated through holes.
According to a fifth aspect of the present invention, in the method of manufacturing an electronic component mounting substrate, the bonding portion is formed by performing electrolytic nickel plating and electrolytic gold plating on the conductor layer, and then wire bonding is performed on the bonding portion. A nickel plating layer is formed so as to entirely cover the upper surface and side surfaces of the conductor layer, and a gold plating layer is formed so as to entirely cover the nickel plating layer, and the nickel crystals in the nickel plating layer are formed. The gist of the method of manufacturing an electronic component mounting board is characterized in that the electrolytic nickel plating is performed under such a condition that the average size is 2 μm or more.
[0010]
The “action” of the present invention will be described below.
According to the first to fifth aspects of the present invention, when the nickel crystal size in the nickel plating layer is 2 μm or more, the internal defects of the nickel plating layer are reduced, and the nickel passes through the internal defects to the gold plating layer side. It is inhibited from moving. Therefore, generation of a high concentration phosphorus layer in the upper layer portion of the nickel plating layer is avoided, and a decrease in bonding strength due to the generation of the high concentration phosphorus layer can be prevented. As a result, the connection reliability of the bonding portion can be improved. Also, the gold plating layer formed by electrolytic plating becomes harder than that formed by electroless plating. This has a positive effect on improving the wear resistance of the gold plating layer and, consequently, improving the bonding strength of the bonding pad.
[0011]
In this case, it is preferable that the thickness of the nickel plating layer is 3 μm to 5 μm. If the nickel plating layer is too thin, the pattern shape may deteriorate due to dissolution of the metal constituting the conductor layer, and in this case, the connection strength may decrease due to deterioration in flatness of the bonding portion. On the other hand, if the nickel plating layer is too thick, the above-mentioned problem does not occur, but the time required for plating becomes long and productivity and cost are reduced.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electronic component mounting board and a method for manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS.
[0013]
As shown in FIG. 1, a wiring pattern 3, a bonding pad 4 as a bonding portion, a die pad 5, and the like are formed on both the front and back surfaces of the insulating substrate 2 of the printed wiring board 1 that constitutes the electronic component mounting board P <b> 1. ing. Accordingly, the printed wiring board 1 is a so-called double-sided board. Note that portions of the front and back surfaces of the insulating substrate 2 other than the bonding pad 4 and the die pad 5 are covered with a solder resist (not shown).
[0014]
A plated through hole 6 is formed through the outer peripheral portion of the insulating substrate 2. The wiring patterns 3 on both surfaces of the insulating substrate 2 are electrically connected to each other through these plated through holes 6. A terminal pin 7 made of a conductive metal material is fitted into the lower surface side opening of the plated through hole 6. Accordingly, when the electronic component mounting board P1 is mounted on a mother board (not shown), the electronic component mounting board P1 side and the mother board side are electrically connected via the terminal pins 7. From the above, the electronic component mounting board P1 of the present embodiment has a form of PGA (pin grid array) which is a kind of semiconductor package.
[0015]
The die pad 5 is formed in a rectangular shape, and is disposed in the central portion on the upper surface side of the insulating substrate 2. An LSI chip (bare chip) 8 as an electronic component is bonded onto the die pad 5 via an adhesive (not shown). Note that the LSI chip 8 may be directly bonded without forming the die pad 5. The plurality of bonding pads 4 connected to the wiring pattern 3 are arranged so as to surround the die pad 5 on the upper surface side of the insulating substrate 2. The number of bonding pads 4 corresponds to the number of pads 9 formed on the outer peripheral portion of the upper surface of the LSI chip 8.
[0016]
The bonding pad 4 and the pad 9 on the LSI chip 8 side are connected to each other by a bonding wire 10 made of gold. As a result, the printed wiring board 1 side and the LSI chip 8 side are electrically connected. An aluminum wire or the like can be used instead of the gold wire.
[0017]
On the upper surface side of the insulating substrate 2, the die area and its periphery are sealed with a potting resin 11. In the present embodiment, a thermosetting resin such as an epoxy resin is used as the potting resin 11.
[0018]
As shown in FIG. 3C, the wiring pattern 3, the bonding pad 4, and the die pad 5 in the printed wiring board 1 of the present embodiment are all made of three kinds of metals, that is, copper, nickel, and gold. More specifically, the bonding pad 4 or the like is roughly composed of three types of a copper pattern 21, a nickel plating layer 22, and a gold plating layer 23.
[0019]
The copper pattern 21 as the conductor layer is in close contact with the insulating substrate 2, and specifically has a three-layer structure. The first layer in the copper pattern 21 is a copper foil 21a having a thickness of about 18 μm, the second layer is a panel copper plating layer 21b having a thickness of about 10 μm, and the third layer is a patterned copper plating layer having a thickness of about 15 μm. 21c. The copper pattern 21 is preferably formed so as to have a total thickness of about 40 μm to 60 μm.
[0020]
The nickel plating layer 22 is formed so as to cover the copper pattern 21. Here, the crystal size of nickel in the nickel plating layer 22 means a value obtained by measuring the longest portion of the linear distance of the crystals appearing in the cross-sectional photograph for each crystal and taking the average. The value of the crystal size needs to be 2 μm or more, more preferably 2 μm to 10 μm, and most preferably 2 μm to 7 μm.
[0021]
This is because if the crystal size of nickel is 2 μm or more, the internal defects of the nickel plating layer 22 are relatively reduced. As a result, nickel is prevented from passing through the internal defect and moving to the gold plating layer 23 side. On the other hand, when the crystal size of nickel is smaller than 2 μm, there are still many internal defects in the nickel plating layer 22, and nickel can easily pass through the internal defects. Therefore, nickel moves to the gold plating layer 23 side, and a high-concentration phosphorus layer that causes a decrease in bonding strength is likely to occur in the upper layer portion of the nickel plating layer 22.
[0022]
Further, making the crystal size of nickel 10 μm or more is suitable for reducing the internal defects of the nickel plating layer 22, but on the other hand, suitable plating conditions for increasing the crystal size are set for productivity. It may be difficult to set without any reduction.
[0023]
The nickel plating layer 22 is preferably formed to have a thickness of 3 μm to 5 μm. If the nickel plating layer 22 is too thin, the copper pattern 21 cannot be completely covered with the nickel plating layer 22, and copper may be dissolved when gold plating is performed, thereby deteriorating the pattern shape. In this case, the flatness of the bonding pad 4 may deteriorate, and the connection strength of the bonding wire 10 to the bonding pad 4 may be reduced. On the other hand, if the nickel plating layer 22 is too thick, the above problem does not occur, but the time required for the plating becomes long and the productivity and cost are reduced.
[0024]
The nickel plating layer 22 of this embodiment contains a small amount of phosphorus in addition to nickel. Therefore, in this nickel plating layer 22, nickel is the main component and phosphorus is the subcomponent. The reason why a small amount of phosphorus is contained in the nickel plating layer 22 is as follows.
[0025]
The first reason is that the adhesion between the nickel plating layer 22 and the gold plating layer 23 is increased. The second reason is that when gold plating is performed, the deposition rate of gold is increased, which is advantageous for improving productivity.
[0026]
More specifically, the nickel plating layer 22 preferably contains 3 wt% to 12 wt%, more preferably 5 wt% to 9 wt% of phosphorus.
When the phosphorus content is less than 3% by weight, the deposition rate of gold is increased, which is advantageous for improving productivity. On the other hand, the adhesion between the nickel plating layer 22 and the gold plating layer 23 decreases, and as a result, the connection strength of the bonding wire 10 to the bonding pad 4 may decrease.
[0027]
On the other hand, when the phosphorus content exceeds 12% by weight, the adhesion between the nickel plating layer 22 and the gold plating layer 23 increases, but the gold deposition rate when the gold plating layer 23 is formed becomes slow. , Productivity will decrease.
[0028]
In addition to this, as a result of the increase in the phosphorus content, a high-concentration phosphorus layer is formed in the upper layer portion of the nickel plating layer 22 when the potting resin 11 is heat-cured even if the nickel crystal size is increased. There is a case.
[0029]
The gold plating layer 23 covering the nickel plating layer 22 is preferably formed to have a thickness of about 0.3 μm to 0.5 μm. If the gold plating layer 23 is too thin, wear may occur due to impact during wire bonding, and the nickel plating layer 22 may be partially exposed from the worn portion. On the other hand, if the gold plating layer 23 is too thick, a large amount of expensive plating material such as gold is required, which inevitably increases the manufacturing cost.
[0030]
Next, a procedure for manufacturing such an electronic component mounting board P1 will be described with reference to FIGS.
First, a copper clad laminate having 18 μm thick copper foil 21 a on both sides of the insulating substrate 2 is prepared. As the material of the insulating substrate 2 in the copper-clad laminate, for example, a glass cloth impregnated with a resin such as an epoxy resin is used. Instead of the epoxy resin, a polyimide resin, a bismaleimide triazine resin (BT resin), or the like may be used.
[0031]
After through-hole forming holes are formed in the outer periphery of the copper-clad laminate, panel plating is applied to the entire surface of the copper foil 21a to form a panel copper plating layer 21b. Subsequently, the plating resist 31 is laminated on the panel copper plating layer 21b (see FIG. 2A). Pattern copper plating is performed in this state to form a patterned copper plating layer 21c. Further, solder plating is performed on the patterned copper plating layer 21c to form a solder plating layer 32 (see FIG. 2B). Here, the plating resist 31 is stripped using a stripping solution (potassium hydroxide aqueous solution) to expose the panel copper plating layer 21b (see FIG. 2C). Thereafter, etching is performed to remove the panel copper plating layer 21b and the copper foil 21a other than the portion corresponding to the pattern copper plating layer 21c (see FIG. 3A). Thereafter, the solder plating layer 32 is peeled off with a peeling solution that does not etch copper, and the copper pattern 21 is completed. In addition, by passing through said plating process, copper plating deposits also in the hole for through-hole formation, and, thereby, the plating through-hole 6 is formed.
[0032]
Next, electrolytic nickel plating is performed to deposit electrolytic nickel on the copper pattern 21, and the copper pattern 21 is entirely covered with the nickel plating layer 22. In the present embodiment, for example, a nickel sulfate bath is used as the electrolytic nickel plating bath. In this case, plating conditions are set such that the average value of the crystal size of the deposited nickel is 2 μm or more.
[0033]
Further, electrolytic gold plating is performed to deposit electrolytic gold on the nickel plating layer 22, and the nickel plating layer 22 is entirely covered with the gold plating layer 23. In the present embodiment, for example, a potassium gold cyanide bath is used as the electrolytic gold plating bath.
[0034]
As a result, as shown in FIG. 3B, the printed wiring board 1 including the wiring pattern 3, the bonding pad 4, and the die pad 5 made of three kinds of metals is obtained.
[0035]
Next, after the LSI chip 8 is die-bonded to the die area of the printed wiring board 1, wire bonding is performed using the bonding wire 10 made of gold. In this case, the wire bonding may be nail head bonding, wedge bonding, or the like. As a result, the bonding pad 4 and the pad 9 on the LSI chip 8 side are connected via the bonding wire 10 (see FIG. 3C).
[0036]
Thereafter, potting using a thermosetting potting resin 11 is performed. As a result, the die area is sealed. Finally, by performing pin stand, the electronic component mounting board P1 is completed.
[0037]
Hereinafter, examples and comparative examples in the present embodiment will be introduced.
[0038]
[Examples and Comparative Examples]
In Example 1, in manufacturing the electronic component mounting board P1 according to the above manufacturing procedure, the thickness of the copper pattern 21 is 50 μm, the thickness of the nickel plating layer 22 is 7 μm, and the thickness of the gold plating layer 23 is Each was set to 0.3 μm. The nickel plating layer 22 was composed of 93 wt% nickel and 7 wt% phosphorus.
[0039]
In Example 1, the following bath was used and plating was performed under the following conditions so that the average value of the crystal size of nickel in the nickel plating layer 22 was 2 μm.
<Composition of electrolytic nickel plating bath>
-Nickel sulfate: 300 g / l,
Nickel chloride: 55 g / l,
・ Boric acid: 40 g / l,
-Brightener: 0.025% by weight,
-Pit inhibitor: 0.167% by weight,
<Plating conditions>
・ Plating time: 30 minutes
・ Plating temperature: 60 ℃
Current density: 2.7 A / dm 2
-PH: 4.7.
[0040]
Thereafter, electrolytic gold plating was performed according to a conventional method using a potassium gold cyanide bath, and then each step of die bonding, wire bonding, potting and pinning was performed. In the potting process, a heat curing process was performed at 250 ° C. for 240 seconds.
[0041]
In Example 2, by setting the plating time to 30 minutes, the plating temperature to 60 ° C., and the current density to 2.0 A / dm 2 , the average value of the crystal size was set to 5 μm.
[0042]
In Example 3, by setting the plating time to 40 minutes, the plating temperature to 60 ° C., and the current density to 2.7 A / dm 2 , the average value of the crystal size was set to 7 μm.
[0043]
In Example 4, by setting the plating time to 40 minutes, the plating temperature to 60 ° C., and the current density to 2.0 A / dm 2 , the average value of the crystal size was set to 12 μm.
[0044]
In the comparative example, the average value of the crystal size was set to 1 μm by setting the plating time to 10 minutes, the plating temperature to 60 ° C., and the current density to 4.0 A / dm 2 .
[0045]
A comparative investigation was conducted on the five types of electronic component mounting substrates P1 manufactured as described above.
First, the bonding strength (kgf) of the bonding wire 10 to the bonding pad 4 was measured by performing a tensile test of the bonding wire 10 by a conventionally known method. Further, after cutting the electronic component mounting substrate P1 at the bonding pad 4, the SEM observation of the cut cross section and the component analysis were performed. Based on this, the presence or absence of a high-concentration phosphorus layer in the upper layer portion of the nickel plating layer 22 was investigated, and when the same layer was present, the thickness (μm) was further measured. Here, it was determined that “no” if the high-concentration phosphorus layer was less than 0.1 μm, and “yes” if it exceeded that. The survey results are as shown in Table 1.
[0046]
[Table 1]
Figure 0004391671
Therefore, according to the present embodiment, the following effects can be obtained.
[0047]
(1) In this embodiment, since the crystal size of nickel in the nickel plating layer 22 is 2 μm or more, generation of a high-concentration phosphorus layer in the upper layer portion of the nickel plating layer 22 can be avoided. Therefore, a decrease in the bonding strength of the bonding wire 10 to the bonding pad 4 can be prevented. As a result, the connection reliability of the bonding pad 4 can be reliably improved.
[0048]
(2) In the present embodiment, the thickness of the nickel plating layer 22 is set within a preferable range of 3 μm to 5 μm, and the thickness of the gold plating layer 23 is within a preferable range of 0.3 μm to 0.5 μm. Is set. Therefore, it is possible to reliably improve connection reliability without lowering productivity and cost.
[0049]
(3) In the present embodiment, electrolytic plating is performed in forming the nickel plating layer 22 and the gold plating layer 23. Therefore, compared with the case where electroless plating is performed, the nickel plating layer 22 and the gold plating layer 23 can be formed thick in a short time. Therefore, productivity does not decrease. Further, the gold plating layer 23 formed by electrolytic plating becomes harder than that formed by electroless plating. This has a positive effect on improving the wear resistance of the gold plating layer 23 and, consequently, improving the bonding strength of the bonding pad 4.
[0050]
In addition, you may change embodiment of this invention as follows.
The insulating substrate 2 constituting the printed wiring board 1 is not limited to the plastic material as exemplified in the embodiment, and is made of a ceramic material such as alumina or aluminum nitride. Also good. Further, a metal substrate whose surface is subjected to insulation treatment may be used as the insulation substrate 2.
[0051]
The printed wiring board 1 is not limited to a double-sided board, and may be a single-sided board or a multilayer board.
As a method of forming the copper pattern 21, an additive method may be performed instead of the subtractive method as in the embodiment.
[0052]
The copper pattern 21 is not limited to the one formed using the plating method, for example, the one formed by printing and baking the copper paste on the insulating substrate 2, or the physical film formation method such as sputtering. It may be formed by.
[0053]
-As a conductor layer, the pattern which consists of conductive metals other than copper can also be formed.
-The nickel plating layer 22 and the gold plating layer 23 may be formed by electroless plating. In this case, the thickness of the bonding pad 4 etc. becomes extremely uniform. Moreover, since the lead for electroplating becomes unnecessary, it becomes difficult to generate electrical noise, and a high-density and fine pattern can be obtained.
[0054]
The electronic component mounted on the die area is not limited to the LSI chip 8 but may be a lead-free semiconductor package such as CLCC or PLCC, a daughter board, or the like. In addition, the die area may be on the back side of the printed wiring board 1 and may be on both the front and back sides.
[0055]
The bonding portion is not limited to the bonding pad 4 connected to the wiring pattern 3, and may be the land 6 a of the plated through hole 6, for example.
[0056]
Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiment described above are listed below .
[0057]
( 1 ) In any one of claims 1 and 2 , the nickel plating layer contains phosphorus.
( 2 ) In an electronic component mounting substrate in which a bonding wire is bonded to a bonding portion formed by coating a copper pattern with an electrolytic nickel plating layer containing phosphorus and an electrolytic gold plating layer, nickel in the electrolytic nickel plating layer An electronic component mounting board, wherein the average value of the crystal size is set to 2 μm to 10 μm.
[0058]
【The invention's effect】
As described in detail above, according to the first aspect of the present invention , the crystal growth rate is increased and productivity is improved as compared with the case of electroless nickel plating, and the connection reliability of the bonding portion is improved. It is possible to provide an electronic component mounting board that is excellent in performance.
[0059]
According to the second aspect of the present invention, it is possible to reliably improve connection reliability without reducing productivity.
According to the fifth aspect of the present invention , the crystal growth rate is increased and the productivity is improved as compared with the case of electroless nickel plating, and the electronic component mounting is excellent in the connection reliability of the bonding portion. The manufacturing method of the board | substrate can be provided.
[Brief description of the drawings]
FIG. 1 is an overall cross-sectional view of an electronic component mounting board according to an embodiment of the present invention.
FIGS. 2A to 2C are enlarged cross-sectional views of main parts for explaining a manufacturing procedure of the electronic component mounting board; FIGS.
FIGS. 3A to 3C are enlarged cross-sectional views of main parts for explaining a manufacturing procedure of the electronic component mounting board; FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 21 ... Copper pattern as a conductor layer, 22 ... Nickel plating layer, 23 ... Gold plating layer, 4 ... Bonding pad as a bonding part, 10 ... Bonding wire, P1 ... Substrate for electronic component mounting.

Claims (5)

絶縁基板の表面に形成された導体層をニッケルめっき層と金めっき層とによって被覆してなるボンディング部に対し、ボンディングワイヤが接合される電子部品搭載用基板において、前記ニッケルめっき層が電解めっきにより前記導体層の上面と側面を全体的に被覆するように形成されているとともに前記金めっき層が電解めっきにより当該ニッケルめっき層上を全体的に被覆するように形成され、前記ニッケルめっき層中のニッケルの結晶サイズの平均値が２μｍ以上であることを特徴とする電子部品搭載用基板。In an electronic component mounting substrate in which a bonding wire is bonded to a bonding portion formed by coating a conductor layer formed on the surface of an insulating substrate with a nickel plating layer and a gold plating layer, the nickel plating layer is formed by electrolytic plating. The gold plating layer is formed so as to entirely cover the nickel plating layer by electrolytic plating and is formed so as to entirely cover the upper surface and side surfaces of the conductor layer. An electronic component mounting board, wherein the average crystal size of nickel is 2 μm or more. 前記ニッケルめっき層の厚さは３μｍ〜５μｍであることを特徴とする請求項１に記載の電子部品搭載用基板。  The electronic component mounting substrate according to claim 1, wherein the nickel plating layer has a thickness of 3 μm to 5 μm. 前記絶縁基板にはめっきスルーホールが貫通形成され、前記ボンディング部を構成する導体層は前記めっきスルーホールのランドに延びて接続されていることを特徴とする請求項１または請求項２に記載の電子部品搭載用基板。The plated through hole is formed through the insulating substrate, and the conductor layer constituting the bonding portion extends and is connected to a land of the plated through hole. Electronic component mounting board. 前記めっきスルーホールには端子ピンが嵌着されていることを特徴とする請求項３に記載の電子部品搭載用基板。4. The electronic component mounting board according to claim 3, wherein terminal pins are fitted into the plated through holes. 導体層上に電解ニッケルめっき及び電解金めっきを行うことによってボンディング部を形成した後、そのボンディング部に対するワイヤボンディングを行う電子部品搭載用基板の製造方法において、前記導体層の上面と側面を全体的に被覆するようにニッケルめっき層を形成するとともに当該ニッケルめっき層上を全体的に被覆するように金めっき層を形成し、前記ニッケルめっき層中のニッケルの結晶サイズの平均値が２μｍ以上となるような条件で前記電解ニッケルめっきを行うことを特徴とする電子部品搭載用基板の製造方法。In a method for manufacturing an electronic component mounting substrate, in which a bonding portion is formed by performing electrolytic nickel plating and electrolytic gold plating on a conductor layer, and then wire bonding is performed on the bonding portion. A nickel plating layer is formed so as to cover the nickel plating layer, and a gold plating layer is formed so as to cover the nickel plating layer as a whole. The average value of the crystal size of nickel in the nickel plating layer is 2 μm or more. The method for producing an electronic component mounting substrate, wherein the electrolytic nickel plating is performed under such conditions.
JP2000198183A 2000-06-30 2000-06-30 Electronic component mounting substrate and manufacturing method thereof Expired - Fee Related JP4391671B2 (en)

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JP5428667B2 (en) 2009-09-07 2014-02-26 日立化成株式会社 Manufacturing method of semiconductor chip mounting substrate
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