TWI235017B - Circuit board having patterned trace with enhanced precision and method for fabricating the same - Google Patents

Abstract

A circuit board having patterned trace with enhanced precision and a method for fabricating the circuit board are proposed, wherein an electric insulative substrate is formed with a metal layer thereon and a patterned resist layer is formed on the metal layer. The metal layer is etched to form a patterned trace structure and at least a dummy pattern structure adjacent to the patterned trace structure, wherein the dummy pattern structure is preferably disposed around the patterned trace structure. Then, the resist layer is removed from the circuit board. Since the etching reactive area and the etching speed of etching solution are balanced and regulated by the dummy pattern structure, the quality of the patterned trace structure are improved.

Description

1235017 V. Description of the invention (l)-[Technical field to which the invention belongs] The present invention relates to a circuit board structure and a manufacturing method thereof, especially a patterned circuit structure that can increase the circuit board in the engraving process. Circuit board and manufacturing method thereof. And-[Prior Art] In the semiconductor manufacturing process, when a circuit patterned circuit layer is formed by providing a metal layer in a general printed circuit board or a semiconductor package substrate, it is often used. When forming a patterned circuit structure by etching ..., a patterned resistive layer must first be formed on the substrate layer of the printed circuit board or semiconductor package substrate by developing technology. The two layers can be light. Materials such as resist or dry film, so as to cover the patterned circuit structure to be formed, and then an etching technique (E t ch 丨 M) for forming a circuit is applied to remove the metal layer outside the circuit structure, leaving a Patterned structure. 'The so-called #etching technology generally refers to the use of physical or chemical methods to remove a material; there are many types of etching methods currently operating in the semiconductor industry. Among them, the physical etching process is called dry etching ( Dry Etching). For example, plasma ions are used to bombard material atoms ^ or plasma ions and material atoms are combined to achieve the purpose of material removal. Similarly, the chemical solution method is called wet Etching (Wet Etching), for example, immersing a material in a chemical solution t, uses the chemical solution to produce a chemical action with the material, so that the surface atoms of the material in contact with the chemical / valley solution are removed layer by layer. Dry Etching generally used in semiconductor processes,

17229 Quan 懋 .ptd Page 5 1235017 Description of the invention (2) Whether it is Sputtering Etching or Plasma Etching, its anisotropic (Anis〇tr〇pi c) etching Although the characteristics can reduce the wire width, it can only etch a few nanometers (nm) per minute. The low etch rate is only suitable for thin semiconductor wafers, and for thicker (5 ~ 30 // m) package substrates Even for printed circuit boards, the time and cost of the dry etching method is too large and obviously not enough. At the same time, the dry money carving method is a physical surname carving method that bombards the surface to be carved with ions. The insect selectivity is not ideal, so if the package substrate is made by dry money engraving, the conductive layer may be contaminated. Please refer to the Wet Etching method shown in Figures 1A and 1B, which is an economical and convenient money engraving technique. It is also the earliest mass production method used in semiconductor manufacturing processes. It consists of laying a material layer 11 to be patterned on the surface of a substrate 10, and covering the material layer 11 to be patterned with a patterned resist layer 12, and then spraying—strong acid or A strong alkali etchant 1 3 (Etchant) flows on the surface molecules of the material layer 1 1 (such as a conductive metal layer) to perform a chemical reaction to complete the removal of the last name. In addition to the high last name rate and low use cost, due to This chemical etching method is caused by the chemical reaction between the etching solution 13 and a specific material, so its etching selectivity (S e 1 ectivity) will be better than other methods without removing other materials that are not intended to be engraved. However, because the chemical solution in this wet type has no specific direction for material invasion, it is isotropic (Is 01 r 〇pic insect engraving). The undercut phenomenon 14 shown in Figure 1B affects the accuracy of the patterning process. This is especially the case for printed circuit boards or semiconductor packaging substrates.

17229 Quan 懋 .ptd Page 6 1235017 V. Description of the invention (3) The surrounding area where the patterned circuit structure is to be formed in the metal layer, and there is no open area without electronic components or circuits is more serious. The reason is that the reaction rate variables that affect the etching process include chemical solution selection, chemical solution concentration, temperature, reaction time, pressure, and contact area. Among them, the first to fifth variables can be optimized according to the process requirements. Only the contact area between the reaction liquid and the reaction substance of the sixth item will be uneven due to the actual needs of the patterned structure. When the contact area of the reaction liquid and the reactable substance becomes larger, the flow of the liquid will not be developed. The resistance formed by the photoresistor becomes smaller, and the new liquid replaces the old liquid faster, thereby increasing the reaction rate. Therefore, the larger the contact area in the #etching process, the larger the remaining reaction will be. Please refer to FIG. 2A, which is a patterned circuit structure on the metal layer of a printed circuit board or semiconductor package substrate where a large number of conductive traces (T race) are to be formed. The distribution is sparse and uneven, and the spacing between them is different. In contrast, the etching rate in chemical etching is also different. Therefore, for the conductive traces where the patterned line is to be formed, if the conductive traces are The larger the unpatterned empty mine area A, the larger the etching area and reaction size of the chemical solution it is subjected to. Therefore, it is easy to cause the conductive trace 21 adjacent to the open area A to be affected by different etching rates. The etched uniformity of the patterned conductive traces even caused the conductive traces in the open area to be too thin due to the fast etching rate (as shown by the dashed line in Figure 2A), resulting in incomplete electrical connections and other problems. . Please refer to FIG. 2B. Similarly, for the welding finger (Finger) 2 2 adjacent to an open area A, compared with the remaining welding fingers,

17229 Quan 懋 .ptd Page 7 1235017 V. Description of the invention (4) Adjacent to the open area A, it is subject to a large amount of chemical solution etching, which causes problems such as insufficient length or width of the welding finger (see Figure 2B) Indicated by a dashed line). Please refer to FIG. 2C. For the pad 23 adjacent to the open area A, it is more likely that the size of the pad is too small due to the large amount of I insects, and even the amount of etching around the pad. The difference results in misalignment of the pad size (as shown by the dashed line in Figure 2C), resulting in poor accuracy problems such as subsequent process alignment errors, which seriously affects the reliability of subsequent processes. [Summary of the Invention] In view of the shortcomings of the conventional techniques described above, the main object of the present invention is to provide a circuit board and method for increasing the accuracy of circuit patterning, by using an empty view area in which no patterned circuit structure is formed. Forming a pseudo-patterned area to control the etching reaction in the open area where no line is formed in the patterned circuit structure, to avoid the obvious difference in etching rate in the etching process that causes the conventional line patterning, resulting in insufficient finger width and electrical conductivity Poor process accuracy such as uneven trace widths, undersized pads, and misalignment. Another object of the present invention is to provide a circuit board and a manufacturing method thereof for increasing the patterning accuracy of a circuit, by forming a pseudo-patterned region in an open area where no patterned circuit structure is formed, so as to control the patterned circuit structure. The etching reaction in the open area where no circuit is formed, thereby improving the yield of the patterned circuit structure, increasing the uniformity of the circuit, and improving the alignment accuracy of subsequent processes. In order to achieve the above disclosure and other objectives, the present invention discloses a circuit board for increasing the accuracy of circuit patterning. The main features of the circuit board include at least one electrically insulating substrate; and a patterned circuit structure provided on the electrically insulating substrate. base

17229 Quan 懋 .ptd Page 8 1235017 V. Description of the invention (5) The surface of the material; and at least one dummy pattern area is formed on the surface of the electrically insulating substrate, except for the patterned circuit structure. The rest of the open area is best adjacent to the patterned circuit structure. The invention also provides a circuit board manufacturing method for increasing the accuracy of circuit patterning, which is characterized by providing at least one electrically insulating substrate, and laying a metal layer on the surface of the electrically insulating substrate; and then laying a metal layer on the metal layer. Patterning the resist layer; then, an etching process is performed to form a patterned circuit structure and at least one dummy patterned (Dummy Pa 11 er η) region on the metal layer located outside the patterned circuit structure; thereafter, removing the Barrier layer. Among them, the dummy patterned region is preferably adjacent to the periphery of the patterned circuit structure. The circuit board and its manufacturing method for increasing the accuracy of circuit patterning provided by the present invention are mainly characterized by forming a pseudo-patterned region in an open area adjacent to a desired patterned circuit structure, and controlling the selection of the drug solution and the drug. Under the reaction substance and reaction conditions such as liquid concentration, temperature, reaction time, pressure, etc., the pseudo-patterned area can effectively control the same contact area between the reaction chemical liquid and the counter substance, thereby providing a consistent etching rate in the circuit patterning structure. Avoid a large number of etching reactions of adjacent patterned lines caused by the large reaction area of the patterned circuit structure in the open area, and avoid the inconsistent etching rate caused by uneven reaction area in the etching process of conventional circuit patterning In addition, poor process accuracy problems such as insufficient finger length and width, uneven conductive trace width, too small pad size, and misalignment can increase the yield of patterned circuit structure, increase the uniformity of the circuit, and improve the precision of subsequent process alignment. degree. [Embodiment]

17229 懋 .ptd Page 9 1235017 V. Description of the invention (6) The following is a detailed disclosure of an embodiment of the circuit board and its manufacturing method for increasing the accuracy of circuit patterning in accordance with the accompanying drawings. It should be noted here that these drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, so they only show elements related to the present invention, and the elements shown are not implemented in actual implementation. When the number, shape, and size ratio of the time are drawn, the number, shape, and size ratio of the actual implementation can be a random 5 and 10 remote selection, and its component layout may be more complicated. Please refer to FIGS. 3A to 3C, which show the schematic forms of the circuit board according to the present invention for increasing the accuracy of circuit patterning. As shown in the figure, the circuit board 30 may be a ball grid array (BG A) substrate, which includes: at least an electrically insulating substrate 3 1;-a patterned circuit structure 32, which is disposed on the electrical The surface of the insulating substrate 31; and at least one dummy patterned area 33 formed on the surface of the electrically insulating substrate 31, and the remaining open areas other than the patterned circuit structure 32 A, the best is adjacent to the patterned circuit structure 32. The electrically insulating substrate 31 may be an organic material, an organic material with a mixed fiber, or an organic material with a mixed particle, and the like (eg, epoxy resin, epoxy Po 1 yimi de, cis-succinic acid). It is made of peryleneimine / triazine, Cyanate ester, polybenzocyclobutene or glass fiber composite materials. The patterned circuit structure 32 is typically formed of a metal material (for example, copper), and is patterned by processes such as exposure (E x p sing), development (Deve 1 ping), # 刻 (Etchlng), and the like. (Patterning) to form a majority

17229 懋 .ptd Page 10 1235017 V. Description of the invention (7) Conductive traces 3 2 a, solder fingers 3 2 b, and solder pads 3 2 c. Table 1 indicates that the pseudo-patterned area 3 3 is provided on the surface of the electrically insulating substrate without patterned circuit structures 3 2 (ie, conductive traces 3 2 a, wide surface and 鍀 塾 3 2 c, etc.). Area, and is preferably adjacent to the figure ^ '3 2 b road structure 32, and the pseudo-patterned area 33 can be designed as a continuous or discontinuous line according to the actual patterned, table structure 3 2 form Or blocks. b ^, 3 A as shown in the figure 'for the shape of the conductive traces 32a on the circuit board, the ° area 3 3 can be designed as a circuit, or as shown in Figure 3 B and 3 (: According to the form of the solder fingers 32b and the pad 32c on the circuit board, the dummy patterned area i 33 can be designed in the form of two blocks, and corresponding to the patterned circuit structure 3 / 'of different forms, and different forms of false patterned areas are designed. 33. In order to control the subsequent etching rate of the actual patterned circuit structure adjacent to the dummy patterned area. In order to achieve the circuit board of the present invention that increases the accuracy of circuit patterning, the present invention also discloses the manufacturing method of the circuit board, please Referring to FIG. 4A, first, at least one electrically insulating substrate 31 is provided, and a metal layer 34 is laid on at least one surface of the electrically insulating substrate 31, and the metal layer 34 is used as a subsequent patterning. Where = road junction, the best material is metallic copper. Please refer to FIG. 4B, and then, a patterned resist layer 35 is formed on the metal layer 34 by developing technology. The resist layer 35 may be Photoresist or dry film 'to cover the patterned circuit structure to be formed to In the remaining open area where the patterned circuit structure is not formed on the metal layer, the edge of the patterned circuit structure adjacent to the edge of the patterned circuit structure is to be used as a pseudo-patterned area for subsequent control of the etching efficiency. Please refer to FIG. Etching process to move

17229 Full 懋 .ptd

Page 11 1235017 V. Description of the invention (8) Except for the area of the metal layer that is not covered by the resistive layer 3, the patterned circuit structure of the metal layer 3 4 is completed on the surface of the electrically insulating substrate 3 2 and false. The patterned area 3 3 〇 Please refer to FIG. 4D. After that, the resist layer 3 5 covering the patterned circuit structure 32 and the dummy patterned area 3 3 is removed to make the patterned circuit structure 3 completed. 2 and the pseudo-patterned area 3 3 are exposed on the surface of the electrically insulating substrate 3 1. The etch uniformity of the patterned circuit structure 32 can be effectively controlled by the pseudo-patterned area 33, which can provide the alignment accuracy of the layer-added structure in the subsequent process. In addition, the dummy patterned area 3 3 may be left on the surface of the electrically insulating substrate 3 1 or removed during the etching process, which may be in accordance with the size and size of the dummy patterned area 33 used in the process. The type of etching solution, or the material of the resistive layer 3 5 covering the dummy patterned area 3 3 during the etching process may be different from the material of the resistive layer 3 5 covering the remaining patterned circuit structure 3 2 to determine the dummy patterning. Whether the region 3 3 remains on the surface of the electrically insulating substrate 3 1 after the etching process. The circuit board for increasing the accuracy of circuit patterning and the manufacturing method thereof according to the present invention are formed by forming the pseudo-patterned region in an open area adjacent to a desired patterned circuit structure to effectively control the selection of the chemical solution and the chemical solution. Under the reaction materials such as concentration, temperature, reaction time, and pressure, and the reaction conditions, the pseudo-patterned area provides the same contact area between the reaction liquid and the anti-matter material, thereby maintaining a consistent etching rate in the line patterning structure, avoiding The large reaction area of the patterned circuit structure in the open area causes a large number of etching reactions of adjacent patterned circuits, thereby avoiding the patterning of conventional circuits.

17229 Quan 懋 _ptd Page 12 1235017 V. Description of the Invention (9) Process accuracy such as insufficient finger length due to uneven etching rate, uneven conductive trace width, too small pad size, and misalignment during the etching process Bad problems can further improve the yield of the patterned circuit structure, increase the uniformity of the circuit, and improve the alignment accuracy of subsequent processes. The previous drawings only show a part of the patterned circuit structure of a circuit board. In fact, the size and relative position of the patterned circuit structure are designed and formed on the surface of an electrically insulating substrate according to the actual process requirements. Therefore, the specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention, without departing from the spirit and technical scope of the present invention. Any equivalent changes and modifications made by using the content disclosed in the present invention shall still be covered by the scope of patent application described below.

17229 Quan 懋 .ptd Page 13 1235017 The openness of the deserted area of the deserted area The emptyness of the deserted case The electrification of the deserted case • The rendering of the surrounding scene Wei ·, Cases Week ·, Wei-Wei-Wai-Wei Diagrams, Diagrams, and Line Diagrams Enclosed with Cases-Wai-Wei ·, Wei ·, Traces Week ·, Weeks; Figure Lines Mat map road profiled surface thoughtful guide surface welding intention welding thread level indication pad shown on the top above shown on the top of the welding surface of the guided welding panel with the panel surface added on the flat surface Lu Ping, Lu Ping, Qian Qian, Qian Ban, Zhi Ban, Zhi Dian, Zhi Dian, Zhi Zhi, Lu Ke, Lu Ying, Ying Yu, Ying Yu, Yu Zhi, Yu Zhi, Yu Zhi, Ding Xian Dian # 电 反 电 反 明 案, Ming District, Ming District, 1 Knowing Knowledge Knowing how to engraving pictures and hair into hair.明 图 习 液 习 # Xiqian this fake this case this picture of the case is illustrated as 1 is dissolved as it is a promising picture is shown in Figure 4 AB c A JLa Jane 1 2 Transform 2 Dissolve 2 Dissolve 3 Suppose 3 have 3 have 4 faces Manufactured by the receiving area οο Substrate 11 Material layer to be patterned 12 Resistive layer 13 Cutting solution 14 Undercut 3 0 Circuit board 31 Electrically insulating substrate

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Claims (1)

1235017 VI. Scope of patent application 1. A circuit board for increasing the accuracy of circuit patterning, comprising: at least one electrically insulating substrate; a patterned circuit structure provided on the surface of the electrically insulating substrate; and at least one false A patterned (Dummy Pattern) region is a region formed on the surface of the electrically insulating substrate and located outside the patterned circuit structure. 2. For a circuit board with increased patterning accuracy as described in item 1 of the scope of patent application, the dummy patterned area is preferably adjacent to the patterned circuit structure. 3. For example, the circuit board for increasing the patterning accuracy of a circuit in the scope of patent application, wherein the patterned circuit structure includes any one of the groups of conductive traces, solder fingers, and pads. 4. For the circuit board with increased patterning accuracy of item 1 in the scope of the patent application, the pseudo-patterned area can be formed by continuous and discontinuous lines and blocks according to the shape of the patterned circuit structure. Constituted by one. 5. For the circuit board that increases the accuracy of circuit patterning as described in item 1 of the scope of patent application, wherein the patterned circuit structure is made of metal copper. 6. For a circuit board with increased patterning accuracy as described in item 1 of the scope of patent application, the dummy patterned area is made of metallic copper. 7. For example, the circuit board 9 for increasing the accuracy of patterning of a circuit in item 1 of the scope of patent application, wherein the electrically insulating substrate is any one of the group consisting of organic materials, organic materials with mixed fibers, and organic materials with mixed particles. Made 17229 Full 懋 .ptd Page 16 1235017 Six, the scope of patent application. 8. For a circuit board that increases the accuracy of patterning of a circuit, as described in item 1 of the scope of patent application, the circuit board is a ball grid array (BGA) substrate. 9. A circuit board manufacturing method for increasing patterning accuracy of a circuit, comprising: providing at least one electrically insulating substrate, and laying a metal layer on a surface thereof; placing a patterned resist layer on the metal layer; performing an etching process to Forming a patterned circuit structure and at least one dummy pattern region on the metal layer outside the patterned circuit structure; and removing the resist layer. 10. The circuit board manufacturing method for increasing the accuracy of circuit patterning according to item 9 of the scope of patent application, wherein the dummy patterned region is preferably adjacent to the periphery of the patterned circuit structure. 1 1. The circuit board manufacturing method for increasing the accuracy of circuit patterning according to item 9 of the scope of patent application, wherein the patterned circuit structure includes any one of the groups consisting of conductive traces, solder fingers and solder pads. 1 2. If the circuit board manufacturing method for increasing the patterning accuracy of a circuit according to item 9 of the scope of the patent application, wherein the pseudo-patterned area can be grouped by continuous and discontinuous lines and blocks according to the pattern of the patterned circuit structure β Any one of the groups is formed to control the rate of money engraving of the patterned circuit structure adjacent to the pseudo-patterned area. 1 3. The circuit board manufacturing method for increasing the patterning accuracy of a circuit according to item 9 of the scope of patent application, wherein the metal layer of the pseudo-patterned area covered by the resist layer 17229 懋 .ptd Page 17 1235017 6. Scope of patent application Can be removed in the etching process. 1 4. The circuit board manufacturing method for increasing the patterning accuracy of a circuit according to item 9 of the scope of patent application, wherein the metal layer is made of metal copper. 1 5. According to the circuit board manufacturing method for increasing the accuracy of circuit patterning according to item 9 of the scope of patent application, wherein the electrically insulating substrate is any one of the group consisting of organic materials, organic materials of mixed fibers, and organic materials of mixed particles One made. 1 6. The circuit board manufacturing method for increasing the accuracy of circuit patterning according to item 9 of the scope of patent application, wherein the resist layer is any of a photoresist and a dry film. 1 7. The circuit board manufacturing method for increasing the accuracy of circuit patterning according to item 9 of the scope of patent application, wherein the circuit board is a ball grid array (BG A) substrate. 17229 懋 .ptd Page 18