TW200411757A - Method for fabricating fine conductive traces substrate - Google Patents

Abstract

A method for fabricating fine conductive traces substrates is proposed. The substrate is formed with a conductive layer on at least a surface thereof, and a patterned resist layer formed with fine traces layout is applied over the conductive layer. It allows the conductive layer to be defined with a reserved area and a corresponding to-be-removed area. Then, the conductive layer in the to-be-removed area is anisotropica11y and rapidly etched by an electric-field activated etch process. Finally, the conductive layer still remained in the to-be-removed area is completely removed by a dry etching process for improving the yield of fine conductive traces substrate. In addition, a thin sacrificial layer can be also deposited on the conductive layer for protecting said conductive layer in the dry etching process; this method used in the package substrates or circuit boards manufacturing process will effectively improve the yield of fine conductive traces substrate.

Description

200411757 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a substrate, especially a method for forming a thin circuit substrate. 1 [Previous technology] BGA, FliP Chip, and chip that can reduce I c area and have high density and multi-pin characteristics due to the rapid growth of various portable products such as communication, network, and computer Packages such as CSP (chip size package) and multi-chip module (MCM) have gradually become the mainstream in the packaging market, and are often associated with microprocessors, chip chips, graphics chips, and AS ICs. High-performance chip collocation for higher-speed computing functions. However, because of the process limitations of the C-packaged substrate with wires, its limitations in transmitting chip signals and improving bandwidth and controlling impedance have become high I / 〇 number of package development obstacles, and because the substrate process accounts for 20% to 50% of the packaging cost, so the integrated circuit manufacturing process in semiconductor wafers has been reduced to 0 · 0 9 // m and the package size is also When shrinking to almost the same size as a wafer (about 1 or 2 times the size of a wafer), how to develop a fine circuit that can be used with it, high-density and small-aperture package substrates, reducing the number of substrate layers At the same time, it will not increase excessive manufacturing costs. It is no doubt that f and even other related electronics industries will enter the next generation of important R & D lessons. 1 The process of brushing a circuit board (pCB) or c package substrate has been passed from a path above // m. Dimensions: Includes wire width, lead, and float *, to do ▼ ^ τ., Aspect Ratio, reduced to about 30 " m, smaller line pull — precision research and development ; Know the name of the board wire size

200411757 V. Description of the invention (2) Above m, the traditional etching method with low cost and fast etching is generally used, that is, the wet etching method (Wet, Spray Etching) shown in Figures 3A and 3B, which uses a strong acid Or the strong alkaline etching solution a (Etchant) diffusion effect (D iffusi ο η) and the surface molecules of the film to be etched 20 〇 (conductive layer) to perform a chemical reaction to complete the etch removal, except for the high etch rate and low This cost reduction (Subtracti ν e) money engraving method has the advantage of higher uniformity (U niformity) of the conductive layer thickness after the last name engraving, and because the last name engraving method borrows the last name engraving liquid 2 3 due to the chemical reaction with specific materials, so its selectivity will be better than other methods, without removing other materials that are not intended to be engraved, but also because this wet etching is isotropic (I s 〇tr 〇pic) etching, so when etching down, it will lead to the undercut (U ndercut) phenomenon shown in Figure 3B 2 6, affecting the accuracy of the process, the quality of this wet etching method ( M ass T rans ρ 〇rt) Wire size restrictions will make it difficult to re-etching down the development. Compared with the traditional subtractive etching method, the industry currently adopts the additive method that can produce finer circuits to respond to higher density substrates. It uses electroless copper to form an electroplated crystal on the insulating layer. Seed layer layer to form a conductive layer pattern. This can be divided into the process of full addition (?! 111 factory A dditive) method and semi-additive (Semi A dditive) method, which can avoid etching. At present, it is conventionally known that the substrate process is performed by a semi-additive method capable of making thinner circuits: as shown in FIG. 4A, the surface roughening is performed before the metal layer 51 on the insulating layer 50. (Surface Roughening), as shown in FIG. 4C, a dielectric layer 52 is formed by pressing, and the dielectric layer 52 is drilled (Dr i 1 1 ing) to form a blind hole 53 in FIG. 4D. (B1 ind Via), then

17028. ptd Page 7 200411757 V. Description of the invention (3) "Forming a | as shown in Figure 4E | ^ Order ..., torture the copper layer 5 4 and make it as shown in Figure 4F according to the wires provided The pattern of ^ resist layer 55 (Resist Layer) is used to form electroplated copper 56 ', and unnecessary plating resist layer 55 is removed in the 4G diagram. == mt wire layer, this—the packaging substrate made by the process It is already possible to process *, and spring sizes on the substrate to 20 to 3 high-performance wafers and packages, but if you want to further advance the accuracy of the wires, there are problems that cannot be overcome by the accuracy of the process. Another 4 progresses As for the dry-style surname engraving method commonly used in the mid-night period, such as ^, p, 1., ^ B clothing (Dry

Etching), whether it is splash erosion 蚀 ·% (Plasma Etchlng), iismr = g.Etchlng) or electropolymerization ^ /, non- # directional (AniS〇tr〇Pic) corrosion: Although the sex can reach the Fine money engraving accuracy and reducing the wire width === meters (nm)… the engraving rate is only applicable to the thickness of the wafer, at the same time, the dry… is the first one; the engraving method, the other engraving selectivity and… The whole process of making the surface of the second engraved K? Is made of the zirconium yttrium yttrium τ at 1 因此 center. Therefore, the dry etching method κ + clothing can be used, there will be a conductive layer subject to contamination. With the semiconductor The process technology on the wafer ', d1 level, the current substrate process technology is gradually insufficient, such as 100; f, nanometers, etc., the package substrate of the lower wire size is indeed t σ can be made 2 ^ is Only the breakthrough of this-force ... support technique, which makes the research and development of the second issue "closer, fewer stacks and lower costs, and finer line R & D progress, will it be possible to achieve mass production. … And packaging technology [Summary 1]

17028. ptd page 8 200411757 V. Description of the invention (4) One object of the present invention is to provide a method for forming a fine circuit substrate with a high yield. Another object of the present invention is to provide a method for forming a fine circuit substrate having anisotropic etching characteristics and high etching selectivity. It is still another object of the present invention to provide a method for forming a fine circuit substrate which can avoid the occurrence of a short circuit on the surface of the conductive layer. Another object of the present invention is to provide a method for forming a fine circuit substrate which is capable of etching quickly and easily. In order to achieve the foregoing and other objectives, the method for forming a fine circuit substrate provided by the present invention includes: providing an insulating layer having a conductive layer formed on at least one surface; forming a resist layer on the conductive layer and patterning the same The resistive layer is used to define a removal area and a retention area on the conductive layer by the patterned resistive layer; the conductive layer located in the removed area is not completely removed by an electric field activated electrochemical etching method; and the dry etching method is used to completely Removing the conductive layer remaining in the removed area; and removing the patterned resistive layer so that the conductive layer located in the reserved area forms a desired fine line. The method for forming a fine circuit substrate of the invention includes: providing an insulating layer having a conductive layer formed on at least one surface; forming a sacrificial layer on the conductive layer, and the material of the sacrificial layer being different from the conductive layer Forming a resist layer on the sacrificial layer and patterning the resist layer to define a removing area and a retaining area on the sacrificial layer and the conductive layer respectively by the patterned resist layer; activating the electrochemical etching with an electric field The method does not completely remove the sacrificial layer and the conductive layer located in the removed area; removes the patterned resistive layer; and then completely removes the conductive layer remaining in the removed area by dry etching; and removes the conductive layer located in the removed area.

17028. ptd page 9 200411757 V. Description of the invention (5) The sacrificial layer in the reserved area, so that the conductive layer in the reserved area forms the desired fine line. In addition, the method can also remove the conductive layer remaining in the removal area by dry etching before performing the electrochemical etching and before removing the patterned resist layer. Among them, the electrochemical name engraving uses an external electrode to apply an electric field to a chemical wet etching process, and uses the electric current of the electric field as the driving force for the transfer of charged ions in the etching solution, resulting in a combination of anisotropy. Etching and electrochemical etching with high etch rate, to meet the needs of fine lines and high uniformity etch yield, and can change various etching control variables by changing the electric field, and the effect of f control is simple; at the same time, this Invented and replaced the electrochemical #etching method with a dry etching method with a slower etch rate at the back of the etching to avoid the phenomenon of over-etching or undercutting caused by the electrochemical etching method, and the remaining conductive in the removal area The layer is completely etched away to prevent the short circuit of the wire. In addition, an additional sacrificial layer can be deposited to protect the conductive layer used as the wire in the reserved area to prevent the dry etching method with poor material selectivity from contaminating the reservation. Conductive layer in the area. [Implementation Mode] The first embodiment of the method for forming a fine circuit substrate of the present invention is shown in FIGS. 1A to 1E, and its steps include sequentially forming a surface 1 0 ′ of an insulating layer 10 into one. The conductive layer 20 is then coated with a resist layer 30 on the conductive layer 20, and an electric field activation method (E 1 ectric Fie 1 d-A ctivated Etching Process) is used according to the patterned resist layer 3 The reserved area 3 0 b defined by 0 and the removed area 3 0 a are engraved with the conductive layer 2 0 a in the removed area, and the dry conductive method is used to etch the conductive layer 2 0 aπ remaining in the removed area. Bit

17028. ptd page 10 200411757 V. Description of the invention (6) The resist layer 3 0 b in the reserved area is removed. Among them, as shown in FIG. 1A, it is a single-sided insulating layer 10 such as a package substrate or a conventional printed circuit board, and epoxy resin (Epoxy Resin), polyimide (Polyimide), and cyanoester ( Cyanate Ester), glass fiber, bismaleimide / imide / triazine (BT, Bisma 1 eimide Triazine) or a mixture of epoxy resin and glass fiber (FR 5) and other materials 1 〇 On the above, a conductive metal layer 20 is formed by a conventional thin film deposition method, wherein the thin film deposition method may be an evaporation method ^ It ^ (Sputter i ng) ># M m: M ( Laser Ablation Deposit ion) or various chemical vapor deposition methods (CVD), and the material of the conductive metal layer 20 is generally copper (cu) with better conductivity, but also aluminum (A1), chromium (Ci) It can be replaced by metal such as nickel (Ni) as the wire material for transmitting signals to the substrate. Figure 1B shows that a high-resolution resistive layer 30 is coated on the conductive copper layer 20, and the resistive layer 30. Based on resin 0 ^ 3: [11), photosensitizer (36113: 11 ^ 261〇, and solvent (8〇1 ¥ 6111;) depending on the composition The branch is composed of mixed materials, which is a pre-designed thin line by the process of exposure, development, and baking in the conventional process of Ph0t〇1 ith〇graphy. The road pattern (1 ^ 1 ^^ 11) is transferred to the barrier layer 30, and a reserved area (not etched) and a removed area (to be etched by the famous insect) are defined to perform subsequent money engraving steps. Figure 1c shows the conductive copper layer 20 is etched into a thin circuit designed in advance by etching, but the thin circuit below 15 // m targeted by the present invention is finer than the wire size of the conventional package substrate. Therefore, the conventional wet etching method and semi-additive method generally used in the packaging substrate manufacturing process are difficult to achieve.

200411757

17028. ptd Page 12 200411757 V. Description of the invention (8) Although the etching rate of this electric field activation etching method is fast, it also makes its end-point detection (E nd-Point Detect) difficult. And it may cause the problem of excessive #etch (0ver Etch), and the undercut phenomenon caused by the isotropic chemical etching of the etching solution 23 may also exceed the acceptable range of this process, thereby affecting the accuracy of the process However, if the etching is stopped early in order to prevent the above-mentioned phenomenon, it may cause the remaining conductive steel layer 20 a incompletely etched in the removal area, resulting in a short circuit phenomenon of the conductive lines on the package substrate, forming a dilemma. To solve this problem in this embodiment, as shown in FIG. 1C, the conductive copper layer 2a, f (for example, about 0 · 1 to 0 · 5 // m) is left in the removed area to be etched. The electric field activation method is used to remove the residual conductive copper layer 20a, 'by using a dry-cut method to solve the foregoing problem. This is because the dry-remove method has an anisotropic money engraving and money engraving rate. Slower (only> 1 nanoseconds per minute) feature 'can meet the needs here' and because of the poor selectivity of tapeworms in the dry-cut method, this step is still reserved as shown in the figure The remaining resistance layer 3 0 b in the reserved area is used to avoid unnecessary etching of the conductive copper layer 2 b in the reserved area during dry etching. The dry etching system may use the conventional 4 sputtering method ( S pu 11 ering E tching), Plasma Etching, Reactive Ion Etching (RIE, Reactive 1½ E t ch i ng), or Laser Etching (Laser E t ch i ng) Reactive ions that are characteristic of both strike and plasma etching

f Ding etching method is more commonly used. This is because it has both physical and chemical winds and the thin film mechanism, which can meet both the anisotropic etching and the good clearance ^, and its The etching rate is also faster than laser etching. With the two existing options of A and B, the contours of the thin film after reactive ion etching can be transported to 80%. to

200411757

The verticality of 9 (l ..), and its choice of etching materials and other materials is up to 40: 1. This embodiment is performed by using a reactive gas containing chlorine atoms or other gases, 2 4 (R eactive G as) In the removal area, green ~% like; ¥ electric surface] exhibiting 20 an reactive ion etching, as shown in FIG. 1D, it can be said that the copper layer 20an and the reactive gas 24 form CuCl rain and smoke, mystery & Package ^ 'Although 隹 steel has better conductivity than your metal', its CuCl product is not a volatile /, (usually until 20 (TC can be volatile), so this dry ^ In the sub-process, the reaction temperature can be appropriately increased or the + force (P ower) in the input electronics can be increased. The larger the DC bias (DCB ias) is used to enhance the effect of the ionization and the copper etching. Rate and ability. * Do n’t continue with “When the remaining guides # 铜 层 20a” in the removed area are completely removed by dry money engraving, you can remove the part that is located in the reserved area and has = part as shown in Figure 1E. The dry etching of the resist layer 30b, and the method of removing the resist layer 30b can be # 士 η 化 ~, "Hubei solution (wet 4) or plasma ( Dry type) The resist layer 30b is removed and the conductive copper layer 20b intended to be used as a conductor in the reserved area is retained. As for the wet inorganic solution de-photoresistance method commonly used in general semiconductor processes, due to the inorganic solution such as crushed acid Or hydrogen peroxide may often invade the conductive layer 20b at the same time, especially when ^ is used as the conductive layer, so this process is not used to remove the resistance layer. After removing the resistance layer, you can get this A thin circuit board with a size of 1 5 # m or less: The second embodiment of the present invention is shown in Figures 2A to 2G, and the second is to add a sacrificial layer 40 (Sacrif icial Layer) to the process of the first embodiment. ) In order to avoid contamination of the conductive copper layer 20 b used as a conductor in the reserved area during the etching process, and the steps include ° σ on an insulating surface 10 of the insulating layer 10 in sequence. A conductive layer 20 is formed, and then the conductive layer is 17028. ptd Μ

Page 14 200411757 V. Description of the invention (ίο) A thin sacrificial layer 40 is deposited on the electrical layer 20, and a patterned resist layer 30 is coated, and the resist layer 3 is applied by an electric field activation method. The remaining area 3 0 b and the removal area 30 a defined above are engraved with the sacrificial layer 4 0 3 and the conductive layer 2 in the removal area, and then the remaining resistance layer 3 〇b in the reservation area is removed, followed by dry etching. The remaining conductive layer 20a in the removed area is etched in a manner such that it is located in the reserved area = the remaining sacrificial layer 40b is removed, wherein the sacrificial layer 40b is used in the dry etching step to replace The resist layer 30b in the first embodiment is used to protect the conductive layer 20b in the reserved area from being polluted by dry etching. In addition, in this embodiment, a dry etching step may be performed before removing the resist layer 30b. In order to remove the removed residual conductive layer 20a, the dry etching step need not be limited to removing the resist layer. After sMb, it is no longer two. The same steps in the manufacturing process as in the first embodiment. Here is the detailed step of the insulation 坪 f ping. The second step is also related to-copper; 2π, ΐ A conductive copper layer 20 is deposited on the substrate 2 and a sacrificial layer 40 is deposited on the conductive layer 2 ′. The deposition method of the sacrificial layer 40 is, for example, the conductive copper layer 20 can be evaporated or sputtered. Plating, laser vapor deposition, or various winds: One, because the role of the sacrificial layer 40 is only to protect the " v copper-clad layer 2 0 b, its deposition thickness need not be too thick and can be any bamboo-non-metal The material can also be different from the conductive layer, that is, the thickness of the sacrificial layer 40 and the material used depend on the distance of the pen layer 20. This is because the last step is to remove the second layer: 歹 ' For the remaining sacrificial layer 40b, the material selectivity of the removal agent needs to be taken into account:: = When the sacrificial layer is removed, and-and is reserved as ί, '^^ 2 0b, generally we can use metal tin (or aluminum, Gold and nickel

17028.ptd Page 15 200411757 V. Description of the invention (11) Other sacrificial materials are used as the sacrificial layer 40. When the sacrificial layer 40b is to be removed at the end, a chemical solution (such as Tin dream agent), that is, figure 2C is coated with a patterned resist layer 30 on the sacrificial layer 40, and the aforementioned electric field activation etching method is used as shown in figure 2D according to the thin line. The sacrificial layer 40a and the conductive copper layer 20a in the removed area are pattern-etched. To avoid the phenomenon of over-etching and undercutting, a residual conductive copper layer 20a of an appropriate thickness is left in the removed area. The final etching is performed by a dry etching method. In this embodiment, since the sacrificial layer 4 0 b already protects the conductive copper 0 2 0 b to be retained, the resistance in the reserved area can be removed before the step in FIG. 2E. The layer 3 0 b is removed in the same manner as in the first embodiment; after that, as shown in FIG. 2 F, the remaining conductive copper layer 20 aπ located in the removal area is removed by dry etching to avoid a short circuit of the substrate. The dry etching method can also use a reactive ion etching method, but in this embodiment, The composition of the reactive gas 2 4 is designed to change the material selectivity of the etch. For example, the rate at which the reactive gas 2 4 can etch the conductive layer 2 0 (copper) and the etching rate of the sacrificial layer 4 0 (tin ' ) At a rate of 10: 1, so only the thickness of the remaining conductive copper layer 20 aπ (such as 0.1 to 0.5 // m) is similar to or slightly thicker than the thickness of the deposited sacrificial layer 40b. Large, it can ensure that when the residual conductive copper layer 2 0 a ″ has been completely removed, the sacrificial layer 4 0 b in the reserved area has a certain thickness, so as not to erode the unnecessary conductive copper layer 2 0 b, in order to exert the protective effect of depositing an additional sacrificial layer 40 in this embodiment, and to protect the conductive copper layer 2 0 b which is to form a wire, the effect is better than that in the first embodiment; FIG. 2 G is as described above To remove the residual sacrificial layer 4 0 b in the reserved area with a de-tinning agent that does not erode copper,

17028. ptd page 16 200411757 V. Description of the invention (12) Retain the thin lines below the formation. In summary, make a line with a thin line | insect engraving and remaining engraving method. It also has the method of the present invention, other substrate effects. The replacement step is also a single-sided substrate, and at the same time, as the situation demands, the present invention, except for semiconductor wires and recording processes, and the above-mentioned four spirits used to limit the original disclosure and the conductive copper package are all covered by the application circuit described later. Substrate. 'The shape of the present invention (1 5 // ra, the selectivity of the material is good, etc. are fast, the steps and processes are disclosed before the cost, or the semiconductor can be used in the present invention, and it can also be used in the double-sided electronic industry high packaging substrate and printing mask manufacturing process The display of the large-area panel is only the scope of this work. For example, the patented scope is 20b, which is based on the principle. In addition, this substrate has a fine circuit base of 15 am). Control is not limited to the methods used in the actual manufacturing process, board, multi-layer board density, high-efficiency brushed circuit board (CD) and digital display, and other creative creations of all the specific hot topics covered by this equivalent. The manufacturing method of the board, besides being able to manufacture, is also non-specific, and its electric field control is simple and effective. Other methods or materials described in the examples and this method can be applied to the development of thin-line energy-capacity calculations of flexible boards or flexible boards, for example, in the manufacturing process of bit discs (DVD) writing substrates. It ’s just an example, it ’s not a modification or modification made by the technical person in this creation, it should still be

200411757 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1 E are schematic diagrams of the first embodiment of the method for forming a fine circuit substrate of the present invention; Figures 2 A to 2 G are the fine lines of the present invention. Schematic diagrams of the second embodiment of the substrate manufacturing method; FIGS. 3A and 3B are schematic diagrams of the substrate manufacturing process of the conventional wet etching method; and FIGS. 4A to 4G are schematic diagrams of the substrate manufacturing process of the conventional semi-additive method. ΐφ Insulating layer 10 'Insulating surface 20 Conductive layer 20a Conductive layer in removed zone 20b Conductive layer in reserved zone 2 0aM Residual conductive layer after engraving 23 Name engraving liquid 24 Reactive gas 25 Electrode 25a Cathode of electrode 26 Undercut phenomenon 30 Resistance Layer 30a, removing resist layer 30b, remaining area resist layer 40, sacrificial layer 40a, removing area sacrificial layer 40b, retaining area sacrificial layer 50, insulating layer 51 metal 52 dielectric layer 5 # blind hole 54 electroless copper layer 55 electroplating resist layer 56 electroplating copper

17028.ptd Page 18

Claims (1)

200411757 VI. Application Patent Scope 1. A method for forming a thin circuit substrate, the steps of which include: providing an insulating layer so that a conductive layer is formed on at least one surface of the insulating layer; forming a resistive layer on the conductive layer, And patterning the resist layer to define a removed area and a reserved area on the conductive layer by the patterned resist layer; incomplete removal of the conductive layer located in the removed area by electrochemical etching; dry etching Completely removing the conductive layer remaining in the removed area; and removing the patterned resistive layer so that the conductive layer located in the reserved area forms a desired fine line. 2. The method for forming a fine circuit substrate as described in item 1 of the scope of patent application, wherein the material used to form the insulating layer is selected from the group consisting of bad oxygen resin, polyvinylamine, cyanoester, glass fiber, BT and FR 5. One of the group. 3. If a method for forming a fine circuit substrate according to item 1 of the patent is claimed, wherein the material of the conductive layer is one selected from the group consisting of copper, aluminum, chromium and nickel with good conductivity. 4. The method for forming a fine circuit substrate as described in the first patent application, wherein the resist layer is a high-resolution photoresist layer. 5. For the method for forming a thin circuit substrate according to item 1 of the scope of the patent application, wherein the electrochemical method of engraving is an electric field activation (Electric Field-Activated Etching) method, and the fourth method is 17028. ptd page 19 200411757 VI. Application for patents' Set a pair of electrodes and a remaining etching solution that can etch the conductive layer material, so that the electric field of the electrode drives the etching solution for an anisotropic electrification Scientific name insect engraving. 6. The method for forming a fine circuit substrate according to item 5 of the application, wherein the etching solution is selected from one of an acidic solution and a test solution that can etch the conductive layer material. 7. For example, the method for forming a fine circuit substrate according to item 1 of the patent application, wherein the dry #etching method is selected from the group consisting of 丨 low strike # 刻, 电 众 # 刻, reactive ion etching (RIE) and laser etching. One of the groups formed by law. 8. The method for forming a fine circuit substrate according to item 7 of the scope of patent application, wherein the reactive gas system used in the reactive ion etching method is a reactive gas containing a chlorine atom (C 1). 9. A method for forming a fine circuit substrate, the steps comprising: providing an insulating layer so that a conductive layer is formed on at least one surface of the insulating layer; '' 'forming a sacrificial layer on the conductive layer, and the sacrificial layer The material is different from the conductive layer; a resist layer is formed on the sacrificial layer, and the resist layer is patterned to define a removal area on the sacrificial layer and the conductive layer by the patterned resist layer and A reserved area; incomplete removal of the sacrificial layer and the conductive layer in the removed area by electrochemical etching; completely removal of the remaining in the removed area by dry etching 17028. ptd page 20 200411757 VI. Patent application conductive layer; and remove the sacrificial layer located in the reserved area so that the conductive layer located in the reserved area forms the desired fine line. 10. The method for forming a fine circuit substrate according to item 9 of the scope of patent application, wherein the patterned resist layer is removed before dry etching. 1 1. The method for forming a fine circuit substrate according to item 9 of the scope of patent application, wherein the patterned resist layer is removed after dry etching. 1 2. The method for forming a thin circuit substrate according to item 9 of the scope of the patent application, wherein the insulating layer is selected from the group consisting of epoxy resin, polyvinylamine, cyanoester, glass fiber, BT and FR 5. One of them. 1 3. According to the method for forming a fine circuit substrate according to item 9 of the scope of the patent application, wherein the material of the conductive layer is one selected from the group consisting of materials with good conductivity such as copper, aluminum, chromium, and nickel. 14. If the method for forming a fine circuit substrate according to item 9 of the scope of patent application, wherein the material of the sacrificial layer is selected from one of the group consisting of tin, Ming, gold, and other materials, but the choice of The material needs to be different from the conductive layer: the material is different. 15. The method for forming a fine circuit substrate according to item 9 of the scope of patent application, wherein the resist layer is a high-resolution photoresist layer. 16. The method for forming a fine circuit substrate according to item 9 of the scope of the patent application, wherein the electrochemical etching method is an electric field-activated etching method, which is configured with a pair of electrodes and a The etch solution of the sacrificial layer and the conductive layer material can be engraved so that the electric field of the electrode drives the etching solution to perform an anisotropy. 17028. ptd page 21 200411757 6. Scope of patent application 17. The method for forming a thin circuit substrate according to item 16 of the scope of patent application, wherein the etching solution is selected from one of an acidic solution and a test solution that can etch the material of the sacrificial layer and the conductive layer. 18. The method for forming a fine circuit substrate according to item 9 of the scope of the patent application, wherein the method of the dry money engraving is selected from the group consisting of sterilization money engraving, electricity gathering engraving, reactive ion etching (RIE) and laser etching. One of the groups formed by law. · 19. According to the method for producing a fine circuit substrate according to item 18 of the scope of patent application, in φ, the reactive gas system used in the reactive ion etching method is a reactive gas containing a chlorine atom (C 1) . 17028.ptd Page 22