CN107708316A - A kind of preparation method of superfinishing fine rule road - Google Patents
A kind of preparation method of superfinishing fine rule road Download PDFInfo
- Publication number
- CN107708316A CN107708316A CN201710762186.8A CN201710762186A CN107708316A CN 107708316 A CN107708316 A CN 107708316A CN 201710762186 A CN201710762186 A CN 201710762186A CN 107708316 A CN107708316 A CN 107708316A
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- CN
- China
- Prior art keywords
- copper
- plate
- production plate
- preparation
- fine rule
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
Abstract
The invention discloses a kind of preparation method of superfinishing fine rule road, comprise the following steps：Production plate is pressed into after PP pieces, core plate, PP pieces are overlapped successively；Drilled on production plate；By way of sputter coating one layer of copper plate is formed in production plate surface；Copper-coating is carried out to production plate, makes the hole metallization on production plate；Then making outer-layer circuit carried out to production plate successively, make solder mask, surface treatment and forming processes, wiring board is made.The inventive method is by by changing technological process, reducing the bottom copper thickness before etching, the minimum feature line-spacing that can be made is 45 μm, improves the fine process capability of circuit.
Description
Technical field
The present invention relates to printed wiring board manufacture technology field, and in particular to a kind of preparation method of superfinishing fine rule road.
Background technology
With the continuous miniaturization of electronic product and highly integrated, wiring board gradually march toward high-accuracy fine rule road, small-bore,
High aspect ratio (6:1-10:1) direction is developed, what high-precision densification, aperture tinyization, high thickness to diameter ratio and the line-spacing of wiring board narrowed
Development trend adds the difficulty of wiring board making, and the process capability for especially making minimum feature line-spacing is difficult to reach requirement.
It is 65 μm/65um that wiring board table copper, which controls the minimum feature line-spacing process capability in the range of≤30um, at present, is pressed
According to existing positive flow and negative film flow ability can not be done to effective lifting, while the bigger (erosion of the lateral erosion etched again
It is smaller to carve the factor)；Positive flow technologies are usually to do basic copper thickness according to the copper foil of 12um or 15um thickness at present, along with heavy
The thickness of copper and plate electricity, it is about 20 μm to cause the bottom copper total thickness before etching, then carries out thick copper on its basis, during etching according to
Bottom copper copper thickness goes to etch, and because the etching factor for etching bottom copper is present, limits minimum feature line-spacing；Negative film flow technologies lead at present
It is often to do basic copper thickness according to the copper foil of 12um or 15um thickness, along with heavy copper and the thickness of plate electricity, causes the bottom before etching
Copper total thickness is about 20 μm, goes to etch according to bottom copper copper thickness during etching, because the etching factor for etching bottom copper is present, limits minimum line
The wide line away from.
The content of the invention
The problem of present invention can only achieve 65 μm for the line width line-spacing process capability of existing line plate outer-layer circuit, carries
For a kind of preparation method of superfinishing fine rule road, this method by the bottom copper thickness before by changing technological process, reducing etching,
The minimum feature line-spacing that can be made is 45 μm, improves the fine process capability of circuit.
In order to solve the above-mentioned technical problem, the invention provides a kind of preparation method of superfinishing fine rule road, including following step
Suddenly：
S1, pressing：Production plate is pressed into after PP pieces, core plate, PP pieces are overlapped successively.
Preferably, in step S1, internal layer circuit is made on core plate before pressing.
S2, drilling：Drilled on production plate.
S3, sputter coating：By way of sputter coating one layer of copper plate is formed in production plate surface.
Preferably, in step S3, the plating that a thickness is 0.5-1 μm is formed in production plate surface by way of sputter coating
Layers of copper.
S4, heavy copper：Copper-coating is carried out to production plate, makes the hole metallization on production plate.
Preferably, in step S4, the heavy layers of copper that a thickness is 1-2 μm is formed in production plate surface by copper-coating.
S5, rear process：Then making outer-layer circuit carried out to production plate successively, make solder mask, surface treatment and shaping
Processing, wiring board is made.
Preferably, in step S5, making outer-layer circuit is carried out using positive blade technolgy.
Compared with prior art, the present invention has the advantages that：
The present invention eliminates outer layer copper by the way that PP pieces and core plate directly are pressed together into production plate in pressing working procedure
Paper tinsel, last layer thin copper layer is plated on production plate by way of sputter coating afterwards, then again by copper-coating in thin copper layer
One layer of heavy layers of copper of upper formation, then directly carry out the process for making outer-layer circuit, the process for eliminating electric plating of whole board, when making etching
Bottom copper total thickness the thickness of heavy layers of copper is added for thin copper layer；The inventive method is by changing technological process, before reducing etching
Bottom copper thickness, bottom copper total thickness≤3 μm of formation, it is i.e. etchable to can be used directly chemical microetch line, avoids and is lost using etching line
Carve, etching factor can accomplish more than >=10, it is ensured that the minimum feature line-spacing that can be made is 45um, greatly improves essence
The process capability of fine rule road.
Embodiment
In order to more fully understand the technology contents of the present invention, the technical side below in conjunction with specific embodiment to the present invention
Case is described further and illustrated.
Embodiment
A kind of preparation method of superfinishing fine rule road shown in the present embodiment, including following treatment process：
(1), sawing sheet：Core plate is outputed by jigsaw size 320mm × 420mm, and core plate thickness of slab is 0.5mm, the outer layer copper of core plate
Face thickness is 0.5OZ.
(2) internal layer circuit (negative film technique), is made：Inner figure is shifted, and light-sensitive surface, light-sensitive surface are coated with vertical application machine
8 μm of film thickness monitoring, using Full-automatic exposure machine, internal layer circuit exposure is completed with 5-6 lattice exposure guide rule (21 lattice exposure guide rule)；Internal layer
Etching, the core plate after exposure imaging is etched into line pattern, it is 3mil that internal layer line width, which measures,；Internal layer AOI, then checks internal layer
The defects of opening short circuit, circuit breach, circuit pin hole of circuit, defective to scrap processing, flawless product goes out to downstream.
(3), press：Brown speed is according to bottom copper copper thickness brown, by PP pieces, core plate, PP pieces on request successively after lamination, root
Pressed according to the characteristic of plate from appropriate lamination, form production plate.
(4), outer layer drills:Drilling operation is carried out using borehole data.
(5), sputter coating:It is 0.5-1 μm to form a thickness in production plate surface by way of magnetron sputtering plating
Copper plate.
(6), heavy copper:Making the hole metallization on production plate, backlight tests 10 grades, and the heavy copper thickness in hole is 0.5 μm, and
The heavy layers of copper that a thickness is 1-2 μm is formed on copper plate.
(7) outer-layer circuit (positive blade technolgy), is made：Outer graphics shift, luxuriant and rich with fragrance using Full-automatic exposure machine and positive circuit
Woods, outer-layer circuit exposure is completed with 5-7 lattice exposure guide rule (21 lattice exposure guide rule), it is developed, outer-layer circuit figure is formed on multilayer boards
Shape；Outer graphics are electroplated, and then distinguish copper facing and tin plating on multilayer boards, copper facing is the current density electric plating of whole board with 1.8ASD
60min, tin plating is to electroplate 10min with 1.2ASD current density, 3-5 μm of tin thickness, then moves back film successively again, etches and move back tin,
During etching using chemical microetch line etch, such etching factor (the ratio between etch depth and lateral etches) can accomplish >=10 with
On, outer-layer circuit is etched on multilayer boards, and it is 45 μm that internal layer line width line-spacing, which measures, outer layer AOI, then checks outer-layer circuit
The defects of opening short circuit, circuit breach, circuit pin hole, defective to scrap processing, flawless product goes out to downstream.
(8), welding resistance, silk-screen character：According to prior art and by design requirement solder mask and silk-screen are made on production plate
Character.
(9), it is surface-treated：It is surface-treated according to prior art and by design requirement on production plate.
(10), it is molded：According to prior art and design requirement gong profile is pressed, circuit board finished product is made.
(11), electric performance test：The electric property of wiring board is detected, qualified wiring board is detected and enters next processing
Link；
(12), inspection eventually：The outward appearance of finished product, hole copper thickness, thickness of dielectric layers, green oil thickness, internal layer copper thickness etc. are taken a sample test respectively,
Qualified product can shipment.
The technical scheme provided above the embodiment of the present invention is described in detail, specific case used herein
The principle and embodiment of the embodiment of the present invention are set forth, the explanation of above example is only applicable to help and understands this
The principle of inventive embodiments；Meanwhile for those of ordinary skill in the art, according to the embodiment of the present invention, in specific embodiment party
There will be changes in formula and application, in summary, this specification content should not be construed as limiting the invention.
Claims (5)
1. a kind of preparation method of superfinishing fine rule road, it is characterised in that comprise the following steps：
S1, pressing：Production plate is pressed into after PP pieces, core plate, PP pieces are overlapped successively；
S2, drilling：Drilled on production plate；
S3, sputter coating：By way of sputter coating one layer of copper plate is formed in production plate surface；
S4, heavy copper：Copper-coating is carried out to production plate, makes the hole metallization on production plate；
S5, rear process：Then making outer-layer circuit carried out to production plate successively, make solder mask, surface treatment and forming processes,
Wiring board is made.
2. the preparation method of superfinishing fine rule road according to claim 1, it is characterised in that in step S3, plated by sputtering
The mode of film forms the copper plate that a thickness is 0.5-1 μm in production plate surface.
3. the preparation method of superfinishing fine rule road according to claim 1, it is characterised in that in step S4, at heavy copper
Manage and form the heavy layers of copper that a thickness is 1-2 μm in production plate surface.
4. the preparation method of superfinishing fine rule road according to claim 1, it is characterised in that in step S5, use positive work
Skill carries out making outer-layer circuit.
5. the preparation method of superfinishing fine rule road according to claim 1, it is characterised in that in step S1, in core before pressing
Internal layer circuit is made on plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710762186.8A CN107708316A (en) | 2017-08-30 | 2017-08-30 | A kind of preparation method of superfinishing fine rule road |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710762186.8A CN107708316A (en) | 2017-08-30 | 2017-08-30 | A kind of preparation method of superfinishing fine rule road |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107708316A true CN107708316A (en) | 2018-02-16 |
Family
ID=61169880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710762186.8A Pending CN107708316A (en) | 2017-08-30 | 2017-08-30 | A kind of preparation method of superfinishing fine rule road |
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| CN (1) | CN107708316A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109451673A (en) * | 2018-11-16 | 2019-03-08 | 深圳崇达多层线路板有限公司 | A kind of production method of high-precision internal layer circuit |
| CN110996566A (en) * | 2019-12-27 | 2020-04-10 | 大连崇达电路有限公司 | Manufacturing method of high-precision multilayer circuit board |
| CN113613399A (en) * | 2021-07-21 | 2021-11-05 | 深圳市景旺电子股份有限公司 | Circuit board manufacturing method and circuit board |
| CN114554702A (en) * | 2022-02-28 | 2022-05-27 | 广东骏亚电子科技股份有限公司 | Manufacturing method of ultrathin copper-thick printed circuit board |
| CN115460781A (en) * | 2022-09-29 | 2022-12-09 | 苏州浪潮智能科技有限公司 | Impedance-controlled PCB design and manufacturing method and PCB |
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| CN102307437A (en) * | 2011-08-24 | 2012-01-04 | 上海美维科技有限公司 | Method for improving bonding force of laminated base material and laminated conductor layer in semi-additive process (SAP) |
| CN103228101A (en) * | 2013-03-14 | 2013-07-31 | 苏州热驰光电科技有限公司 | FR4 circuit board enhanced by high-thermal-conductive nano DLC (diamond-like carbon) coating |
| CN103491732A (en) * | 2013-10-08 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing circuit board layer-adding structure |
| CN103966601A (en) * | 2013-02-05 | 2014-08-06 | 汉达精密电子(昆山)有限公司 | Manufacturing method for nonmetal substrate conducting circuit and product thereof |
| CN105777210A (en) * | 2016-03-10 | 2016-07-20 | 浙江大学 | Aluminum nitride ceramic CCL (copper-clad laminate) and preparation method thereof |
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- 2017-08-30 CN CN201710762186.8A patent/CN107708316A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102307437A (en) * | 2011-08-24 | 2012-01-04 | 上海美维科技有限公司 | Method for improving bonding force of laminated base material and laminated conductor layer in semi-additive process (SAP) |
| CN103966601A (en) * | 2013-02-05 | 2014-08-06 | 汉达精密电子(昆山)有限公司 | Manufacturing method for nonmetal substrate conducting circuit and product thereof |
| CN103228101A (en) * | 2013-03-14 | 2013-07-31 | 苏州热驰光电科技有限公司 | FR4 circuit board enhanced by high-thermal-conductive nano DLC (diamond-like carbon) coating |
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| CN105777210A (en) * | 2016-03-10 | 2016-07-20 | 浙江大学 | Aluminum nitride ceramic CCL (copper-clad laminate) and preparation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109451673A (en) * | 2018-11-16 | 2019-03-08 | 深圳崇达多层线路板有限公司 | A kind of production method of high-precision internal layer circuit |
| CN110996566A (en) * | 2019-12-27 | 2020-04-10 | 大连崇达电路有限公司 | Manufacturing method of high-precision multilayer circuit board |
| CN113613399A (en) * | 2021-07-21 | 2021-11-05 | 深圳市景旺电子股份有限公司 | Circuit board manufacturing method and circuit board |
| CN114554702A (en) * | 2022-02-28 | 2022-05-27 | 广东骏亚电子科技股份有限公司 | Manufacturing method of ultrathin copper-thick printed circuit board |
| CN115460781A (en) * | 2022-09-29 | 2022-12-09 | 苏州浪潮智能科技有限公司 | Impedance-controlled PCB design and manufacturing method and PCB |
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Application publication date: 20180216 |
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