CN1149759A - 一种在半导体器件中形成精细接触孔的方法 - Google Patents
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Abstract
一种形成精细接触孔的方法,包括以下步骤:在进行干腐蚀的时候,在接触孔的侧壁上形成隔离层,其能使到接触孔的通路加宽,所以接触区几乎不受腐蚀剂的损伤。然后按照本发明的干腐蚀工艺,能减少衬底的损伤,这是因为要露出的衬底是位于绝缘保护层43的下面,衬底的损伤可以小于100A°。
Description
本发明涉及形成精细接触孔的方法,特别是能减少硅衬底损耗的方法。
通常,当在第一导电层和与第一导电层绝缘接触的第二导电层之间形成电气互连时,一定要形成接触孔,除掉与第二导电层绝缘接触的第一导电层的绝缘层的一部分。
随着半导体器件的集成度的增加,因为接触孔的高度变高及宽度变窄台阶覆盖层变差。
因此,为了获得良好的台阶覆盖层,一定要宽大地形成到接触孔的通路。因此,接触孔成为酒杯形。
图1A到图1C是表示按照现有技术的第一实施例形成接触孔方法的剖视图。
如图1A所示,在导电层1上,例如硅衬底,形成绝缘层2,在绝缘层2上形成光致抗蚀剂图形3,以便限定接触区。然后,利用光致抗蚀剂图形3作为腐蚀掩模,在绝缘层2的上面进行湿腐蚀,形成到接触孔的宽大通路。
在湿腐蚀以后,如图1B所示,用干腐蚀方法腐蚀剩下的绝缘层2,直到露出导电层1,该工艺采用相同的光致抗蚀剂图形3作掩模。最后,获得如图1C所示的腐蚀剖面。
但是,在这种常规方法中,因为湿腐蚀本身的特性,不能精确地控制“a”对“b”的比例。而且,不可能获得比由光致抗蚀剂图形3限定区域小的接触孔。
图2A和2B是表示按照现有技术第二实施例形成接触孔方法的剖视图。
如图2A所示,在导电层21上,例如硅衬底上,形成绝缘层22,在绝缘层22上形成光致抗蚀剂图形(未表示),以便限定接触区。然后对绝缘层22进行干腐蚀,露出导电层21的表面。
在干腐蚀后,如图2B所示,对已构图的绝缘层22进行掩蔽腐蚀以便加宽接触孔的通路。
在第二实施例中,可利用简单工艺获得良好的外形。但是,不可能获得比给定接触掩模(光致抗蚀剂图形)限定的区域小的接触孔。而且该方法的缺点是难于在掩蔽腐蚀工艺中控制露出层的损耗。由于绝缘层通常由利用多层绝缘层形成的叠层组成,所以在接触孔的侧壁上露出不均匀的叠层绝缘层。因此,在淀积金属层之前,在对叠层进行各向同性腐蚀时,因为绝缘层各处腐蚀率不同,在接触孔的侧壁上产生凸起和凹坑。
图3是表示按现有技术第三实施例形成接触孔方法的剖视图。该方法被称为侧氧化隔离接触(下文称为SOSCON)方法。
如图3所示,这种方法在接触孔的侧壁上形成隔离层。也就是,在导电层31上,例如硅衬底上,形成第一绝缘层32,在第一绝缘层32上形成光致抗蚀剂层图形(未表示),以便限定接触区。然后用干腐蚀工艺腐蚀绝缘层32,露出导电层31的表面。接着,淀积作为隔离层的第二绝缘层33,用掩蔽腐蚀来腐蚀第二绝缘层33。
该SOSCON方法有下述优点,隔离层能有助于形成精细接触孔。但是,因为到接触孔的通路不能变宽,该方法存在产生不良台阶覆盖层的问题。
特别是,利用SOSCON方法和倾斜干腐蚀方法(the dry slop etchingprocess)来形成接触孔时(例如,在完成如图2所示的工艺后,进行如图3所示的工艺),在倾斜干腐蚀工艺中由于等离子体使衬底产生损耗。也就是形成隔离层的SOSCON方法在接着进行的倾斜干腐蚀中,使接触区的衬底暴露到腐蚀剂。结果,在进行倾斜干腐蚀期间,接触区中的衬底被腐蚀剂腐蚀,使露出的衬底被显著的腐蚀。
因此,本发明的目的是提供一种方法,用于形成精细接触孔,利用隔离层进行倾斜干腐蚀工艺,能使硅衬底减少损耗。
按照本发明一个方面,提供一种方法,其包括下列步骤:在衬底上形成第一绝缘层;除掉第一绝缘层的部分,露出衬底;在所得结构上形成作为隔离层的第二绝缘层;对第一和第二绝缘层进行干腐蚀,以便加宽到接触孔的通路,和在接触孔的侧壁上形成隔离层。
从下述结合附图对实施例的说明,本发明的其它目的和方案将变得显而易见,其中:
图1A到图1C是表示按照现有技术第一实施例形成接触孔方法的剖视图;
图2A和图2B是表示现有技术第二实施例形成接触孔方法的剖视图;
图3是表示现有技术第三实施例形成接触孔方法的剖视图;
图4A到图4C是表示按照本发明一个实施例能够减小形成接触孔中衬底损耗的方法的剖视图。
下面参照附图4A至4C详细地说明本发明的实施例,其中所示的方法能够减小按照本发明实施例形成接触孔中衬底的损耗。
首先,图4A表示利用光致抗蚀剂图形(未表示)限定接触区的步骤。在衬底41上所形成的绝缘层42上,形成光致抗蚀剂图形来限定的接触区。绝缘层42由氧化硅层、氮化硅层、氮氧化硅层或它们的叠层组成。利用光刻工艺,把光致抗蚀剂图形作为腐蚀掩模,除掉绝缘层42,由此露出要和金属层连接的那部分衬底。
接着参看图4B,在获得的结构上,形成作为隔离层的绝缘层43。该隔离层可能缩小由光致抗蚀剂图形形成的接触区尺寸。
接着,如图4C所示,不用腐蚀掩模,对绝缘层42和43进行干腐蚀,此时,通过适当地控制工艺条件进行干腐蚀。应当注意,干腐蚀工艺在一步工序上同时形成隔离层和通到接触孔的宽大通路。
在优选实施例中,把器件装入用ICP(感应耦合等离子体)方法的等离子真空室,其具有加热的硅板。此时加工条件如下:
处理气体:CF4,CHF3,CH3F,C2F6,C3F8,C2H2F4,或者,它们的化合物气体
气体流量:15-50sccm
源RF功率:1800-2800瓦
偏压RF功率:700-1600瓦
硅板加热温度:220-280℃
腐蚀附加气体:Ar,He,Co,O2或它们的化合物气体。
按照本发明形成接触孔的方法,由于在进行干腐蚀的时候,在接触孔中的侧壁上形成隔离层,它加宽了到接触孔的通路,则如图4A所示的接触区,几乎不被腐蚀剂损伤。因此,按照本发明的干腐蚀能减小衬底的损耗,因为,将要露出的衬底是在绝缘保护层43下面可能使衬底损伤小于106A°。
由上述可见,本发明具有可以获得良好台阶覆盖层的效果,减小衬底的损耗。而且本发明提供一种方法,利用隔离层形成0.2μm或更小的精细图形。另外,可利用本发明形成连接第一导电层和第二导电层的通孔。
虽然,为了说明本发明公开了本发明的各优选实施例,但是本领域技术人员应该了解,在不脱离权利要求公开的本发明的范围和精神实质的条件下,可以进行各种修改、增加和替换。
Claims (11)
1、一种形成精细接触孔的方法,包括下列步骤:
在导电层上形成第一绝缘层;
除掉部分第一绝缘层,露出导电层;
在获得的结构上形成用作隔离层的第二绝缘层;及
用干腐蚀工艺腐蚀第一和第二绝缘层,以便使到接触孔的通路加宽,同时在接触孔的侧壁上形成隔离层。
2、按照权利要求1的方法,其中,利用感应耦合等离子方法,进行干腐蚀处理。
3、按照权利要求1的方法,其中,干腐蚀工艺利用CF4,CHF3,CH3F,C2F6,C3F8,C2H2F2,或它们的化合物气体作为腐蚀气体。
4、按照权利要求3的方法,其中,腐蚀气体还包括Ar、He、Co、O2或它们的化合物气体中的一种或两种作为附加气体。
5、按照权利要求3的方法,其中,腐蚀气体流量近似为15-50sccm。
6、按照权利要求1的方法,其中,在RP功率源为大约1800到2800瓦的处理室中,进行第一和第二绝缘层的干腐蚀工艺的步骤。
7、按照权利要求6的方法,其中,处理室的偏压RP功率大约为700到1600瓦。
8、按照权利要求2的方法,其中,在具有加热硅板的处理室中,进行第一和第二绝缘层的干腐蚀工艺的步骤。
9、按照权利要求8的方法,其中,硅板的温度为大约220-280℃。
10、按照权利要求1的方法,其中,导电层是硅衬底。
11、按照权利要求1的方法,其中,第一绝缘层是利用多层绝缘层形成的叠层。
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KR1019950026990A KR0171733B1 (ko) | 1995-08-28 | 1995-08-28 | 반도체 소자의 콘택홀 형성 방법 |
KR26990/95 | 1995-08-28 | ||
KR26990/1995 | 1995-08-28 |
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CN1149759A true CN1149759A (zh) | 1997-05-14 |
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Cited By (6)
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CN103219304A (zh) * | 2013-04-19 | 2013-07-24 | 昆山西钛微电子科技有限公司 | 半导体晶圆级封装结构及其制备方法 |
CN102087963B (zh) * | 2009-12-04 | 2013-08-14 | 无锡华润上华半导体有限公司 | 多晶硅层的蚀刻方法 |
CN104979274A (zh) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔形成方法 |
CN105789111A (zh) * | 2014-12-18 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN107390391A (zh) * | 2017-06-20 | 2017-11-24 | 武汉华星光电技术有限公司 | 一种过孔的制作方法 |
CN113130382A (zh) * | 2020-01-16 | 2021-07-16 | 长鑫存储技术有限公司 | 半导体器件及其制备方法 |
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US6159862A (en) * | 1997-12-27 | 2000-12-12 | Tokyo Electron Ltd. | Semiconductor processing method and system using C5 F8 |
US6228279B1 (en) * | 1998-09-17 | 2001-05-08 | International Business Machines Corporation | High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials |
US7687407B2 (en) * | 2004-12-02 | 2010-03-30 | Texas Instruments Incorporated | Method for reducing line edge roughness for conductive features |
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JPS59181614A (ja) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | 半導体装置の製造方法 |
IT1225636B (it) * | 1988-12-15 | 1990-11-22 | Sgs Thomson Microelectronics | Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio |
US5556501A (en) * | 1989-10-03 | 1996-09-17 | Applied Materials, Inc. | Silicon scavenger in an inductively coupled RF plasma reactor |
KR920015542A (ko) * | 1991-01-14 | 1992-08-27 | 김광호 | 반도체장치의 다층배선형성법 |
US5477975A (en) * | 1993-10-15 | 1995-12-26 | Applied Materials Inc | Plasma etch apparatus with heated scavenging surfaces |
JPH0832053A (ja) * | 1994-07-12 | 1996-02-02 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3049228B2 (ja) * | 1998-04-27 | 2000-06-05 | 株式会社アイエス | フラッシュバルブ開閉装置 |
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1995
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- 1996-08-28 CN CN96113323A patent/CN1077725C/zh not_active Expired - Fee Related
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Cited By (9)
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CN102087963B (zh) * | 2009-12-04 | 2013-08-14 | 无锡华润上华半导体有限公司 | 多晶硅层的蚀刻方法 |
CN103219304A (zh) * | 2013-04-19 | 2013-07-24 | 昆山西钛微电子科技有限公司 | 半导体晶圆级封装结构及其制备方法 |
CN104979274A (zh) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔形成方法 |
CN104979274B (zh) * | 2014-04-04 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔形成方法 |
CN105789111A (zh) * | 2014-12-18 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN105789111B (zh) * | 2014-12-18 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN107390391A (zh) * | 2017-06-20 | 2017-11-24 | 武汉华星光电技术有限公司 | 一种过孔的制作方法 |
CN113130382A (zh) * | 2020-01-16 | 2021-07-16 | 长鑫存储技术有限公司 | 半导体器件及其制备方法 |
CN113130382B (zh) * | 2020-01-16 | 2022-03-08 | 长鑫存储技术有限公司 | 半导体器件及其制备方法 |
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TW374203B (en) | 1999-11-11 |
US5767019A (en) | 1998-06-16 |
CN1077725C (zh) | 2002-01-09 |
KR970013051A (ko) | 1997-03-29 |
KR0171733B1 (ko) | 1999-03-30 |
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