US20070278611A1 - Modified Facet Etch to Prevent Blown Gate Oxide and Increase Etch Chamber Life - Google Patents

Modified Facet Etch to Prevent Blown Gate Oxide and Increase Etch Chamber Life Download PDF

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US20070278611A1
US20070278611A1 US11/839,766 US83976607A US2007278611A1 US 20070278611 A1 US20070278611 A1 US 20070278611A1 US 83976607 A US83976607 A US 83976607A US 2007278611 A1 US2007278611 A1 US 2007278611A1
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conductive structures
exposed layer
etch
target depth
depth
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US11/839,766
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William Polinsky
Thomas Kari
Mark Bossler
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Definitions

  • This invention relates to semiconductor manufacture, and more particularly to facet etching useful for improving subsequent dielectric layer step coverage.
  • Step coverage refers to the ability of subsequent layers to evenly cover layers (“steps”) already present on the substrate. Facet etches are frequently used to provide superior step coverage.
  • the standard facet etch uses a high energy argon ion which physically bombards the material being etched and thereby etches the oxide at an angle to allow subsequent material to have the best step coverage possible.
  • the argon ions etch through the oxide and reach metal or another conductor, they disperse their energy into the metal line or other conductor. This energy finds its way to a ground through a weak spot in the gate oxide thereby resulting in a blown gate.
  • sputter etching In sputter etching, ions which impinge on horizontal surfaces have a minimal effect on etch rate and profile. However, the sputter yield of the etch at the corners is approximately four times that of the etch rate of a horizontal surface, thereby creating an extreme etch profile. The effect is the wearing away of the corners of a feature at approximately 45 degree angles. The material removed by the sputter etch is redeposited along the sides of the feature and along the surface of the substrate.
  • the process of the present invention employs a two-step etching sequence wherein an insulating layer deposited on top of a plurality of conductive structures is first etched by a high energy inert gas ion to physically sputter the oxide material and form a faceted etch.
  • the first step etch is terminated prior to reaching a predetermined target depth.
  • the second step etch is conducted with a reactant gas to further remove the insulating material down to the target depth.
  • the method of the invention comprises forming a first layer comprising an insulating material superjacent a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures, such that the first layer forms in at least some of the spaces between the conductive structures and the first layer is formed to a thickness at least equal to the target depth.
  • the first layer is etched by directing a plasma of an inert gas at the first layer formed in at least some of the spaces between the conductive structures. The plasma is of sufficient energy to sputter material from the first layer thereby forming a facet etch in the first layer formed in the spaces between the conductive structures.
  • the first etch is terminated when the first layer has been etched to a predetermined depth which is less than the target depth.
  • the first layer is etched, in a second etch, by contacting the first layer with a reactive chemical gas/plasma. The second etch is terminated when the first layer has been etched to the target depth.
  • FIG. 1 is a schematic view of a semiconductor device having a plurality of conductive structures.
  • FIG. 2 is a schematic view of the semiconductor device of FIG. 1 at a later stage in the process.
  • FIG. 3 shows a schematic view of a portion of the semiconductor device of FIG. 2 .
  • FIG. 4 shows the semiconductor device of FIG. 2 at a later stage in the process.
  • FIG. 5 shows a portion of the semiconductor device of FIG. 4 .
  • FIG. 6 shows the semiconductor device of FIG. 4 at a later stage of the process.
  • FIG. 1 shows a semiconductor device 1 suitable for use in a preferred embodiment of this invention.
  • the semiconductor device I comprises a plurality of conductive structures 12 overlying a substrate 10 .
  • the conductive structures 12 are positioned in close proximity to each other to form spaces 14 between the conductive structures 12 .
  • Conductive structures 12 can be any conductive element of semiconductor device 1 but are typically metal lines, runners, leads or interconnects. Conductive structures 12 typically comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof.
  • the substrate 10 includes any semiconductor-based structure having a silicon base.
  • the base of substrate 10 is to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, previous process steps may have been used to form regions or junctions in the base semiconductor structure or foundation.
  • the substrate 10 will comprise at least one layer of material deposited on top of the silicon base.
  • the uppermost layer of material of substrate 10 which contacts conductive structures 12 , will be a dielectric material such as silicon dioxide or boron phosphosilicate glass (BPSG).
  • BPSG boron phosphosilicate glass
  • a first layer 16 is formed over the substrate 10 and conductive structures 12 as shown in FIG. 2 .
  • First layer 16 comprises a dielectric material 17 , preferably silicon dioxide or BPSG.
  • First layer 16 may be conveniently formed by chemical vapor deposition or any other suitable means.
  • the spaces 14 between the conductive structures 12 are not completely or uniformly filled during the formation of first layer 16 .
  • the bottom 37 and lower corners 36 of space 14 are covered with a thinner depth of dielectric material 17 than are the sidewalls 38 and upper corners 35 .
  • This nonuniform coverage of dielectric material 17 leads to the formation of undesirable voids, known as keyholes within the first layer 10 or between the first layer 10 and subsequent layers.
  • a facet etch is performed to provide a lower aspect opening for subsequent layers as shown in FIG. 4 .
  • the facet etch is conveniently performed by placing the semiconductor device 1 in a high vacuum reactor on a cathode for which a power source creates a radio frequency (RF) of 13.56 Mhz, while controlling the introduction of the etchant gases.
  • RF radio frequency
  • the walls of the reactor are grounded to allow for a return RF path.
  • This chamber configuration is generally referred to as a Reactive Ion Etcher (R.I.E.).
  • the RF power source acts to create a plasma condition within the chamber, thereby allowing for the creation of charged particles or ions 40 .
  • a direct current self-bias voltage condition is created at the semiconductor device 1 location. This self-bias condition acts to direct the charged particles or ions 40 toward the semiconductor device 1 in a direction perpendicular to the device surface 1 .
  • the mean free path of the charged particles or ions 40 will be great enough to allow for physical sputtering of dielectric material 17 when the ions 40 impinge on the surface of the first layer 12 . It is important to note that a wide variety of systems and parameters can be used to effect a facet etch, as long as the pressure limit is not violated. As the pressure nears and exceeds 30 mtorr, the results of the process are effected.
  • the facet etch is performed for a time sufficient to obtain holes with sloping sides 42 in first layer 16 as shown in FIG. 4 .
  • the facet etch is terminated at depth 51 prior to removing the dielectric material 17 to a predetermined target depth 53 as shown in FIG. 5 .
  • the facet etch is terminated at a depth at least half of the target depth. For example, if the target depth is 300 ⁇ , the facet etch will be at least 150 ⁇ .
  • the facet etch is as deep as possible, as constrained by the possibility of etching through first layer 12 , in order to allow the second etch to maintain the facet contour.
  • the facet etch is terminated less than about 150 ⁇ , preferably no more than about 100 ⁇ , more preferably, not more than about 50 ⁇ prior to the target depth 53 .
  • Some of the sputtered dielectric material 17 redeposits 55 in bottom corners 36 .
  • RIE reactive ion etch
  • a second layer 64 may then be formed over first layer 10 with the formation of only minimized keyholes 66 . Additionally, the upper surface 68 of the second layer is relatively even.
  • the sputtered dielectric material redeposits onto the interior surfaces of the etching chamber.
  • the sputtered material which redeposits onto the chamber surfaces gradually builds up to a depth sufficient to impair the operation of the etching chamber.
  • the etching chamber must be taken off-line for cleaning and reconditioning.
  • An additional benefit to the current two-stage process is that the second stage reactive ion etch also etches the material building up on the chamber surfaces. As such, the etching chamber is at least partially cleaned on-line and the time between off-line cleaning and reconditioning is greatly extended.

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
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  • Electrodes Of Semiconductors (AREA)

Abstract

A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the target depth for the etching process. The second stage etch is a reactive ion etch which directionally follows the facet profile to reach the target depth.

Description

    CROSS-REFERENCE TO RELATED U.S. PATENT APPLICATIONS
  • This application is a Divisional of U.S. application Ser. No. 10/887,049 filed Jul. 8, 2004, now U.S. Pat. No. 7,262,136, issued Aug. 28, 2007, which is a Continuation of U.S. application Ser. No. 09/854,975 filed May 14, 2001, now U.S. Pat. No. 6,762,125, issued Jul. 13, 2004, all applications hereby incorporated herein by reference.
    • FIELD OF THE INVENTION
  • This invention relates to semiconductor manufacture, and more particularly to facet etching useful for improving subsequent dielectric layer step coverage.
    • BACKGROUND OF THE INVENTION
  • A major goal of any dielectric deposition system is good step coverage. Step coverage refers to the ability of subsequent layers to evenly cover layers (“steps”) already present on the substrate. Facet etches are frequently used to provide superior step coverage. The standard facet etch uses a high energy argon ion which physically bombards the material being etched and thereby etches the oxide at an angle to allow subsequent material to have the best step coverage possible. However, if the argon ions etch through the oxide and reach metal or another conductor, they disperse their energy into the metal line or other conductor. This energy finds its way to a ground through a weak spot in the gate oxide thereby resulting in a blown gate.
  • In sputter etching, ions which impinge on horizontal surfaces have a minimal effect on etch rate and profile. However, the sputter yield of the etch at the corners is approximately four times that of the etch rate of a horizontal surface, thereby creating an extreme etch profile. The effect is the wearing away of the corners of a feature at approximately 45 degree angles. The material removed by the sputter etch is redeposited along the sides of the feature and along the surface of the substrate.
  • An issue associated with sputter etching is that some of the sputtered material redeposits frequently on the inside surfaces of the etching chamber. This redeposited material must be removed at intervals, thereby taking the etching chamber off-line.
    • SUMMARY OF THE INVENTION
  • The process of the present invention employs a two-step etching sequence wherein an insulating layer deposited on top of a plurality of conductive structures is first etched by a high energy inert gas ion to physically sputter the oxide material and form a faceted etch. The first step etch is terminated prior to reaching a predetermined target depth. The second step etch is conducted with a reactant gas to further remove the insulating material down to the target depth.
  • In a preferred embodiment, the method of the invention comprises forming a first layer comprising an insulating material superjacent a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures, such that the first layer forms in at least some of the spaces between the conductive structures and the first layer is formed to a thickness at least equal to the target depth. Next, the first layer is etched by directing a plasma of an inert gas at the first layer formed in at least some of the spaces between the conductive structures. The plasma is of sufficient energy to sputter material from the first layer thereby forming a facet etch in the first layer formed in the spaces between the conductive structures. The first etch is terminated when the first layer has been etched to a predetermined depth which is less than the target depth. Next, the first layer is etched, in a second etch, by contacting the first layer with a reactive chemical gas/plasma. The second etch is terminated when the first layer has been etched to the target depth.
  • Various other features, objects and advantages of the present invention will be made apparent from the following detailed description and the drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts.
  • FIG. 1 is a schematic view of a semiconductor device having a plurality of conductive structures.
  • FIG. 2 is a schematic view of the semiconductor device of FIG. 1 at a later stage in the process.
  • FIG. 3 shows a schematic view of a portion of the semiconductor device of FIG. 2.
  • FIG. 4 shows the semiconductor device of FIG. 2 at a later stage in the process.
  • FIG. 5 shows a portion of the semiconductor device of FIG. 4.
  • FIG. 6 shows the semiconductor device of FIG. 4 at a later stage of the process.
    • DETAILED DESCRIPTION OF THE INVENTION
  • In the following detailed description, references made to the accompanying drawings which form a part hereof and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.
  • FIG. 1 shows a semiconductor device 1 suitable for use in a preferred embodiment of this invention. The semiconductor device I comprises a plurality of conductive structures 12 overlying a substrate 10. The conductive structures 12 are positioned in close proximity to each other to form spaces 14 between the conductive structures 12.
  • Conductive structures 12 can be any conductive element of semiconductor device 1 but are typically metal lines, runners, leads or interconnects. Conductive structures 12 typically comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof.
  • The substrate 10 includes any semiconductor-based structure having a silicon base. The base of substrate 10 is to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, previous process steps may have been used to form regions or junctions in the base semiconductor structure or foundation. Typically, the substrate 10 will comprise at least one layer of material deposited on top of the silicon base. In one preferred embodiment, the uppermost layer of material of substrate 10, which contacts conductive structures 12, will be a dielectric material such as silicon dioxide or boron phosphosilicate glass (BPSG).
  • A first layer 16 is formed over the substrate 10 and conductive structures 12 as shown in FIG. 2. First layer 16 comprises a dielectric material 17, preferably silicon dioxide or BPSG. First layer 16 may be conveniently formed by chemical vapor deposition or any other suitable means.
  • As shown in FIG. 3, the spaces 14 between the conductive structures 12 are not completely or uniformly filled during the formation of first layer 16. In particular, the bottom 37 and lower corners 36 of space 14 are covered with a thinner depth of dielectric material 17 than are the sidewalls 38 and upper corners 35. This nonuniform coverage of dielectric material 17 leads to the formation of undesirable voids, known as keyholes within the first layer 10 or between the first layer 10 and subsequent layers.
  • A facet etch is performed to provide a lower aspect opening for subsequent layers as shown in FIG. 4. The facet etch is conveniently performed by placing the semiconductor device 1 in a high vacuum reactor on a cathode for which a power source creates a radio frequency (RF) of 13.56 Mhz, while controlling the introduction of the etchant gases.
  • The walls of the reactor are grounded to allow for a return RF path. This chamber configuration is generally referred to as a Reactive Ion Etcher (R.I.E.). The RF power source acts to create a plasma condition within the chamber, thereby allowing for the creation of charged particles or ions 40.
  • Due to the physics of the RF powered electrode, a direct current self-bias voltage condition is created at the semiconductor device 1 location. This self-bias condition acts to direct the charged particles or ions 40 toward the semiconductor device 1 in a direction perpendicular to the device surface 1.
  • If the pressure is in a range being slightly less than 30 mtorr, the mean free path of the charged particles or ions 40 will be great enough to allow for physical sputtering of dielectric material 17 when the ions 40 impinge on the surface of the first layer 12. It is important to note that a wide variety of systems and parameters can be used to effect a facet etch, as long as the pressure limit is not violated. As the pressure nears and exceeds 30 mtorr, the results of the process are effected.
  • Typical parameters for facet etching using an Applied Materials 5000 Series equipment are as follows:
  • RF power: 300-700 watts
  • pressure: 10-30 mtorr
  • etchant: 30-70 sccm.
  • The facet etch is performed for a time sufficient to obtain holes with sloping sides 42 in first layer 16 as shown in FIG. 4. The facet etch is terminated at depth 51 prior to removing the dielectric material 17 to a predetermined target depth 53 as shown in FIG. 5. The facet etch is terminated at a depth at least half of the target depth. For example, if the target depth is 300 Å, the facet etch will be at least 150 Å. Preferably, the facet etch is as deep as possible, as constrained by the possibility of etching through first layer 12, in order to allow the second etch to maintain the facet contour. Typically, the facet etch is terminated less than about 150 Å, preferably no more than about 100 Å, more preferably, not more than about 50 Å prior to the target depth 53. Some of the sputtered dielectric material 17 redeposits 55 in bottom corners 36.
  • Subsequent to the termination of the facet etch, a chemical reactive ion etch (RIE) is performed on first layer 16. The RIE is a directional etch which removes dielectric material 17 along the profile established by the facet etch. The RIE is terminated when sufficient dielectric material 17 is removed to reach the target depth 53. This two-stage etch therefore results in a profiled etch of the desired depth.
  • As shown in FIG. 6, a second layer 64 may then be formed over first layer 10 with the formation of only minimized keyholes 66. Additionally, the upper surface 68 of the second layer is relatively even.
  • As is typical with any sputter process, some of the sputtered dielectric material redeposits onto the interior surfaces of the etching chamber. The sputtered material which redeposits onto the chamber surfaces gradually builds up to a depth sufficient to impair the operation of the etching chamber. At that time, the etching chamber must be taken off-line for cleaning and reconditioning. An additional benefit to the current two-stage process is that the second stage reactive ion etch also etches the material building up on the chamber surfaces. As such, the etching chamber is at least partially cleaned on-line and the time between off-line cleaning and reconditioning is greatly extended.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (22)

1. An intermediate for a semiconductor device, the intermediate comprising:
a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures;
an exposed layer of insulating material which is in direct contact with the substrate and in at least some of the spaces between the conductive structures, wherein the semiconductor device requires a facet etch to a target depth in the exposed layer; and,
a facet etch in the exposed layer having a predetermined depth which is less than the target depth.
2. The intermediate of claim 1 wherein the exposed layer comprises silicon dioxide or boron phosphosilicate glass.
3. The intermediate of claim 1 wherein the conductive structures form at least one of metal lines, interconnects and leads.
4. The intermediate of claim 1 wherein the conductive structures comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof.
5. The intermediate of claim 1 wherein the predetermined depth is no more than about 150 Å less than the target depth.
6. The intermediate of claim 1 wherein the predetermined depth is no more than about 100 Å less than the target depth.
7. The intermediate of claim 1 wherein the predetermined depth is about 50 Å less than the target depth.
8. An intermediate for a semiconductor device that requires a facet etch to a target depth in an exposed layer of insulating material, the intermediate comprising:
a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures;
an exposed layer of insulating material which is in direct contact with the substrate and in at least some of the spaces between the conductive structures; and,
an intermediate facet etch in the exposed layer having a predetermined depth which is less than the target depth, wherein the intermediate facet etch was formed by a sputter etching method.
9. The intermediate of claim 8 wherein the exposed layer comprises silicon dioxide or boron phosphosilicate glass.
10. The intermediate of claim 8 wherein the conductive structures form at least one of metal lines, interconnects and leads.
11. The intermediate of claim 8 wherein the conductive structures comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof.
12. The intermediate of claim 8 wherein the predetermined depth is no more than about 150 Å less than the target depth.
13. The intermediate of claim 8 wherein the predetermined depth is no more than about 100 Å less than the target depth.
14. The intermediate of claim 8 wherein the predetermined depth is about 50 Å less than the target depth.
15. The intermediate of claim 8 wherein the sputter etching method comprises etching the exposed layer by directing a plasma beam at the exposed layer formed in at least some of the spaces between the conductive structures, wherein the plasma is of sufficient energy to sputter material from the exposed layer and the plasma is an ion of an inert gas.
16. A method of making a semiconductor device that requires a facet etch to a target depth in an exposed layer of insulating material, the method comprising:
providing an the intermediate comprising: a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures; an exposed layer of insulating material which is in direct contact with the substrate and in at least some of the spaces between the conductive structures; and, an intermediate facet etch in the exposed layer having a predetermined depth which is less than the target depth, wherein the intermediate facet etch was formed by a sputter etching method;
etching the exposed layer by contacting the exposed layer with a reactive chemical gas/plasma; and
terminating the etch when the exposed layer has been etched to the target depth.
17. The method of claim 16 wherein the exposed layer comprises silicon dioxide or boron phosphosilicate glass.
18. The method of claim 16 wherein the conductive structures form at least one of metal lines, interconnects and leads.
19. The method of claim 16 wherein the conductive structures comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof.
20. The method of claim 16 wherein the predetermined depth is no more than about 150 Å less than the target depth.
21. The method of claim 16 wherein the predetermined depth is no more than about 100 Å less than the target depth.
22. The method of claim 16 wherein the predetermined depth is about 50 Å less than the target depth.
US11/839,766 2001-05-14 2007-08-16 Modified Facet Etch to Prevent Blown Gate Oxide and Increase Etch Chamber Life Abandoned US20070278611A1 (en)

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US09/854,975 US6762125B1 (en) 2001-05-14 2001-05-14 Modified facet etch to prevent blown gate oxide and increase etch chamber life
US10/887,049 US7262136B2 (en) 2001-05-14 2004-07-08 Modified facet etch to prevent blown gate oxide and increase etch chamber life
US11/839,766 US20070278611A1 (en) 2001-05-14 2007-08-16 Modified Facet Etch to Prevent Blown Gate Oxide and Increase Etch Chamber Life

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US10/887,049 Division US7262136B2 (en) 2001-05-14 2004-07-08 Modified facet etch to prevent blown gate oxide and increase etch chamber life

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8696875B2 (en) 1999-10-08 2014-04-15 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
US10047430B2 (en) 1999-10-08 2018-08-14 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
US6762125B1 (en) * 2001-05-14 2004-07-13 Micron Technology, Inc. Modified facet etch to prevent blown gate oxide and increase etch chamber life
US7504006B2 (en) * 2002-08-01 2009-03-17 Applied Materials, Inc. Self-ionized and capacitively-coupled plasma for sputtering and resputtering
US6784096B2 (en) * 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
KR100675895B1 (en) * 2005-06-29 2007-02-02 주식회사 하이닉스반도체 Metal interconnection of semiconductor device and method of fabricating the same
US8691622B2 (en) 2012-05-25 2014-04-08 Micron Technology, Inc. Memory cells and methods of forming memory cells
US10084056B1 (en) * 2017-03-20 2018-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of manufacturing the same

Citations (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US5202008A (en) * 1990-03-02 1993-04-13 Applied Materials, Inc. Method for preparing a shield to reduce particles in a physical vapor deposition chamber
US5203957A (en) * 1991-06-12 1993-04-20 Taiwan Semiconductor Manufacturing Company Contact sidewall tapering with argon sputtering
US5302233A (en) * 1993-03-19 1994-04-12 Micron Semiconductor, Inc. Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP)
US5346585A (en) * 1993-04-20 1994-09-13 Micron Semiconductor, Inc. Use of a faceted etch process to eliminate stringers
US5416048A (en) * 1993-04-16 1995-05-16 Micron Semiconductor, Inc. Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage
US5658818A (en) * 1994-11-02 1997-08-19 Micron Technology, Inc. Semiconductor processing method employing an angled sidewall
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US5744196A (en) * 1995-01-04 1998-04-28 Air Products And Chemicals, Inc. Low temperature deposition of silicon dioxide using organosilanes
US5789314A (en) * 1995-12-05 1998-08-04 Integrated Device Technology, Inc. Method of topside and inter-metal oxide coating
US5814564A (en) * 1997-05-15 1998-09-29 Vanguard International Semiconductor Corporation Etch back method to planarize an interlayer having a critical HDP-CVD deposition process
US5858865A (en) * 1995-12-07 1999-01-12 Micron Technology, Inc. Method of forming contact plugs
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US5892285A (en) * 1996-02-02 1999-04-06 Micron Technology, Inc. Semiconductor connection with a top surface having an enlarged recess
US5935875A (en) * 1996-08-20 1999-08-10 Samsung Electronics Co., Ltd. Dual insulating layer methods for forming integrated circuit gates and conductive contacts
US5985767A (en) * 1996-01-31 1999-11-16 Micron Technology, Inc. Facet etch for improved step coverage of integrated circuit contacts
US5997699A (en) * 1996-04-08 1999-12-07 Micron Technology Inc. Insitu faceting during deposition
US6001541A (en) * 1998-03-27 1999-12-14 Micron Technology, Inc. Method of forming contact openings and contacts
US6069398A (en) * 1997-08-01 2000-05-30 Advanced Micro Devices, Inc. Thin film resistor and fabrication method thereof
US6136695A (en) * 1999-08-04 2000-10-24 Taiwan Semiconductor Manufacturing Company Method for fabricating a self-aligned contact
US6143649A (en) * 1998-02-05 2000-11-07 Micron Technology, Inc. Method for making semiconductor devices having gradual slope contacts
US6177802B1 (en) * 1998-08-10 2001-01-23 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device using the hall-effect
US6191050B1 (en) * 1996-12-19 2001-02-20 Intel Corporation Interlayer dielectric with a composite dielectric stack
US6191026B1 (en) * 1996-01-09 2001-02-20 Applied Materials, Inc. Method for submicron gap filling on a semiconductor substrate
US6565721B1 (en) * 1996-04-04 2003-05-20 Micron Technology, Inc. Use of heavy halogens for enhanced facet etching
US6762125B1 (en) * 2001-05-14 2004-07-13 Micron Technology, Inc. Modified facet etch to prevent blown gate oxide and increase etch chamber life

Patent Citations (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US5202008A (en) * 1990-03-02 1993-04-13 Applied Materials, Inc. Method for preparing a shield to reduce particles in a physical vapor deposition chamber
US5203957A (en) * 1991-06-12 1993-04-20 Taiwan Semiconductor Manufacturing Company Contact sidewall tapering with argon sputtering
US5302233A (en) * 1993-03-19 1994-04-12 Micron Semiconductor, Inc. Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP)
US5416048A (en) * 1993-04-16 1995-05-16 Micron Semiconductor, Inc. Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage
US5346585A (en) * 1993-04-20 1994-09-13 Micron Semiconductor, Inc. Use of a faceted etch process to eliminate stringers
US5658818A (en) * 1994-11-02 1997-08-19 Micron Technology, Inc. Semiconductor processing method employing an angled sidewall
US5744196A (en) * 1995-01-04 1998-04-28 Air Products And Chemicals, Inc. Low temperature deposition of silicon dioxide using organosilanes
US5789314A (en) * 1995-12-05 1998-08-04 Integrated Device Technology, Inc. Method of topside and inter-metal oxide coating
US5858865A (en) * 1995-12-07 1999-01-12 Micron Technology, Inc. Method of forming contact plugs
US6191026B1 (en) * 1996-01-09 2001-02-20 Applied Materials, Inc. Method for submicron gap filling on a semiconductor substrate
US5985767A (en) * 1996-01-31 1999-11-16 Micron Technology, Inc. Facet etch for improved step coverage of integrated circuit contacts
US5892285A (en) * 1996-02-02 1999-04-06 Micron Technology, Inc. Semiconductor connection with a top surface having an enlarged recess
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US6565721B1 (en) * 1996-04-04 2003-05-20 Micron Technology, Inc. Use of heavy halogens for enhanced facet etching
US5997699A (en) * 1996-04-08 1999-12-07 Micron Technology Inc. Insitu faceting during deposition
US5935875A (en) * 1996-08-20 1999-08-10 Samsung Electronics Co., Ltd. Dual insulating layer methods for forming integrated circuit gates and conductive contacts
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US6191050B1 (en) * 1996-12-19 2001-02-20 Intel Corporation Interlayer dielectric with a composite dielectric stack
US5814564A (en) * 1997-05-15 1998-09-29 Vanguard International Semiconductor Corporation Etch back method to planarize an interlayer having a critical HDP-CVD deposition process
US5872058A (en) * 1997-06-17 1999-02-16 Novellus Systems, Inc. High aspect ratio gapfill process by using HDP
US6069398A (en) * 1997-08-01 2000-05-30 Advanced Micro Devices, Inc. Thin film resistor and fabrication method thereof
US6143649A (en) * 1998-02-05 2000-11-07 Micron Technology, Inc. Method for making semiconductor devices having gradual slope contacts
US6001541A (en) * 1998-03-27 1999-12-14 Micron Technology, Inc. Method of forming contact openings and contacts
US6177802B1 (en) * 1998-08-10 2001-01-23 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device using the hall-effect
US6136695A (en) * 1999-08-04 2000-10-24 Taiwan Semiconductor Manufacturing Company Method for fabricating a self-aligned contact
US6762125B1 (en) * 2001-05-14 2004-07-13 Micron Technology, Inc. Modified facet etch to prevent blown gate oxide and increase etch chamber life

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