CN114823667A - 具有用于有效应力转移的mos晶体管的半导体装置 - Google Patents

具有用于有效应力转移的mos晶体管的半导体装置 Download PDF

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CN114823667A
CN114823667A CN202210086447.XA CN202210086447A CN114823667A CN 114823667 A CN114823667 A CN 114823667A CN 202210086447 A CN202210086447 A CN 202210086447A CN 114823667 A CN114823667 A CN 114823667A
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liner film
region
gate electrode
film
regions
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今本拓也
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请案涉及一种具有用于有效应力转移的MOS晶体管的半导体装置。本文公开一种方法，所述方法包含：在由STI区围绕的半导体衬底的作用区上形成栅极电极；通过使用所述栅极电极作为掩模将第一掺杂剂植入到所述作用区中以形成LDD区；在所述栅极电极、所述STI区和所述LDD区的顶表面和侧表面上形成衬层膜；在所述栅极电极的所述侧表面上形成侧壁间隔件，其中所述衬层膜插入所述侧表面与所述侧壁间隔件之间；凭借用所述衬层膜覆盖所述STI区和所述LDD区，通过使用所述栅极电极、形成在所述栅极电极的所述侧表面上的所述衬层膜和所述侧壁间隔件作为掩模来植入第二掺杂剂，以形成源极/漏极区；以及移除所述侧壁间隔件。

Description

具有用于有效应力转移的MOS晶体管的半导体装置
技术领域
本申请案涉及一种具有用于有效应力转移的MOS晶体管的半导体装置。
背景技术
将物理应力施加到沟道区以增加载流子迁移率的方法被公知为用于增加MOS晶体管的切换速率的方法。向沟道区施加物理应力的方法的实例包含用接触蚀刻停止衬层(CESL)覆盖MOS晶体管的方法和在源极/漏极区中嵌入外延层的方法。这些方法在相邻MOS晶体管的栅极电极之间的间隔足够宽的情况下是有效的。然而，当相邻MOS晶体管的栅极电极之间的距离较窄时，这些方法具有对沟道区施加较小的物理应力和载流子迁移率没有充分增加的问题。
发明内容
一方面，本申请案涉及一种设备，其包括：半导体衬底，其具有多个作用区，每个作用区由包括第一绝缘材料的STI区围绕；多个MOS晶体管，其形成在所述多个作用区中，所述多个MOS晶体管中的每一者包含源极/漏极区、在所述源极/漏极区之间的沟道区、以及覆盖所述沟道区的栅极电极，其中栅极绝缘膜插入在所述栅极电极与所述沟道区之间；衬层膜，其连续覆盖所述多个MOS晶体管中的每一者的所述栅极电极和所述源极/漏极区以及所述STI区，所述衬层膜包括不同于所述第一绝缘材料的第二绝缘材料；和拉伸/压缩膜，其覆盖所述衬层膜使得所述拉伸/压缩膜覆盖所述多个MOS晶体管中的每一者的所述源极/漏极区和所述STI区，其中所述衬层膜插入它们之间。
另一方面，本申请案涉及一种方法，其包括：在由STI区围绕的半导体衬底的作用区上形成栅极电极；通过使用所述栅极电极作为掩模来将第一掺杂剂植入到所述作用区中以形成LDD区；在所述栅极电极、所述STI区和所述LDD区的顶表面和侧表面上形成衬层膜；在所述栅极电极的所述侧表面上形成侧壁间隔件，其中所述衬层膜插入所述侧表面与所述侧壁间隔件之间；凭借覆盖所述STI区和所述LDD区的所述衬层膜，通过使用所述栅极电极、形成在所述栅极电极的所述侧表面上的所述衬层膜和所述侧壁间隔件作为掩模来植入第二掺杂剂，以形成源极/漏极区；以及移除所述侧壁间隔件。
另一方面，本申请案涉及一种方法，其包括：分别在半导体衬底的第一和第二作用区上形成第一和第二栅极电极；通过使用所述第一和第二栅极电极作为掩模来将第一掺杂剂植入到所述第一和第二作用区中以形成LDD区；在所述第一和第二栅极电极的至少侧表面上形成衬层膜；在所述第一和第二栅极电极的所述侧表面上形成第一侧壁间隔件，其中所述衬层膜插入所述侧表面与所述第一侧壁间隔件之间；移除所述第一栅极电极的所述侧表面上的所述第一侧壁间隔件，使得所述第二栅极电极的所述侧表面上的所述第一侧壁间隔件保留；在所述第一栅极电极的所述侧表面上形成第二侧壁间隔件，其中所述衬层膜插入所述侧表面与所述第二侧壁间隔件之间，且在所述第二栅极电极的所述侧表面上形成第二侧壁间隔件，其中所述衬层膜和所述第一侧壁间隔件插入所述侧表面与所述第二侧壁间隔件之间；通过使用所述第一和第二栅极电极、所述衬层膜、所述第一侧壁间隔件和所述第二侧壁间隔件作为掩模来植入第二掺杂剂以形成源极/漏极区；以及移除所述第一和第二侧壁间隔件。
附图说明
图1是根据本公开的半导体装置的框图；
图2是MOS晶体管的示意性平面图；
图3A是沿图2中所展示的线A-B的示意性横截面，并且展示构成外围装置的MOS晶体管的配置；
图3B是沿图2中所展示的线A-B的示意性横截面，并且展示构成间距装置的MOS晶体管的配置；
图4到9是用于解释根据本公开的半导体装置的制造工艺的工艺图，并且展示构成外围装置的MOS晶体管和构成间距装置的MOS晶体管所共用的制造工艺；
分别表示为“A”的图10到16是用于解释根据本公开的半导体装置的制造工艺的工艺图，并且展示构成外围装置的MOS晶体管的制造工艺；和
分别表示为“B”的图10到16是用于解释根据本公开的半导体装置的制造工艺的工艺图，并且展示构成间距装置的MOS晶体管的制造工艺。
具体实施方式
下文将参考附图详细地解释本发明的各种实施例。以下详细描述参考附图，所述附图通过说明的方式展示其中可实践本发明的特定方面及实施例。足够详细地描述这些实施例以使所属领域的技术人员能够实践本发明。可利用其它实施例，且可在不背离本发明的范围的情况下进行结构、逻辑及电改变。本文中所公开的各种实施例不一定是互斥的，因为一些所公开实施例可与一或多个其它所公开实施例组合以形成新实施例。
图1中所展示的半导体装置例如是DRAM(动态随机存取存储器)，并且包含含有多个存储器单元的存储器单元阵列1、连接到存储器单元阵列1的外围电路(间距装置)2、连接到外围电路(间距装置)2的外围电路(外围装置)3、以及连接到外围装置3的外部端子4。间距装置2是直接连接到存储器单元阵列1的电路，并且包含感测放大器、位线均衡器、列开关、子字驱动器、用于本地I/O线的上拉电路、用于感测放大器的激活电路等。外围装置3是包含在半导体装置中的其它外围电路，并且包含解码器、计数器、时钟控制电路、FIFO(先进先出)电路、输入/输出电路等。存储器单元阵列1中的存储器单元以最小间距布置。由于间距装置2是直接连接到存储器单元阵列1的电路，所以构成间距装置2的MOS晶体管也以与存储器单元的间距相同的间距布置。相反，构成外围装置3的MOS晶体管以比构成间距装置2的MOS晶体管的间距更大的间距布置。因此，构成间距装置2的MOS晶体管的间距小于构成外围装置3的MOS晶体管的间距。
如图2中所展示，包含在间距装置2和外围装置3中的每个MOS晶体管具有一对源极/漏极区50，以及在平面图中定位于源极/漏极区50之间的栅极电极30。虚设栅极电极30d分别放置在源极/漏极区50与栅极电极30相对的侧上。在图3A中展示构成外围装置3的MOS晶体管的结构，且在图3B中展示构成间距装置2的MOS晶体管的结构。如图3A和3B中所展示，包含在间距装置2和外围装置3中的每个MOS晶体管形成在包含半导体衬底的作用区10中。作用区10由STI(浅沟槽隔离)区20围绕。STI区20包含含有氧化硅的SOD膜21、氮化硅膜22和氧化硅膜23。在作用区10中提供LDD(轻掺杂漏极)区51和源极/漏极区52。LDD区51可具有包含HALO区的LDD/HALO结构。一对源极/漏极区52之间的区是沟道区53。用栅极绝缘膜31覆盖沟道区53。在栅极绝缘膜31上提供包含多晶硅膜32和钨膜33的栅极电极30。可在栅极绝缘膜31与多晶硅膜32之间提供金属栅极。用包含氮化硅的栅极盖34覆盖栅极电极30的顶部部分。用包含氮化硅的侧壁膜41覆盖栅极电极30和栅极盖34的侧表面。此外，用包含氮化硅的衬层膜42覆盖侧壁膜41和栅极盖34。衬层膜42不仅覆盖栅极电极30的侧表面和顶表面，而且连续地覆盖源极/漏极区52和STI区20。衬层膜42用包含氮化硅的拉伸/压缩膜43覆盖。拉伸/压缩膜43是用作CESL的膜，并且在通过向沟道区53施加物理应力来增加载流子迁移率时发挥作用。关于拉伸/压缩膜43是用作拉伸膜还是用作压缩膜，可根据膜形成条件来控制。
在包含在外围装置3中的每个MOS晶体管的LDD区51的长度为L1和包含在间距装置2中的每个MOS晶体管的LDD区51的长度为L2的情况下，L1>L2。这使得能够在间距装置2中实现高速切换，并且能够减小外围装置3中的洩漏电流。
接下来解释根据本实施例的半导体装置的制造方法。
首先，如图4中所展示，在半导体衬底5上形成沟槽6，并且用氧化硅膜23、氮化硅膜22和SOD膜21填充沟槽6的内部部分，从而形成STI区20。半导体衬底5上分别由STI区20围绕的区是作用区10。接下来，在每个作用区10上依序形成栅极绝缘膜31、多晶硅膜32、钨膜33和栅极盖34，并随后对其图案化以形成栅极电极30。栅极电极30的端部部分定位于STI区20上。可在栅极绝缘膜31与多晶硅膜32之间形成金属栅极。
接下来，如图5中所展示，在包含每个栅极电极30的侧表面和顶表面的整个表面上形成氮化硅膜41A之后，如图6中所展示，回蚀氮化硅膜41A以形成侧壁膜41。在此状态下离子植入掺杂剂61，以形成LDD区51。栅极电极30用作植入掩模以形成LDD区51。此时，可进一步形成HALO区以形成LDD/HALO结构。接下来，如图7中所展示，在整个表面上形成包含氮化硅的衬层膜42。因此，栅极电极30和栅极盖34的侧表面用衬层膜42覆盖，其中侧壁膜41插入所述侧表面与衬层膜42之间。作用区10和STI区20也用衬层膜42覆盖。衬层膜42的膜厚度为(例如)
Figure BDA0003487100370000041
接下来，如图8中所展示，在整个表面上形成氧化硅膜44。氧化硅膜44A的膜厚度为(例如)
Figure BDA0003487100370000042
接着，如图9中所展示，回蚀氧化硅膜44A，以形成侧壁膜44。因此，栅极电极30和栅极盖34的侧表面用侧壁膜44覆盖，其中侧壁膜41及衬层膜42插入所述侧表面与侧壁膜44之间。
接下来，如图10A和10B中所展示，用光掩模71覆盖外围装置3的整个表面。移除覆盖间距装置2的光掩模71。在此状态下执行侧壁膜44的蚀刻，从而如图11A和11B中所展示，选择性地移除定位于间距装置2上的侧壁膜44。定位于外围装置3上的侧壁膜44保持原样。接下来，如图12A和12B中所展示，在整个表面上形成氧化硅膜45A。氧化硅膜45A的膜厚度为(例如)
Figure BDA0003487100370000043
接着，如图13A和13B中所展示，回蚀氧化硅膜45A，以形成侧壁膜45。因此，外围装置3中的栅极电极30和栅极盖34的侧表面用侧壁膜44和45的两个层覆盖，其中侧壁膜41及衬层膜42插入所述侧表面与所述侧壁膜之间。相比之下，间距装置2中的栅极电极30和栅极盖34的侧表面用侧壁膜45的一个层覆盖，其中侧壁膜41及衬层膜42插入所述侧表面与侧壁膜45之间。在此状态下，通过衬层膜42离子植入掺杂剂62，从而形成源极/漏极区52。这使得外围装置3中的LDD区51的长度L1较长，而间距装置2中的LDD区51的长度L2较短。栅极电极30、衬层膜42、侧壁膜41、侧壁膜44和/或侧壁膜45用作植入掩模以形成源极/漏极区52。如上所描述，由于掺杂剂62在本实施例中是通过衬层膜42离子植入，所以衬层膜42的膜厚度被设置为足够薄。
接下来，如图14A和14B中所展示，通过使用氢氟酸的湿法蚀刻移除侧壁膜44和45。由于此时主要包含氧化硅的STI区20被衬层膜42覆盖，所以STI区20不被蚀刻。如图3A和3B中所展示，随后形成包含氮化硅的拉伸/压缩膜43，由此完成根据本实施例的MOS晶体管。这样，在本实施例中，在其中外围装置3中的栅极电极30的侧表面用侧壁膜44和45的两个层覆盖且间距装置2中的栅极电极30的侧表面用侧壁膜45的一个层覆盖的状态下，离子植入掺杂剂52。因此，外围装置3和间距装置2的LDD区51可形成为具有不同的长度。此外，在形成源极/漏极区52之后并且在形成拉伸/压缩膜43之前移除侧壁膜44和45。因此，相邻MOS晶体管之间的栅极电极间隔被加宽。这使得能够对沟道区施加足够的应力，因为拉伸/压缩膜43也在其中以高密度布置MOS晶体管的间距装置2中。
或者，可在移除侧壁膜44和45之后，如图15A和15B中所展示，回蚀衬层膜42，进一步回蚀源极/漏极区52以形成凹入区53A，且随后如图16A和16B中所展示，在凹入区53A中形成外延层53。同样在这种情况下，由于外延层53，应力可施加到沟道区。此外，由于在形成外延层53时侧壁膜44和45已经被移除，所以即使相邻MOS晶体管之间的栅极电极间隔较窄时，也可向凹入区53A供应外延生长所需的反应气体。
尽管已在某些优选实施例及实例的上下文中公开本发明，但所属领域的技术人员将理解，本发明延伸超出特定公开实施例到本发明的其它替代实施例及/或用途及其明显修改及等效物。另外，所属领域的技术人员将基于本公开容易地明白本发明范围内的其它修改。还预期，可对实施例的特定特征及方面进行各种组合或子组合，且其仍落入本发明的范围内。应理解，所公开实施例的各种特征及方面可彼此组合或替代以形成本发明的变化模式。因此，希望至少一些本发明的范围不应受上述特定公开实施例限制。

Claims (20)

1.一种设备，其包括：
半导体衬底，其具有多个作用区，每个作用区由包括第一绝缘材料的STI区围绕；多个MOS晶体管，其形成在所述多个作用区中，所述多个MOS晶体管中的每一者包含源极/漏极区、在所述源极/漏极区之间的沟道区、以及覆盖所述沟道区的栅极电极，其中栅极绝缘膜插入在所述栅极电极与所述沟道区之间；
衬层膜，其连续覆盖所述多个MOS晶体管中的每一者的所述栅极电极和所述源极/漏极区以及所述STI区，所述衬层膜包括不同于所述第一绝缘材料的第二绝缘材料；和
拉伸/压缩膜，其覆盖所述衬层膜使得所述拉伸/压缩膜覆盖所述多个MOS晶体管中的每一者的所述源极/漏极区和所述STI区，其中所述衬层膜插入它们之间。
2.根据权利要求1所述的设备，
其中所述衬层膜包含覆盖所述栅极电极的侧表面的侧壁区段，以及
其中所述拉伸/压缩膜包含覆盖所述衬层膜的所述侧壁区段的侧壁区段，而在它们之间并未插入有包括所述第一绝缘材料的绝缘膜。
3.根据权利要求1所述的设备，
其中所述多个作用区包含第一作用区及第二作用区，
其中所述多个MOS晶体管中的所述每一者进一步包含在所述源极/漏极区中的每一者与所述沟道区之间的LDD区，及
其中所述第一作用区中的所述多个MOS晶体管中的一者的所述LDD区的长度短于所述第二作用区中的所述多个MOS晶体管中的另一者的所述LDD区的长度。
4.根据权利要求3所述的设备，
其中所述多个MOS晶体管中的每一者形成在所述第一和第二作用区中的任一者中，以及
其中所述第一作用区中的所述多个MOS晶体管的所述栅极电极的间距小于所述第二作用区中的所述多个MOS晶体管的所述栅极电极的间距。
5.根据权利要求4所述的设备，其进一步包括存储器单元阵列，所述存储器单元阵列包含以预定间距布置的多个存储器单元，
其中所述第一作用区中的所述多个MOS晶体管的所述栅极电极的所述间距大体上与所述预定间距相同。
6.根据权利要求1所述的设备，其中所述第一绝缘材料包含氧化硅。
7.根据权利要求6所述的设备，其中所述第二绝缘材料包含氮化硅。
8.一种方法，其包括：
在由STI区围绕的半导体衬底的作用区上形成栅极电极；
通过使用所述栅极电极作为掩模来将第一掺杂剂植入到所述作用区中以形成LDD区；
在所述栅极电极、所述STI区和所述LDD区的顶表面和侧表面上形成衬层膜；
在所述栅极电极的所述侧表面上形成侧壁间隔件，其中所述衬层膜插入所述侧表面与所述侧壁间隔件之间；
凭借覆盖所述STI区和所述LDD区的所述衬层膜，通过使用所述栅极电极、形成在所述栅极电极的所述侧表面上的所述衬层膜和所述侧壁间隔件作为掩模来植入第二掺杂剂，以形成源极/漏极区；以及
移除所述侧壁间隔件。
9.根据权利要求8所述的方法，其进一步包括在移除所述侧壁间隔件之后在所述衬层膜上形成拉伸/压缩膜。
10.根据权利要求8所述的方法，其进一步包括：
在移除所述侧壁间隔件之后，移除所述源极/漏极区上的所述衬层膜；
回蚀所述源极/漏极区；和
在所述源极/漏极区上形成外延层。
11.根据权利要求8所述的方法，其中所述衬层膜包括与所述侧壁间隔件不同的绝缘材料。
12.根据权利要求11所述的方法，其中所述衬层膜包括氮化硅。
13.根据权利要求12所述的方法，其中所述侧壁间隔件包括氧化硅。
14.根据权利要求13所述的方法，其中所述STI区包括氧化硅。
15.一种方法，其包括：
分别在半导体衬底的第一和第二作用区上形成第一和第二栅极电极；
通过使用所述第一和第二栅极电极作为掩模来将第一掺杂剂植入到所述第一和第二作用区中以形成LDD区；
在所述第一和第二栅极电极的至少侧表面上形成衬层膜；
在所述第一和第二栅极电极的所述侧表面上形成第一侧壁间隔件，其中所述衬层膜插入所述侧表面与所述第一侧壁间隔件之间；
移除所述第一栅极电极的所述侧表面上的所述第一侧壁间隔件，使得所述第二栅极电极的所述侧表面上的所述第一侧壁间隔件保留；
在所述第一栅极电极的所述侧表面上形成第二侧壁间隔件，其中所述衬层膜插入所述侧表面与所述第二侧壁间隔件之间，且在所述第二栅极电极的所述侧表面上形成第二侧壁间隔件，其中所述衬层膜和所述第一侧壁间隔件插入所述侧表面与所述第二侧壁间隔件之间；
通过使用所述第一和第二栅极电极、所述衬层膜、所述第一侧壁间隔件和所述第二侧壁间隔件作为掩模来植入第二掺杂剂以形成源极/漏极区；以及
移除所述第一和第二侧壁间隔件。
16.根据权利要求15所述的方法，其进一步包括在所述移除所述第一和第二侧壁间隔件之后在所述衬层膜上形成拉伸/压缩膜。
17.根据权利要求15所述的方法，其进一步包括：
在所述移除所述第一和第二侧壁间隔件之后，移除所述源极/漏极区上的所述衬层膜；
回蚀所述源极/漏极区；和
在所述源极/漏极区上形成外延层。
18.根据权利要求15所述的方法，其中所述衬层膜包括与所述第一和第二侧壁间隔件不同的绝缘材料。
19.根据权利要求18所述的方法，其中所述衬层膜包括氮化硅。
20.根据权利要求19所述的方法，其中所述第一和第二侧壁间隔件包括氧化硅。
CN202210086447.XA 2021-01-27 2022-01-25 具有用于有效应力转移的mos晶体管的半导体装置 Pending CN114823667A (zh)

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US6277683B1 (en) * 2000-02-28 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer
US6582995B2 (en) * 2001-07-11 2003-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a shallow ion implanted microelectronic structure
US6670227B1 (en) * 2003-02-10 2003-12-30 Advanced Micro Devices, Inc. Method for fabricating devices in core and periphery semiconductor regions using dual spacers
US7855126B2 (en) * 2004-06-17 2010-12-21 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7078285B1 (en) * 2005-01-21 2006-07-18 Sony Corporation SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
JP2009088069A (ja) * 2007-09-28 2009-04-23 Panasonic Corp 半導体装置及びその製造方法
US7851313B1 (en) * 2007-11-09 2010-12-14 Xilinx, Inc. Semiconductor device and process for improved etch control of strained silicon alloy trenches
JP5147588B2 (ja) * 2008-08-04 2013-02-20 パナソニック株式会社 半導体装置
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