CN1147621C - 图形形成法 - Google Patents

图形形成法

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CN1147621C
CN1147621C CNB961082437A CN96108243A CN1147621C CN 1147621 C CN1147621 C CN 1147621C CN B961082437 A CNB961082437 A CN B961082437A CN 96108243 A CN96108243 A CN 96108243A CN 1147621 C CN1147621 C CN 1147621C
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photoresist
film disk
electroplated film
etching
photo
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CN1148637A (zh
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李相均
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Hanwha Aerospace Co Ltd
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Samsung Aerospace Industries Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/07Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process being removed electrolytically
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/44Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2203/01Tools for processing; Objects used during processing
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0323Working metal substrate or core, e.g. by etching, deforming
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0376Etching temporary metallic carrier substrate

Abstract

一种图形形成法包括下列工序:在基板上形成不溶于刻蚀溶液的金属电镀薄膜;在电镀薄膜上形成光致抗蚀薄膜;用预定的光掩模图形将光致抗蚀薄膜曝光然后显影,由此制取光致抗蚀图形;用光致抗蚀图形作为掩模制取电镀薄膜图形;完全清除光致抗蚀图形;用电镀薄膜图形作为刻蚀掩模刻蚀基片,然后完全清除电镀薄膜图形。本发明由于用电镀薄膜图形代替了光致抗蚀图形作为基片刻蚀工序中的刻蚀掩模,故可准确精密加工引线框架。

Description

图形形成法
技术领域
本发明涉及一种以刻蚀法形成图形的方法,更具体地说,涉及在用刻蚀法形成图形中用电镀薄膜图形作为蚀刻掩模以形成预定图形的一种方法。
背景技术
各种技术领域,例如在制造印刷电路板、阴极射线管的荫罩和叫做“引线框架”的半导体元件时,都采用刻蚀工艺。按惯例,这种加工方法是在需要把材料加工成复杂的图形时使用的。本专利申请通过介绍制造引线框架的一种方法来说明刻蚀形成图形的方法,作为在各种技术领域应用这种方法的一个例子。
引线框架是半导体器件的一个必不可少的部分,其作用是将半导体器件的电信号传送给外部电路,并作为独立部件以机械支撑半导体器件。通常,引线框架由底座、内引线和外引线构成,底座支撑着半导体芯片,内引线焊接到半导体芯片,外引线则用以将内引线与外部电路连接起来。用周知的刻蚀方法制造引线框架时,将光致抗蚀剂淀积在基片表面,用掩模曝光后进行显影,从而形成光致抗蚀图形。最后用刻蚀剂以光致抗蚀图形作为刻蚀掩模,通过刻蚀基片的经曝光的部分以形成引线框架。这时通常以恒定压力将刻蚀剂喷涂到引线框架基片的上下表同。
图1中的流程图示出了现有技术制造引线框架的方法,光致抗蚀剂(光敏聚合物树脂)涂敷到预处理过的金属基片上以便形成图形。通常,光致抗蚀剂按种类可分成液体光致抗蚀剂和干式光致抗蚀剂。前者是将水溶性树脂(例如酪素树脂或聚氯乙烯树脂)与光敏剂(例如重铬酸盐)按预定比例混合起来制成的。将这种液体光致抗蚀剂在基板上涂成大约5~10微米的厚度,然后进入光致抗蚀剂曝光工序,在光掩模安置在基片与光源之间的情况下,用光照射涂有光致抗蚀剂的表面。在曝光过程中,光致抗蚀剂曝过光的部分进入交联状态,未曝光的部分仍然处于未反应状态。
接着,在下一步的显影工序中,通常喷涂上显影液清除未曝光的部分。这样,交联部分形成光致抗蚀图形,由于溶解度不同而没有被清除掉。
显影工序之后,进行刻蚀操作,在高压下将刻蚀溶液喷涂到基片上。经显影的图形不溶于刻蚀溶液中,因而在刻蚀工艺形成图形的过程中起了刻蚀掩模的作用。
然而,现有技术蚀刻法制造引线框架的过程中有这样的一些问题。首先,要制造引线间距大的引线框架有困难。这是因为内引线间距减小的程度远比外引线间距减小的程度大得多,因而用上述刻蚀法制造引线框架需要非常精确的操作。若光致抗蚀剂在引线框架的金属基片上涂成5~10微米厚,则由于光致抗蚀剂的厚度比引线间距大,要进行如此精密的加工就难了。此外,光致抗蚀剂图形会因液体光致抗蚀剂抗刻蚀能力不足而损坏。这会使图形在刻蚀操作过程中刻蚀过头。此外高压喷涂蚀刻溶液时,由于光致抗蚀图形损坏而产生额外刻蚀图形。
发明内容
本发明的目的就是要解决上述问题,提供一种用电镀薄膜图形作为刻蚀掩模以形成图形的方法。
本发明的另一个目的是提供一种用电镀薄膜图形作为刻蚀掩模以刻蚀制造引线框架的方法。
为达到上述目的,本发明提供了一种用于制造引线框架的图形形成法,其特征在于,它包括下列工序:在基板上形成不溶于刻蚀溶液的金属电镀薄膜,所述基板是一个引线框架基片;在所述电镀薄膜上形成光致抗蚀薄膜;用预定的光掩模图形将所述光敏薄膜曝光然后显影,由此形成光致抗蚀图形;用所述光致抗蚀图形作为掩模制造电镀薄膜图形;清除光致抗蚀图形;用所述电镀薄膜图形作为刻蚀掩模刻蚀所述基片;然后,清除电镀薄膜图形;其中,所述引线框架基片用选自下列金属群的一种材料制成:铜、铁、镍和不锈钢合金,所述电镀薄膜则用选自下列金属群的一种金属制成:金、银和钯。
所述光敏薄膜是光致抗蚀剂,所述光致抗蚀图形形成工序是将光致抗蚀薄膜曝光。
所述光致抗蚀图形清除工序和电镀薄膜图形清除工序是分别将光致抗蚀图形和电镀薄膜图形完全清除掉。
所述电镀薄膜是用电解电镀法形成,所述电镀薄膜图形的形成和清除是通过加上方向与形成电镀薄膜工序中施加电流的方向相反的电流进行的。
所述电镀薄膜的厚度约为0.1~1微米。
参看附图详细说明本发明的一个最佳实施例可以更清楚地了解本发明的上述目的和优点。
附图说明
图1是现有技术制造引线框架方法的流程图;
图2是本发明制造引线框架方法的流程图;
图3A至图3F是本发明制造引线框架各工序的剖视图。
具体实施方式
在一个最佳实施例中,本发明的方法是从电镀工序开始的,即在预处理过的引线框架基片上覆盖上不溶于刻蚀溶液的电镀材料。电镀时最好采用金、银或钯,但也可以采用任何不溶于刻蚀溶液的电镀金属。具体地说,若引线框架基片采用铜、镍、不锈钢或铁合金,则考虑到成本和导电性能,电镀金属最好采用银。此外,电镀最好采用电解式而不要采用非电解式,使电镀金属从里面含有这种电镀金属的溶液中沉淀下来。这里,电镀薄膜的厚度约为0.1~1微米。
电镀工序之后,往电镀薄膜上涂上一层光敏材料,例如光致抗蚀剂。接着,按现有技术类似的方式形成光致抗蚀剂薄膜之后进行曝光和显影工序。曝光工序可采用可见光、紫外光或其它本技术领域周知的辐射光进行照射。
图3A至3F举例说明了最佳实施例的方法。图3B至3F中,充满斜线的阴影部分表示各清除掉的部分。
图3A和3B示出了在上面形成有电镀薄膜的基片上形成光致抗蚀剂薄膜图形的工序。这里,先有基片31的上下侧面上形成电镀薄膜32,再在电镀薄膜32上形成光致抗蚀薄膜33。用掩模(图中未示出)将光致抗蚀薄膜33曝光,然后显影,此此形成光致抗蚀图形33A。
图3C示出了形成电镀薄膜图形的工序。电镀薄膜图形32A是通过加上方向与电镀时施加电流的方向相反的电流采用光致抗蚀图形33A形成的。就是说,反向电流清除电镀薄膜覆有光致抗蚀图形33A的部分,但不清除电镀薄膜经曝光的部分。这样,电镀薄膜图形32A形成的图形和光致抗蚀图形33A的一样。
图3D说明清除光致抗蚀图形33A的工序。在电镀薄膜图形32A形成后,就清除光致抗蚀图形。现有技术清除抗蚀图形33A是采用氢氧化钠溶液进行的。光致抗蚀图形33A最好是完全清除,然后在引线框架基片上形成电镀薄膜图形32A的预定图形,大约0.1~1微米厚。
图3E示出了基片的刻蚀工序。引线框架基片是用电镀薄膜图形32A作为刻蚀掩模进行刻蚀的。由于电镀薄膜是上述不溶于刻蚀溶液的材料制成的,因而经曝光的引线框架基片不为电镀薄膜图形32A所覆盖的部分都受到刻蚀。于是基片31上就形成与光致抗蚀图形一模一样的预定图形。引线框架基片31一形成预定图形就将电镀薄膜图形32A清除掉。电镀薄膜图形32A最好通过上述那样通上反向电流完全清除掉。既然光致抗蚀图形33A已完全清除掉,就不难用反向电流将留在引线框架基片31上的电镀薄膜型板32A清除掉,于是如图3F所示形成了引线框架基片的预定图形。
电镀薄膜完全清除之后,可以再进行附加电镀。这个选择电镀工序,例如镀金,可以在引线框架的预定部分上进行,目的是使引线框架成品达到所要求的质量。
本发明的图形形成法和作为基应用实施例的引线框架制造方法具有这样的好处:由于基片刻蚀工序中用电镀薄膜图形代替现有技术的光致抗蚀图形作为蚀刻掩模,因而可以进行精确而精密的加工。具体地说,即使电镀薄膜0.1~1微米的厚度比现有技术光致抗蚀薄膜5~10微米的厚度小得多,电镀薄膜的硬度还是比光致抗蚀薄膜大。此外,由于电镀薄膜对刻蚀工序中高压喷涂上的刻蚀溶液的抵抗力强,因而既可以避免过刻蚀,又可以避免刻蚀不足,而且可以任意控制刻蚀溶液的喷涂压力。此外,无需进行电镀工艺中作为准备工序的要击工序,还可以明显减少基片诸如表面污染之类的低级品质。
上面已就附图中所示制造引线框架的具体实施例详细说明了本发明的线路图形形成法,但本技术领域的行家们都知道,在不脱离本发明在本说明书所附权利要求书的保护范围的前提下是可以对本发明基本原理的实施例进行种种修改和提出等效实施例的。

Claims (5)

1.一种用于制造引线框架的图形形成法,其特征在于包括下列工序:
在一个引线框架基片上形成不溶于刻蚀溶液的金属电镀薄膜;
在所述电镀薄膜上形成光致抗蚀薄膜;
用预定的光掩模图形将所述光敏薄膜曝光然后显影,由此形成光致抗蚀图形;
用所述光致抗蚀图形作为掩模制造电镀薄膜图形;
清除光致抗蚀图形;
用所述电镀薄膜图形作为刻蚀掩模刻蚀所述基片;然后
清除电镀薄膜图形;
其中,所述引线框架基片用选自下列金属群的一种材料制成:铜、铁、镍和不锈钢合金,所述电镀薄膜则用选自下列金属群的一种金属制成:金、银和钯。
2.如权利要求1所述的方法,其特征在于,所述光敏薄膜是光致抗蚀剂,所述光致抗蚀图形形成工序是将光致抗蚀薄膜曝光。
3.如权利要求1所述的方法,其特征在于,所述光致抗蚀图形清除工序和电镀薄膜图形清除工序是分别将光致抗蚀图形和电镀薄膜图形完全清除掉。
4.如权利要求1所述的方法,其特征在于,所述电镀薄膜是用电解电镀法形成,所述电镀薄膜图形的形成和清除是通过加上方向与形成电镀薄膜工序中施加电流的方向相反的电流进行的。
5.如权利要求1所述的方法,其特征在于,所述电镀薄膜的厚度约为0.1~1微米。
CNB961082437A 1995-07-18 1996-07-18 图形形成法 Expired - Fee Related CN1147621C (zh)

Applications Claiming Priority (3)

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KR21105/1995 1995-07-18
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KR100227520B1 (ko) * 1997-03-12 1999-11-01 강진수 턴스타일 애드슬리브의 커버
JP2000040679A (ja) * 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法
CN1081246C (zh) * 1999-07-29 2002-03-20 上海交通大学 镍钛合金薄膜多元化学刻蚀剂
DE10129670A1 (de) * 2001-06-20 2003-01-09 Bosch Gmbh Robert Verfahren zur Herstellung einer Materialbibliothek
US6699356B2 (en) 2001-08-17 2004-03-02 Applied Materials, Inc. Method and apparatus for chemical-mechanical jet etching of semiconductor structures
KR100819797B1 (ko) * 2002-05-02 2008-04-07 삼성테크윈 주식회사 리이드 프레임의 제조 방법 및, 그에 의해서 제조된리이드 프레임
WO2005015308A2 (en) * 2003-08-08 2005-02-17 Quantiscript Inc. Fabrication process for high resolution lithography masks using evaporated or plasma assisted electron sensitive resists with plating image reversal
JP2006229147A (ja) * 2005-02-21 2006-08-31 Toshiba Corp 半導体装置のレイアウト最適化方法、フォトマスクの製造方法、半導体装置の製造方法およびプログラム
US7960819B2 (en) * 2006-07-13 2011-06-14 Cree, Inc. Leadframe-based packages for solid state emitting devices
US8044418B2 (en) 2006-07-13 2011-10-25 Cree, Inc. Leadframe-based packages for solid state light emitting devices
US7973394B2 (en) * 2009-06-10 2011-07-05 Blondwich Limited Enhanced integrated circuit package
KR101494702B1 (ko) * 2014-10-22 2015-02-26 (주)메가메디칼 네블라이저용 메쉬 제조방법

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KR970008379A (ko) 1997-02-24
TW418345B (en) 2001-01-11
DE19628264A1 (de) 1997-01-23
CN1148637A (zh) 1997-04-30
KR0165413B1 (ko) 1999-02-01
US5770096A (en) 1998-06-23

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