CN114664741A - 集成电路及其制造方法 - Google Patents

集成电路及其制造方法 Download PDF

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CN114664741A
CN114664741A CN202210367963.XA CN202210367963A CN114664741A CN 114664741 A CN114664741 A CN 114664741A CN 202210367963 A CN202210367963 A CN 202210367963A CN 114664741 A CN114664741 A CN 114664741A
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epitaxial
well
high voltage
type
crystal plane
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陈奕寰
郑光茗
周建志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种具有外延源极与漏极的集成电路被提供，其可降低栅极烧毁并提高开关速度，因而适合于高电压的应用。此集成电路包括具有高电压N型阱高电压P型阱的半导体基板。此集成电路亦包括高电压装置位于该半导体基板之上。此高电压装置包括外延P型源极设置于高电压N型阱中，外延P型漏极设置于高电压P型阱中，以及栅极位于半导体基板的表面上的外延P型源极与外延P型漏极之间。

Description

集成电路及其制造方法
本申请为分案申请，其母案申请的申请号为201711216693.8，申请日为2017年11月28日，发明名称为“集成电路及其制造方法”。
技术领域
本公开涉及一种半导体装置，且特别涉及一种具有外延源极与漏极的集成电路及其制造方法。
背景技术
现代集成晶片使用广泛的装置以实现不同的功能。一般而言，集成晶片包括主动装置和被动装置。主动装置包括晶体管，例如，金属氧化物半导体场效晶体管(MOSFETs)。基于金属氧化物半导体场效晶体管装置的开关速度，金属氧化物半导体场效晶体管装置使用于车辆电子系统、电源供应及电源管理应用中。开关速度至少部分地基于金属氧化物半导体场效晶体管装置的RDS(on)。RDS(on)代表“漏极-源极导通电阻”，或是当金属氧化物半导体场效晶体管为“导通”时，金属氧化物半导体场效晶体管中漏极和源极之间的总电阻。RDS(on)与电流损耗相关，并且是金属氧化物半导体场效晶体管最大电流额定值的基础。
发明内容
本公开的一实施例是提供一种集成电路，包括：半导体基板，具有高电压N型阱与高电压P型阱；高电压装置位于半导体基板之上，其中高电压装置包括外延P型源极设置于高电压N型阱中，外延P型漏极设置于高电压P型阱中，以及栅极位于半导体基板的表面上的外延P型源极与外延P型漏极之间。
本公开的另一实施例是提供一种集成电路，包括：半导体基板，具有高电压P型阱与高电压N型阱；高电压装置位于半导体基板之上，其中高电压装置包括外延N型源极设置于高电压P型阱中，外延N型漏极设置于高电压N型阱中，以及栅极位于半导体基板的表面上的高电压P型阱与高电压N型阱之间。
本公开的又一实施例是提供一种集成电路的制造方法，包括：形成多层栅极层于基板之上，其中基板具有高电压N型阱与高电压P型阱；图案化上述栅极层，以形成具有栅极介电质与栅极电极的栅极；形成多个侧壁间隙壁于栅极介电质与栅极电极的每一个侧壁上；选择性沉积多个硬掩模层于基板与栅极之上；进行斜角蚀刻，以形成多边源极凹孔于高电压N型阱之中，且形成多边漏极凹孔于高电压P型阱之中，其中多边源极凹孔与多边漏极凹孔具有实质上平面的多个边缘，且上述边缘在多个角落相连接；形成外延P型源极于多边源极凹孔之中，且形成外延P型漏极于多边漏极凹孔之中，其中外延P型源极与外延P型漏极具有多边形形状；以及移除上述硬掩模层。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是，根据本产业的一般作业，图示并未必按照比例绘制。事实上，可能任意的放大或缩小元件的尺寸，以做清楚的说明。
图1A为根据一些实施例绘示一具有外延源极与漏极的P型金属氧化物半导体(PMOS)的剖面图。
图1B为图1A所绘示的外延源极与漏极的局部放大剖面图。
图2为根据一些实施例绘示一具有外延源极与漏极的N型金属氧化物半导体(NMOS)的剖面图。
图3为根据一些实施例绘示一具有用于高电压装置的外延源极与漏极的集成电路(IC)的剖面图。
图4～图13为根据一些实施例绘示一具有外延源极与漏极的集成电路的制造方法的一系列剖面图。
图14为根据图4～图13的实施例的制造方法的流程图。
附图标记说明：
100～P型金属氧化物半导体晶体管
102～基板
104a～第一N阱区域
104b～第二N阱区域
106～P阱区域
108～隔离P阱
110a～第一N+掺杂区域
110b～第二N+掺杂区域
112a～第一隔离结构
112b～第二隔离结构
112c～第三隔离结构
114～外延P型源极
116～外延P型漏极
118～P型轻掺杂扩散区域
120～栅极
122～栅极电极
124～栅极介电质
126～侧壁间隔物
150～底部晶面
152～顶部晶面
154～第一侧
156～第二侧
158～第一上部晶面
160～第一下部晶面
162～第一点
164～第二上部晶面
166～第二下部晶面
168～第二点
200～N型金属氧化物半导体晶体管
202～基板
204a～第一P阱区域
204b～第二P阱区域
206～N阱区域
208～隔离N阱
210a～第一P+掺杂区域
210b～第二P+掺杂区域
212a～第一隔离结构
212b～第二隔离结构
212c～第三隔离结构
214～外延N型源极
216～外延N型漏极
218～N型轻掺杂扩散区域
220～栅极
222～栅极介电质
224～栅极电极
226～侧壁间隔物
300～集成电路
302～半导体基板
304～P型金属氧化物半导体装置
306～N型金属氧化物半导体装置
308～P型金属氧化物半导体阱区域
308a～第一P型金属氧化物半导体阱区域
308b～第二P型金属氧化物半导体阱区域
310s～外延源极
310d～外延漏极
312～沟道区域
314～栅极结构
316～栅极电极
318～栅极介电质
320a、320b～隔离区域
322～N型金属氧化物半导体阱区域
322a～第一N型金属氧化物半导体阱区域
322b～第二N型金属氧化物半导体阱区域
324s～外延源极
324d～外延漏极
326～沟道区域
328～栅极结构
330～栅极电极
332～栅极介电质
334～层间介电质结构
336～第一组内连线层
336a～接触
336b～金属线层
336c～金属介层窗层
338～第二组内连线层
338a～接触
338b～金属线层
338c～金属介层窗层
340～覆盖结构
342～第一钝化层
344～第二钝化层
346～第一接合垫
348～第二接合垫
400、500、600、700、800、900、1000、1100、1200、1300～剖面图
502～栅极层
504～栅极介电质层
506～栅极电极层
508～栅极掩模
602～第一图案化
802～斜角注入
1002、1004、1006～硬掩模层
1102～第二图案化
1104～多边源极凹孔
1106～多边漏极凹孔
1400～流程图
1402、1404、1406、1408、1410、1412、1414、1416、1418、1420～步骤
d1、d2～距离
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本案的不同特征。以下的公开内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本公开书叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。另外，以下公开书不同范例可能重复使用相同的参照符号及/或标记。这些重复是为了简化与清晰的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
此外，其与空间相关用词。例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，是为了便于描述图示中一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中绘示的方位外，这些空间相关用词意欲包含使用中或操作中的装置的不同方位。装置可能被转向不同方位(旋转90度或其他方位)，则在此使用的空间相关词也可依此相同解释。
高电压装置由于其较高的开关速度而被广泛应用于电源管理、电信等领域。然而，一些不预发生的效应，例如，高RDS(on)，在切换期间会导致开关速度降低与较多的能量损失。需要较低的RDS(on)，以避免电流损耗，并达到适合于相关设备的较高的最大电流额定值。例如，因为高电压装置需要较高的最大电流额定值，所以需要较低的RDS(on)。
装置，例如，高电压装置，可包括晶体管，此晶体管具有由栅极所分隔的源极与漏极。源极与漏极通常通过在基板中注入杂质而形成。然而，注入工艺可能会损坏位于源极与漏极的基板表面。基板中的缺陷可能会对操作产生负面影响，例如，提高RDS(on)。在此，不是在基板中注入杂质以形成源极与漏极，而是外延成长源极与漏极。由于成长源极与漏极，源极与漏极的表面不会产生因离子注入而引起的缺陷。因此，此处描述一种用于高电压装置的外延源极与漏极，以减少RDS(on)。此外，源极与漏极的掺杂密度可以通过外延成长而增加，如此也会降低RDS(on)。
请参照图1A，其是绘示一具有外延P型源极与漏极的P型金属氧化物半导体(PMOS)晶体管100的一些实施例的剖面图。P型金属氧化物半导体晶体管100包括半导体基板102。基板102具有N阱区域，N阱区域包括第一N阱区域104a及第二N阱区域104b。在一些实施例中，N阱区域104a、104b是高电压N型阱(high-voltage N-well,HVNW)。N阱区域104a、104b具有N型掺质，并且可具有介于约1015～1017掺质/cm3之间的掺杂浓度。基板102亦包括P阱区域106。在一些实施例中，P阱区域106是高电压P型阱(high-voltage P-well,HVPW)。P阱区域106设置在第一N阱区域104a与第二N阱区域104b之间。P阱区域106具有P型掺质，并且可具有介于约1015～1017掺质/cm3之间的掺杂浓度。
注入隔离P阱(isolated P-well)108于第一N阱区域104a中。在一些实施例中，隔离P阱108具有P型掺质，并且可具有介于约1016～1018掺质/cm3之间的掺杂浓度。隔离P阱108从基板102的最上方表面延伸到第一N阱区域104a。
N阱区域104a、104b亦包括N+掺杂区域110a、110b。举例而言，在第一N阱区域104a中注入第一N+掺杂区域110a，并且在第二N阱区域104b中注入第二N+掺杂区域110b。N+掺杂区域110a、110b的功能在于作为与N阱区域104a、104b的主体接触(body contact)。N+掺杂区域110a、110b可掺杂比N阱区域104a、104b更高浓度的N型掺质(例如，硼)，使N+掺杂区域作为与N阱区域104a、104b的接触。
隔离结构112a、112b、112c定义出各种主动特征的区域并将它们彼此隔离。隔离结构112a、112b、112c可包括第一隔离结构112a、第二隔离结构112b及第三隔离结构112c。举例而言，隔离结构112a、112b、112c可以是，例如，浅沟槽隔离结构、深沟槽隔离结构或一些其它类型的隔离结构，并且，例如，可以填充介电材料，例如二氧化硅。
外延P型源极114设置在第一N阱区域104a中，且外延P型漏极116设置在P阱区域106中。外延P型源极114及外延P型漏极116成长为外延层。外延P型源极114及外延P型漏极116成长为外延层具有多边形形状。在一些实施例中，多边形形状是六边形，如图1B所示。
请转而参照图1B，其绘示多边形的外延P型源极114嵌埋于第一N阱区域104a中。外延P型源极114具有六个实质上平面的晶面(facet)，包括底晶面150、顶晶面152、具有两个斜角晶面(angled facet)的第一侧154及具有两个斜角晶面的第二侧156。第一侧154具有从顶部晶面152延伸到隔离P阱108之中的第一上部晶面158。第一侧154亦具有从底部晶面150朝向第一上部晶面158延伸的第一下部晶面160。第一上部晶面158与第一下部晶面160在第一点162相交，第一点162位于第一N阱区域104a的最上方表面104a’下方一段距离d1。由于基板102包括N阱区域104，所以第一N阱区域104a的最上方表面104a’是基板102的最上方表面。
第二侧156具有从顶部晶面152延伸到第一N阱区域104a的第二上部晶面164。第二侧156亦具有从底部晶面150朝向第二上部晶面164延伸的第二下部晶面166。第二上部晶面164和第二下部晶面166在第二点168相交，第二点168位于第一N阱区域104a的最上方表面104a’下方一段距离d1。因此，外延P型源极114可嵌埋于第一N阱区域104a中，使第一点162和第二点168位于最上方表面104a’下方一段距离d1。在一些实施例中，第一点162可位于栅极介电质124或侧壁间隔物126的一个侧壁间隔物下方。
外延P型源极114的一部分延伸于第一N阱区域104a的最上方表面104a’上方一段距离d2。延伸于最上方表面104a’上方的外延P型源极114的量可基于外延成长工艺而定。距离d2可大于距离d1。在一些实施例中，距离d2可大于基板102上的其它特征的高度。例如，距离d2可大于栅极120的高度。由于外延P型源极114的外延成长，因而晶面150、152、158、160、164及166实质上是平滑的。
图1B绘示外延P型源极114、外延P型漏极116即使不是相同的尺寸，也可具有相似的尺寸。举例而言，外延P型漏极116也可在侧面具有斜角晶面，其延伸而在P阱区域106的最上方表面下方的点的位置相交。此外，可基于多边形的拉伸强度，而选择用于外延P型源极114及/或外延P型漏极116的多边形形状，然而，也可使用其它形状。
请参照回1A图，在一些实施例中，外延P型源极114及外延P型漏极116可为包括晶体结构的硅或锗的P型元素半导体。在其它实施例中，外延P型源极114及外延P型漏极116包括P型合金，例如，硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、磷砷化铟镓(GaInAsP)、或锗组成从在一个位置的一比例变化为在另一个位置的另一比例。外延P型源极114及外延P型漏极116的掺杂浓度范围介于约1020～1021杂质/cm3之间。
P型轻掺杂扩散(P-type lightly doped diffusion,PLDD)区域118设置在第一N阱区域104a中并且与栅极120的边缘对准，并且位于间隔物126下方。栅极120形成于基板102的最上方表面，并且在水平方向上插入在外延P型源极114与外延P型漏极116之间。栅极120可延伸于第二隔离结构112b上，第二隔离结构112b位于外延P型源极114与外延P型漏极116之间。栅极120包括栅极电极122、栅极介电质124及侧壁间隔物126，侧壁间隔物126邻接栅极电极122及栅极介电质124的侧壁。
外延P型源极114、外延P型漏极116及栅极120共同形成P型金属氧化物半导体晶体管100。因为外延P型源极114及外延p型漏极116成长，所以外延P型源极114及外延P型漏极116不会产生通过离子注入形成源极与漏极时通常会发生的缺陷。此外，外延成长可为外延P型源极114和外延P型漏极116提供更高的掺杂浓度。这些优点具有降低P型金属氧化物半导体晶体管100的RDS(on)的作用。较低的RDS(on)有利于促进P型金属氧化物半导体晶体管100中的电流流动，因此，可降低栅极烧毁(burnout)并提高开关速度，而适合于高电压的应用。
请参照图2，其是绘示一具有外延N型源极与漏极的N型金属氧化物半导体(NMOS)晶体管200的一些实施例的剖面图。N型金属氧化物半导体晶体管200包括基板202。基板102具有P阱区域，P阱区域包括第一P阱区域204a及第二P阱区域204b。在一些实施例中，P阱区域204a、204b是高电压P型阱(high-voltage P-well,HVPW)，如同以上图1A所述的P阱区域106。基板202亦包括N阱区域206。N阱区域206设置在第一P阱区域204a与第二P阱区域204b之间。在一些实施例中，N阱区域206是高电压N型阱(high-voltage N-well,HVNW)，如同以上图1A所述的N阱区域104a、104b。
注入隔离N阱(isolated N-well)208于第一P阱区域204a中。在一些实施例中，隔离N阱208具有N型掺质，并且可具有介于约1016～1018掺质/cm3之间的掺杂浓度。P阱区域204a、204b亦分别包括P+掺杂区域210a、210b。举例而言，在第一P阱区域204a中注入第一P+掺杂区域210a，并且在第二P阱区域204b中注入第二P+掺杂区域210b。P+掺杂区域210a、210b的功能在于作为与P阱区域204的主体接触。
隔离结构212a、212b、212c可包括第一隔离结构212a、第二隔离结构212b及第三隔离结构212c。举例而言，隔离结构212a、212b、212c可以是，例如，浅沟槽隔离结构、深沟槽隔离结构或一些其它类型的隔离结构。隔离结构212a、212b、212c从基板202的顶部表面延伸，如同以上图1A所述。
外延N型源极214设置在第一P阱区域204a中，且外延N型漏极216设置在N阱区域206中。外延N型源极214及外延N型漏极216成长为具有N型材料的外延层，如同以上所述。举例而言，在此，外延N型源极214及外延N型漏极216包括N型元素半导体，N型元素半导体包括硅或磷，例如，磷化硅(SiP)。此外，即使不是相同的多边形形状，外延N型源极214及外延N型漏极216也可具有相似的多边形形状，如同以上图1B所述。
N型轻掺杂扩散(N-type lightly doped diffusion,NLDD)区域218设置在第一P阱区域204a中并且与栅极220的边缘对准。栅极220形成于基板202的最上方表面，并且在水平方向上插入在外延N型源极214与外延N型漏极216之间。栅极220包括栅极介电质222、栅极电极224及侧壁间隔物226，侧壁间隔物226邻接栅极介电质222及栅极电极224的侧壁。外延N型源极214、外延N型漏极216及栅极220共同形成N型金属氧化物半导体晶体管200。如同上述的P型金属氧化物半导体晶体管100，N型金属氧化物半导体晶体管200提供较低的RDS(on)。
请参照图3，其是绘示一具有用于高电压装置的外延源极与漏极的集成电路(IC)的一些实施例的剖面图。集成电路300包括设置于半导体基板302之上的P型金属氧化物半导体装置304及N型金属氧化物半导体装置306。P型金属氧化物半导体装置304包括P型金属氧化物半导体阱区域308设置于半导体基板302之中。P型金属氧化物半导体阱区域308包括第一P型金属氧化物半导体阱区域308a及第二P型金属氧化物半导体阱区域308b。第一P型金属氧化物半导体阱区域308a具有第一掺杂类型，第二P型金属氧化物半导体阱区域308b具有第二掺杂类型，且第二掺杂类型不同于第一掺杂类型。举例而言，当第二P型金属氧化物半导体阱区域308b为高电压P型阱，第一P型金属氧化物半导体阱区域308a可为高电压N型阱。P型金属氧化物半导体晶体管设置于P型金属氧化物半导体阱区域308之中。P型金属氧化物半导体晶体管包括外延源极310s，外延源极310s通过沟道区域312而与外延漏极310d隔开。栅极结构314设置于沟道区域312之上。栅极结构314包括栅极电极316，栅极电极316通过栅极介电质318而与沟道区域312隔开。在一些实施例中，隔离区域320a(例如，浅沟槽隔离区域)设置于半导体基板302之中，且位于外延源极310s与外延漏极310d之间。
N型金属氧化物半导体装置306包括N型金属氧化物半导体阱区域322设置于半导体基板302之中。N型金属氧化物半导体阱区域322包括第一N型金属氧化物半导体阱区域322a及第二N型金属氧化物半导体阱区域322b。第一N型金属氧化物半导体阱区域322a具有第一掺杂类型，第二N型金属氧化物半导体阱区域3具有第二掺杂类型，且第二掺杂类型不同于第一掺杂类型。举例而言，当第二N型金属氧化物半导体阱区域322b为高电压N型阱，第一N型金属氧化物半导体阱区域322a可为高电压P型阱。N型金属氧化物半导体晶体管设置于N型金属氧化物半导体阱区域322之中。N型金属氧化物半导体晶体管包括外延源极324s，外延源极324s通过沟道区域326而与外延漏极324d隔开。栅极结构328设置于沟道区域326之上。栅极结构328包括栅极电极330，栅极电极330通过栅极介电质332而与沟道区域326隔开。在一些实施例中，隔离区域320b(例如，浅沟槽隔离区域)设置于半导体基板302之中，且位于外延源极324s与外延漏极324d之间。
层间介电质(inter-layer dielectric,ILD)结构334设置于半导体基板302之上。在一些实施例中，层间介电质结构334可包括氧化物、低介电常数(low-k)介电质或超低介电常数(ultra-low-k)介电质。第一组内连线层336包括接触336a、金属线层336b及金属介层窗层336c，其受到层间介电质结构334包围，并且覆盖P型金属氧化物半导体装置304。第二组内连线层338包括接触338a、金属线层338b及金属介层窗层338c，其受到层间介电质结构334包围，并且覆盖N型金属氧化物半导体装置306。在一些实施例中，第一组内连线层336及第二组内连线层338可包括铜、钨及/或铝。层间介电质结构334受到覆盖结构340所覆盖。覆盖结构340可包括多个钝化层，例如，第一钝化层342及第二钝化层344。第一钝化层342及第二钝化层344可包括以下材料：第一钝化层342和第二钝化层344可以包括作为氧化物或氮化物(例如，氧化硅、氮化硅)、未掺杂的硅酸盐玻璃及/或上述的多层结构。接合垫，其包括第一接合垫346及第二接合垫348，被设置在覆盖结构340中。第一接合垫346及第二接合垫348由导电材料所制成，例如，铜。在一些实施例中，第一接合垫346通过第一组内连线层336连接到P型金属氧化物半导体装置304，且第二接合垫348通过第二组内连线层338连接到N型金属氧化物半导体装置306。
请参照图4～图13，其是一系列剖面图400～1300，用以绘示一具有外延源极与外延漏极的集成电路的制造方法的一些实施例，其是用于P型金属氧化物半导体晶体管，例如，图1A的P型金属氧化物半导体晶体管。
如图4的剖面图400所绘示，提供基板102。基板102可由半导体材料所形成。在一些实施例中，基板102为块材(bulk)单晶硅基板。在另一些实施例中，基板102为绝缘体上覆半导体(SOI)基板，包括承载基板，位于承载基板上的绝缘层，以及位于绝缘层上的装置层，其中装置层由半导体材料所形成。隔离结构112a、112b、112c形成于基板之中，且延伸进入基板102的顶部表面中。基板102可具有介于约1.5～4μm的厚度。举例而言，基板102可为约2.5μm厚。隔离结构112a、112b、112c可从基板102的顶部表面延伸到深度为，例如，约1μm。隔离结构112a、112b、112c划分基板102的装置区域，例如，逻辑区域或高电压装置区域。在一些实施例中，用以形成隔离结构112a、112b、112c的工艺包括：形成沟槽，以及随后使用介电质材料填充这些沟槽。
使用掺质注入基板，以形成N阱区域104a、104b及P阱区域106。如上所述，N阱区域104a、104b具有N型掺质，并且可具有介于约1015～1017掺质/cm3之间的掺杂浓度，P阱区域106具有P型掺质，并且可具有介于约1015～1017掺质/cm3之间的掺杂浓度。N阱区域104a、104b可具有介于约2～5μm的厚度。
如图5的剖面图500所绘示，多个栅极层502形成于基板102上。在一些实施例中，栅极层502包括栅极介电质层504及栅极电极层506。在一些实施例中，栅极介电质层504，例如，可包括高介电常数(high-k)介电质，且栅极电极层506可包括多晶硅。虽然栅极介电质层504与栅极电极层506被绘示为单层，然而，其每一层可分别由多层所形成。栅极掩模508选择性地沉积于上述多个栅极层502上。特别是，栅极掩模508被形成并图案化，以位于第一隔离结构112a和第二隔离结构112b之间。在一些实施例中，栅极掩模508为光致抗蚀剂层。
如图6的剖面图600所绘示，使用栅极掩模(图5的508)将多个栅极层502在适当的位置图案化。举例而言，可利用光刻(photolithography)工艺将上述多个栅极层(图5的502)图案化，以实施第一图案化602。或者，可通过将上述多个栅极层(图5的502)暴露于蚀刻剂中，以实施第一图案化602。在另一实施例中，可利用蚀刻剂蚀刻上述多个栅极层(图5的502)，以实施第一图案化602。蚀刻剂可包括具有蚀刻化学性质的包括氟物质的干式蚀刻剂(例如，四氟甲烷、三氟甲烷、八氟环丁烷等)，或是包括氢氟酸(HF)的湿式蚀刻剂。之后，将栅极掩模(图5的508)剥除，以形成栅极电极122与栅极介电质124。
如图7的剖面图700所绘示，侧壁间隔物126沿着栅极电极122及栅极介电质124的侧壁而形成，以形成栅极120。侧壁间隔物126可为，例如，氧化物或其他介电质，例如，氮化硅。在一些实施例中，用以形成侧壁间隔物126的工艺包括：形成侧壁间隔物层分别顺应性地覆盖于且衬垫于栅极电极122及栅极介电质124。侧壁间隔物层可通过，例如，高温氧化(high temperature oxidation,HTO)之后进行快速热退火(rapid thermal annealing,RTA)而形成。此外，在一些实施例中，上述工艺包括对侧壁间隔物层实施回蚀刻(etchback)，以移除侧壁间隔物层的水平部分，而不移除侧壁间隔物层的垂直部分。在回蚀刻之后，上述垂直部分仍留在对应于侧壁间隔物126的适当的位置。
如图8的剖面图800所绘示，实施斜角注入802，以形成P型轻掺杂扩散区域118于栅极120下方且位于第一N阱区域104a中。斜角注入802具有不同于第一N阱区域104a的导电类型(例如，P+)。在一些实施例中，斜角注入802可注入于基板的包括104a、104b及106暴露的表面区域中(未绘示)，然而，也可通过场氧化物(field oxide)或其他阻挡结构(未绘示)阻挡斜角注入802，且因此只有P型轻掺杂扩散区域118被绘示。
如图9的剖面图900所绘示，使用P阱掩模(未绘示)在适当的位置实施正常的P型离子注入操作，以形成隔离P阱108(所谓「正常」，意指垂直于基板102的表面)。使用N阱掩模(未绘示)在适当的位置实施正常的N型离子注入操作，以在第一N阱区域104a中形成第一N+掺杂区域110a，且同时在第二N阱区域104b中形成第二N+掺杂区域110b。隔离P阱108可具有介于约0.5～2μm的厚度。在另一实施例中，隔离P阱108的厚度可介于约1～1.5μm。
如图10的剖面图1000所绘示，沉积硬掩模层1002～1006。硬掩模层1002及1006选择性地沉积于基板102上，且硬掩模层1004选择性地沉积于栅极120上。硬掩模层1002～1006可由氮化硅(Si3N4)所形成。
如图11的剖面图1100所绘示，通过第二图案化1202蚀刻基板102的最上方表面，以形成多边源极凹孔(multi-edged source cavity)1104与多边漏极凹孔(multi-edgeddrain cavity)1106。在一些实施例中，第二图案化1202为斜角蚀刻，其可允许凹孔沿着一斜角延伸于基板102中。多边源极凹孔1104与多边漏极凹孔1106具有多个实质上平面的边缘，且这些边缘在角落相连接。第二图案化1202的蚀刻剂可包括具有蚀刻化学性质的干式蚀刻剂，例如，氟物质(例如，四氟甲烷、三氟甲烷、八氟环丁烷等)，或是湿式蚀刻剂，例如，氢氟酸。
如图12的剖面图1200所绘示，通过外延成长工艺形成外延P型源极114及外延P型漏极116。外延P型源极114形成于多边源极凹孔中(图11的1104)，且外延P型漏极116形成于多边漏极凹孔中(图11的1106)。外延P型源极114及外延P型漏极116通过外延技术成长。假设外延P型源极114是硅锗(SiGe)。可在化学气相沉积(CVD)反应器、低压化学气相沉积(LPCVD)反应器或超高真空化学气相沉积(ultra-high vacuum CVD,UHVCVD)中进行，反应器温度可介于600～800℃之间，反应器压力可介于1～760Torr之间。载送气体可由氢或氦形成，流速介于10～50SLM之间。
可使用硅源前驱物气体进行沉积，例如，二氯硅烷(DCS或SiH2Cl2)、硅烷(SiH4)或乙硅烷(Si2H6)。举例而言，可在流速介于15～100SCCM的条件下使用二氯硅烷。沉积也可使用锗源前驱物气体，例如，四氢化锗(GeH4)稀释于氢气中(例如，四氢化锗可被稀释为1～5％)。举例而言，可在浓度为1％且流速介于50～300SCCM的条件下使用稀释的四氢化锗。据此，可成长外延P型源极114。
在此，此一制造具有外延源极与漏极的集成电路的方法是针对P型金属氧化物半导体晶体管而描述，例如，图1A的P型金属氧化物半导体晶体管。据此，外延P型漏极116可以也是硅锗。因此，外延P型漏极116可通过相似的工艺而成长。然而，此一制造具有外延源极与漏极的集成电路的方法也可使用于N型金属氧化物半导体晶体管，例如，图2的N型金属氧化物半导体晶体管。外延N型源极214及外延N型漏极216可由磷化硅(SiP)所形成。举例而言，不使用锗源前驱物气体，而可使用磷源前驱物气体形成外延N型源极214及外延N型漏极216。外延成长工艺可使外延P型源极114汲外延P型漏极116成长高于基板102的最上方表面。
如图13的剖面图1300所绘示，在成长外延P型源极114及外延P型漏极116之后，从基板102及栅极120移除硬掩模层1002～1006。举例而言，在一些实施例中，移除硬掩模层1002～1006可能会使高于基板102上的外延P型源极114及外延P型漏极116的厚度降低约1％到约10％(例如，从约
Figure BDA0003586708330000151
到约
Figure BDA0003586708330000152
)。在其他实施例中，移除硬掩模层1002～1006可能会使外延P型源极114及外延P型漏极116位于或低于基板102的表面。
虽然图4～图13描述具有外延P型源极与外延P型漏极的P型金属氧化物半导体装置的制造方法，然而，此方法可以通过改变装置的掺杂特性而适用于N型金属氧化物半导体装置。举例而言，N型金属氧化物半导体装置将具有外延N型源极与外延N型漏极。因此，此方法不会改变，而是改变掺质以适用于装置的类型。
请参照图14，提供图4～图13的方法的一些实施例的流程图。
在步骤1402，形成隔离结构于基板中。基板包括N阱区域及P阱区域。N阱区域可为高电压N型阱，且P阱区域可为高电压P型阱。隔离结构从基板的顶部表面延伸进入基板的内部。请参照，例如，图4。
在步骤1404，形成栅极层于基板上，栅极层可包括栅极介电质层及栅极电极层。此外，栅极掩模沉积于栅极层上。请参照，例如，图5。
在步骤1406，通过图案化栅极层，以形成栅极。栅极包括栅极介电质及栅极电极。请参照，例如，图6。
在步骤1408，形成侧壁间隔物于栅极的每一个侧壁上。请参照，例如，图7。
在步骤1410，通过斜角注入，以形成P型轻掺杂扩散区域于栅极下方且位于N阱区域中。在一些实施例中，P型轻掺杂扩散区域的一侧壁对准于栅极。请参照，例如，图8。
在步骤1412，通过离子注入操作，以形成隔离P阱及N+掺杂区域于第一N阱区域中，并且形成N+掺杂区域于第二N阱区域中。请参照，例如，图9。
在步骤1414，选择性地沉积硬掩模层于基板及栅极上。请参照，例如，图10。
在步骤1416，形成多边源极凹孔于基板的N阱区域中，且形成多边漏极凹孔于基板的P阱区域中。请参照，例如，图11。
在步骤1418，形成外延P型源极于多边源极凹孔中，且形成外延P型漏极于多边漏极凹孔中。请参照，例如，图12。
在步骤1420，移除硬掩模层。请参照，例如，图13。
外延P型源极及外延P型漏极可有益于降低RDS(on)。
虽然在此所绘示及描述的图14的流程图1400为一系列的动作或事件，然而，应可理解的是，在此所绘示的这些动作或事件的排序不被解释为具有限制性的。举例而言，一些动作可能会以不同的顺序发生及/或与其他动作或事件同时发生，这些其他动作或事件可能是与在此所绘示及描述的这一些动作彼此独立。此外，并非所有绘示的动作都需要实施于在此所描述的一或多个实施例中，且在此所描述的一或多个动作可实施于一或多个独立的动作及/或阶段中。
如上所述，本公开的一些实施例提供一种具有外延源极与漏极的集成电路，其可降低栅极烧毁并提高开关速度，因而适合于高电压的应用。此集成电路包括具有高电压N型阱高电压P型阱的半导体基板。此集成电路亦包括高电压装置位于该半导体基板之上。此高电压装置包括外延P型源极设置于高电压N型阱中，外延P型漏极设置于高电压P型阱中，以及栅极位于半导体基板的表面上的外延P型源极与外延P型漏极之间。
如前述的集成电路，其中该外延P型源极与该外延P型漏极是硅锗。
如前述的集成电路，其中该外延P型源极与该外延P型漏极具有一多边形形状。
如前述的集成电路，其中该多边形是六边形。
如前述的集成电路，其中该外延P型源极具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
如前述的集成电路，其中该第一侧包括：一第一上部晶面从该顶部晶面延伸至该高电压N型阱中；以及一第一下部晶面从该底部晶面延伸朝向该第一上部晶面，其中该第一上部晶面与该第一下部晶面交会于一第一点，该第一点低于该半导体基板的该表面。
如前述的集成电路，其中该第二侧包括：一第二上部晶面从该顶部晶面延伸至该高电压P型阱中；以及一第二下部晶面从该底部晶面延伸朝向该第二上部晶面，其中该第二上部晶面与该第二下部晶面交会于一第二点，该第二点低于该半导体基板的该表面，且其中该第一点与该第二点延伸至该半导体基板的该表面下方的一距离d1。
如前述的集成电路，其中该栅极包括一栅极介电质、一栅极电极以及多个侧壁间隙壁，其中所述多个侧壁间隙壁被该栅极介电质和该栅极电极隔离，其中该第一点位于所述多个侧壁间隙壁的一个侧壁间隙壁之下。
如前述的集成电路，其中该外延P型源极延伸至高于该半导体基板的该表面。
此外，本公开的其他实施例提供一种具有外延源极与漏极的集成电路。此集成电路包括具有高电压P型阱与高电压N型阱的半导体基板。此集成电路亦包括高电压装置位于该半导体基板之上。此高电压装置包括外延N型源极设置于高电压P型阱中，外延N型漏极设置于高电压N型阱中，以及栅极位于半导体基板的表面上的高电压P型阱与高电压N型阱之间。
如前述的集成电路，其中该外延N型源极与该外延N型漏极是磷化硅。
如前述的集成电路，其中该外延N型源极与该外延N型漏极具有一多边形形状。
如前述的集成电路，其中该多边形是六边形。
如前述的集成电路，其中该外延N型源极具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
如前述的集成电路，其中该第一侧包括：一第一上部晶面从该顶部晶面延伸至该高电压P型阱中；以及一第一下部晶面从该底部晶面延伸朝向该第一上部晶面，其中该第一上部晶面与该第一下部晶面交会于一第一点，该第一点低于该高电压P型阱的一最上方表面。
如前述的集成电路，该外延N型源极的一部分延伸高于该高电压P型阱的一最上方表面之上。
此外，本公开的其他实施例提供一种具有外延源极与漏极的集成电路的制造方法。此集成电路的制造方法包括形成多层栅极层于基板之上。此基板具有高电压N型阱与高电压P型阱。图案化上述多层栅极层，以形成具有栅极介电质与栅极电极的栅极。形成多个侧壁间隙壁于栅极介电质与栅极电极的每一个侧壁上。此集成电路的制造方法亦包括选择性沉积多个硬掩模层于基板与栅极之上。进行斜角蚀刻，以形成多边源极凹孔于高电压N型阱之中，且形成多边漏极凹孔于高电压P型阱之中。多边源极凹孔与多边漏极凹孔具有实质上平面的多个边缘，且上述多个边缘在多个角落相连接。形成外延P型源极于多边源极凹孔之中，且形成外延P型漏极于多边漏极凹孔之中。外延P型源极与外延P型漏极具有多边形形状。接着移除上述多个硬掩模层。
如前述的集成电路的制造方法，其中该外延P型源极与该外延P型漏极由硅锗所形成。
如前述的集成电路的制造方法，其中该外延P型源极与该外延P型漏极各自具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
如前述的集成电路的制造方法，其中该第一侧的该两个斜角晶面交会于一第一点，且该第二侧的该两个斜角晶面交会于一第二点，且其中该第一点与该第二点位于至高于该半导体基板的一上表面下方的一距离d1。
前述内文概述了许多实施例的特征，使本领域普通技术人员可以从各个方面更佳地了解本公开。本领域普通技术人员应可理解，且可轻易地以本公开为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本领域普通技术人员也应了解这些相等的结构并未背离本公开的发明构思与范围。在不背离本公开的发明构思与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (20)

1.一种集成电路，包括：
一半导体基板，具有一高电压N型阱与一高电压P型阱；
一高电压装置，位于该半导体基板之上，其中该高电压装置包括一外延P型源极设置于该高电压N型阱中，一外延P型漏极设置于该高电压P型阱中，以及一栅极位于该半导体基板的一表面上的该外延P型源极与该外延P型漏极之间；
一隔离P阱，于该高电压N型阱中，其中该外延P型源极延伸到该隔离P型阱之中；
一隔离结构，包括一介电材料并延伸进入该半导体基板中，其中该隔离P阱在该外延P型源极和该隔离结构下方延伸；
一N+掺杂区域，于该高电压N型阱中且与该隔离结构相邻；以及
一P型轻掺杂扩散区域，设置于该高电压N型阱中并且与该栅极的边缘对准。
2.如权利要求1所述的集成电路，其中该外延P型源极与该外延P型漏极是硅锗。
3.如权利要求1所述的集成电路，其中该外延P型源极与该外延P型漏极具有六边形形状。
4.如权利要求1所述的集成电路，其中该外延P型源极的一部分延伸于该高电压N型阱的一最上方表面之上一第一距离，且该第一距离大于该栅极的一高度。
5.如权利要求1所述的集成电路，其中该外延P型源极具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
6.如权利要求5所述的集成电路，其中该第一侧包括：
一第一上部晶面从该顶部晶面延伸至该高电压N型阱中；以及
一第一下部晶面从该底部晶面延伸朝向该第一上部晶面，其中该第一上部晶面与该第一下部晶面交会于一第一点，该第一点低于该半导体基板的该表面。
7.如权利要求6所述的集成电路，其中该第二侧包括：
一第二上部晶面从该顶部晶面延伸至该高电压P型阱中；以及
一第二下部晶面从该底部晶面延伸朝向该第二上部晶面，其中该第二上部晶面与该第二下部晶面交会于一第二点，该第二点低于该半导体基板的该表面，且该第一点与该第二点延伸至该半导体基板的该表面下方的一第二距离。
8.如权利要求6所述的集成电路，其中该栅极包括一栅极介电质、一栅极电极以及多个侧壁间隙壁，所述多个侧壁间隙壁被该栅极介电质和该栅极电极隔离，该第一点位于所述多个侧壁间隙壁的一个侧壁间隙壁之下。
9.如权利要求1所述的集成电路，其中该外延P型源极延伸至高于该半导体基板的该表面。
10.一种集成电路，包括：
一半导体基板，具有一高电压P型阱与一高电压N型阱；
一高电压装置，位于该半导体基板之上，其中该高电压装置包括一外延N型源极设置于该高电压P型阱中，一外延N型漏极设置于该高电压N型阱中，以及一栅极位于该半导体基板的一表面上的该高电压P型阱与该高电压N型阱之间；
一隔离N阱，于该高电压P型阱中，其中该外延N型源极延伸到该隔离N阱之中；
一隔离结构，包括一介电材料并延伸进入该半导体基板中，其中隔离N阱在该外延N型源极和该隔离结构下方延伸；
一P+掺杂区域，于该高电压P型阱中且与该隔离结构相邻；以及
一N型轻掺杂扩散区域，设置于该高电压P型阱中并且与该栅极的边缘对准。
11.如权利要求10所述的集成电路，其中该外延N型源极与该外延N型漏极是磷化硅。
12.如权利要求10所述的集成电路，其中该外延N型源极与该外延N型漏极具有六边形形状。
13.如权利要求10所述的集成电路，其中该外延N型源极的一部分延伸于该高电压P型阱的一最上方表面之上一距离，且该距离大于该栅极的一高度。
14.如权利要求10所述的集成电路，其中该外延N型源极具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
15.如权利要求14所述的集成电路，其中该第一侧包括：
一第一上部晶面从该顶部晶面延伸至该隔离N阱中；以及
一第一下部晶面从该底部晶面延伸朝向该第一上部晶面，其中该第一上部晶面与该第一下部晶面交会于一第一点，该第一点低于该高电压P型阱的该最上方表面。
16.一种集成电路的制造方法，包括：
形成一隔离结构于一基板之中且延伸进入该基板，该隔离结构包括一介电材料；
形成多层栅极层于该基板之上，其中该基板具有一高电压N型阱与一高电压P型阱；
图案化所述多层栅极层，以形成具有一栅极介电质与一栅极电极的一栅极；
形成多个侧壁间隙壁于该栅极介电质与该栅极电极的每一个侧壁上；
实施一斜角注入以形成一P型轻掺杂扩散区域于该栅极下方且位于该高电压N型阱中；
形成一隔离P阱于该高电压N型阱中；
形成一N+掺杂区域于该高电压N型阱中且与该隔离结构相邻；
选择性沉积多个硬掩模层于该基板与该栅极之上；
在形成该隔离P阱之后，进行一斜角蚀刻，以形成一多边源极凹孔于该高电压N型阱和该隔离P阱之中，且形成一多边漏极凹孔于该高电压P型阱之中，其中该多边源极凹孔与该多边漏极凹孔具有实质上平面的多个边缘，且所述多个边缘在多个角落相连接；
形成一外延P型源极于该多边源极凹孔之中，且形成一外延P型漏极于该多边漏极凹孔之中，其中该外延P型源极与该外延P型漏极具有一多边形形状，且该隔离P阱在该外延P型源极和该隔离结构下方延伸；以及
移除所述多个硬掩模层。
17.如权利要求16所述的集成电路的制造方法，其中该外延P型源极的一部分延伸于该高电压N型阱的一最上方表面之上一第一距离，且该第一距离大于该栅极的一高度。
18.如权利要求16所述的集成电路的制造方法，其中该外延P型源极与该外延P型漏极各自具有六个实质上平面的晶面，包括一底部晶面、一顶部晶面、具有两个斜角晶面的一第一侧、以及具有两个斜角晶面的一第二侧。
19.如权利要求18所述的集成电路的制造方法，其中该第一侧的该两个斜角晶面交会于一第一点，且该第二侧的该两个斜角晶面交会于一第二点，且该第一点与该第二点位于至高于该半导体基板的一上表面下方的一第二距离。
20.如权利要求16所述的集成电路的制造方法，其中在形成该N+掺杂区域之后，形成该外延P型源极。
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