TWI677095B - 積體電路及其製造方法 - Google Patents

積體電路及其製造方法 Download PDF

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TWI677095B
TWI677095B TW106135924A TW106135924A TWI677095B TW I677095 B TWI677095 B TW I677095B TW 106135924 A TW106135924 A TW 106135924A TW 106135924 A TW106135924 A TW 106135924A TW I677095 B TWI677095 B TW I677095B
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epitaxial
type
voltage
crystal plane
well
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TW106135924A
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TW201916358A (zh
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陳奕寰
Yi Huan Chen
鄭光茗
Kong Beng Thei
周建志
Chien Chih Chou
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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Abstract

一種具有磊晶源極與汲極的積體電路被提供，其可降低閘極燒毀並提高開關速度，因而適合於高電壓之應用。此積體電路包括具有高電壓N型井高電壓P型井的半導體基板。此積體電路亦包括高電壓裝置位於該半導體基板之上。此高電壓裝置包括磊晶P型源極設置於高電壓N型井中，磊晶P型汲極設置於高電壓P型井中，以及閘極位於半導體基板之表面上之磊晶P型源極與磊晶P型汲極之間。

Description

積體電路及其製造方法
本揭露係有關於一種半導體裝置，且特別有關於一種具有磊晶源極與汲極的積體電路及其製造方法。
現代積體晶片使用廣泛的裝置以實現不同的功能。一般而言，積體晶片包括主動裝置和被動裝置。主動裝置包括電晶體，例如，金屬氧化物半導體場效電晶體(MOSFETs)。基於金屬氧化物半導體場效電晶體裝置的開關速度，金屬氧化物半導體場效電晶體裝置使用於車輛電子系統、電源供應及電源管理應用中。開關速度至少部分地基於金屬氧化物半導體場效電晶體裝置的RDS(on)。RDS(on)代表「汲極-源極導通電阻」，或是當金屬氧化物半導體場效電晶體為「導通」時，金屬氧化物半導體場效電晶體中汲極和源極之間的總電阻。RDS(on)與電流損耗相關，並且是金屬氧化物半導體場效電晶體最大電流額定值的基礎。
本揭露之一實施係提供一種積體電路，包括：半導體基板，具有高電壓N型井與高電壓P型井；高電壓裝置位於半導體基板之上，其中高電壓裝置包括磊晶P型源極設置於高 電壓N型井中，磊晶P型汲極設置於高電壓P型井中，以及閘極位於半導體基板之表面上之磊晶P型源極與磊晶P型汲極之間。
本揭露之另一實施係提供一種積體電路，包括：半導體基板，具有高電壓P型井與高電壓N型井；高電壓裝置位於半導體基板之上，其中高電壓裝置包括磊晶N型源極設置於高電壓P型井中，磊晶N型汲極設置於高電壓N型井中，以及閘極位於半導體基板之表面上之高電壓P型井與高電壓N型井之間。
本揭露之又一實施係提供一種積體電路之製造方法，包括：形成複數層閘極層於基板之上，其中基板具有高電壓N型井與高電壓P型井；圖案化上述閘極層，以形成具有閘極介電質與閘極電極的閘極；形成複數個側壁間隙壁於閘極介電質與閘極電極之每一個側壁上；選擇性沉積複數個硬罩幕層於基板與閘極之上；進行斜角蝕刻，以形成多邊源極凹孔於高電壓N型井之中，且形成多邊汲極凹孔於高電壓P型井之中，其中多邊源極凹孔與多邊汲極凹孔具有實質上平面的複數個邊緣，且上述邊緣在複數個角落相連接；形成磊晶P型源極於多邊源極凹孔之中，且形成磊晶P型汲極於多邊汲極凹孔之中，其中磊晶P型源極與磊晶P型汲極具有多邊形形狀；以及移除上述硬罩幕層。
100‧‧‧P型金屬氧化物半導體電晶體
102‧‧‧基板
104a‧‧‧第一N井區域
104b‧‧‧第二N井區域
106‧‧‧P井區域
108‧‧‧隔離P井
110a‧‧‧第一N+摻雜區域
110b‧‧‧第二N+摻雜區域
112a‧‧‧第一隔離結構
112b‧‧‧第二隔離結構
112c‧‧‧第三隔離結構
114‧‧‧磊晶P型源極
116‧‧‧磊晶P型汲極
118‧‧‧P型輕摻雜擴散區域
120‧‧‧閘極
122‧‧‧閘極介電質
124‧‧‧閘極介電質
126‧‧‧側壁間隔物
150‧‧‧底部晶面
152‧‧‧頂部晶面
154‧‧‧第一側
156‧‧‧第二側
158‧‧‧第一上部晶面
160‧‧‧第一下部晶面
162‧‧‧第一點
164‧‧‧第二上部晶面
166‧‧‧第二下部晶面
168‧‧‧第二點
200‧‧‧N型金屬氧化物半導體電晶體
202‧‧‧基板
204a‧‧‧第一P井區域
204b‧‧‧第二P井區域
206‧‧‧N井區域
208‧‧‧隔離N井
210a‧‧‧第一P+摻雜區域
210b‧‧‧第二P+摻雜區域
212a‧‧‧第一隔離結構
212b‧‧‧第二隔離結構
212c‧‧‧第三隔離結構
214‧‧‧磊晶N型源極
216‧‧‧磊晶N型汲極
218‧‧‧N型輕摻雜擴散區域
220‧‧‧閘極
222‧‧‧閘極介電質
224‧‧‧閘極電極
226‧‧‧側壁間隔物
300‧‧‧積體電路
302‧‧‧半導體基板
304‧‧‧P型金屬氧化物半導體裝置
306‧‧‧N型金屬氧化物半導體裝置
308‧‧‧P型金屬氧化物半導體井區域
308a‧‧‧第一P型金屬氧化物半導體井區域
308b‧‧‧第二P型金屬氧化物半導體井區域
310s‧‧‧磊晶源極
310d‧‧‧磊晶汲極
312‧‧‧通道區域
314‧‧‧閘極結構
316‧‧‧閘極電極
318‧‧‧閘極介電質
320a、320b‧‧‧隔離區域
322‧‧‧N型金屬氧化物半導體井區域
322a‧‧‧第一N型金屬氧化物半導體井區域
322b‧‧‧第二N型金屬氧化物半導體井區域
324s‧‧‧磊晶源極
324d‧‧‧磊晶汲極
326‧‧‧通道區域
328‧‧‧閘極結構
330‧‧‧閘極電極
332‧‧‧閘極介電質
334‧‧‧層間介電質結構
336‧‧‧第一組內連線層
336a‧‧‧接觸
336b‧‧‧金屬線層
336c‧‧‧金屬介層窗層
338‧‧‧第二組內連線層
338a‧‧‧接觸
338b‧‧‧金屬線層
338c‧‧‧金屬介層窗層
340‧‧‧覆蓋結構
342‧‧‧第一鈍化層
344‧‧‧第二鈍化層
346‧‧‧第一接合墊
348‧‧‧第二接合墊
400、500、600、700、800、900、1000、1100、1200、1300‧‧‧剖面圖
502‧‧‧閘極層
504‧‧‧閘極介電質層
506‧‧‧閘極電極層
508‧‧‧閘極罩幕
602‧‧‧第一圖案化
802‧‧‧斜角佈植
1002、1004、1006‧‧‧硬罩幕層
1102‧‧‧第二圖案化
1104‧‧‧多邊源極凹孔
1106‧‧‧多邊汲極凹孔
1400‧‧‧流程圖
1402、1404、1406、1408、1410、1412、1414、1416、1418、1420‧‧‧步驟
d1、d2‧‧‧距離
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1A圖為根據一些實施例繪示一具有磊晶源極與汲極的P型金屬氧化物半導體(PMOS)的剖面圖。
第1B圖為第1A圖所繪示之磊晶源極與汲極的局部放大剖面圖。
第2圖為根據一些實施例繪示一具有磊晶源極與汲極的N型金屬氧化物半導體(NMOS)的剖面圖。
第3圖為根據一些實施例繪示一具有用於高電壓裝置之磊晶源極與汲極的積體電路(IC)的剖面圖。
第4-13圖為根據一些實施例繪示一具有磊晶源極與汲極的積體電路的製造方法的一系列剖面圖。
第14圖為根據第4-13圖的實施例之製造方法的流程圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參照符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外，其與空間相關用詞。例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
高電壓裝置由於其較高的開關速度而被廣泛應用於電源管理、電信等領域。然而，一些不預發生的效應，例如，高RDS(on)，在切換期間會導致開關速度降低與較多的能量損失。需要較低的RDS(on)，以避免電流損耗，並達到適合於相關設備之較高的最大電流額定值。例如，因為高電壓裝置需要較高的最大電流額定值，所以需要較低的RDS(on)。
裝置，例如，高電壓裝置，可包括電晶體，此電晶體具有由閘極所分隔的源極與汲極。源極與汲極通常藉由在基板中佈植雜質而形成。然而，佈植製程可能會損壞位於源極與汲極的基板表面。基板中的缺陷可能會對操作產生負面影響，例如，提高RDS(on)。在此，不是在基板中佈植雜質以形成源極與汲極，而是磊晶成長源極與汲極。由於成長源極與汲極，源極與汲極的表面不會產生因離子佈植而引起的缺陷。因此，此處描述一種用於高電壓裝置的磊晶源極與汲極，以減少RDS(on)。此外，源極與汲極的摻雜密度可以藉由磊晶成長而增加，如此也會降低RDS(on)。
請參照第1A圖，其係繪示一具有磊晶P型源極與汲極的P型金屬氧化物半導體(PMOS)電晶體100的一些實施例的剖面圖。P型金屬氧化物半導體電晶體100包括半導體基板102。基板102具有N井區域，N井區域包括第一N井區域104a及第二N井區域104b。在一些實施例中，N井區域104a、104b是高電壓N型井(high-voltage N-well,HVNW)。N井區域104a、104b具有N型摻質，並且可具有介於約1015-1017摻質/cm3之間的摻雜濃度。基板102亦包括P井區域106。在一些實施例中，P井區域106是高電壓P型井(high-voltage P-well,HVPW)。P井區域106設置在第一N井區域104a與第二N井區域104b之間。P井區域106具有P型摻質，並且可具有介於約1015-1017摻質/cm3之間的摻雜濃度。
佈植隔離P井(isolated P-well)108於第一N井區域104a中。在一些實施例中，隔離P井108具有P型摻質，並且可具有介於約1016-1018摻質/cm3之間的摻雜濃度。隔離P井108從基板102的最上方表面延伸到第一N井區域104a。
N井區域104a、104b亦包括N+摻雜區域110a、110b。舉例而言，在第一N井區域104a中佈植第一N+摻雜區域110a，並且在第二N井區域104b中佈植第二N+摻雜區域110b。N+摻雜區域110a、110b的功能在於作為與N井區域104a、104b的主體接觸(body contact)。N+摻雜區域110a、110b可摻雜比N井區域104a、104b更高濃度的N型摻質(例如，硼)，使N+摻雜區域作為與N井區域104a、104b的接觸。
隔離結構112a、112b、112c定義出各種主動特徵的區域並將它們彼此隔離。隔離結構112a、112b、112c可包括第 一隔離結構112a、第二隔離結構112b及第三隔離結構112c。舉例而言，隔離結構112a、112b、112c可以是，例如，淺溝槽隔離結構、深溝槽隔離結構或一些其它類型的隔離結構，並且，例如，可以填充介電材料，例如二氧化矽。
磊晶P型源極114設置在第一N井區域104a中，且磊晶P型汲極116設置在P井區域106中。磊晶P型源極114及磊晶P型汲極116成長為磊晶層。磊晶P型源極114及磊晶P型汲極116成長為磊晶層具有多邊形形狀。在一些實施例中，多邊形形狀是六邊形，如第1B圖所示。
請轉而參照第1B圖，其繪示多邊形的磊晶P型源極114嵌埋於第一N井區域104a中。磊晶P型源極114具有六個實質上平面的晶面(facet)，包括底晶面150、頂晶面152、具有兩個斜角晶面(angled facet)的第一側154及具有兩個斜角晶面的第二側156。第一側154具有從頂部晶面152延伸到隔離P井108之中的第一上部晶面158。第一側154亦具有從底部晶面150朝向第一上部晶面158延伸的第一下部晶面160。第一上部晶面158與第一下部晶面160在第一點162相交，第一點162位於第一N井區域104a的最上方表面104a'下方一段距離d1。由於基板102包括N井區域104，所以第一N井區域104a的最上方表面104a'是基板102的最上方表面。
第二側156具有從頂部晶面152延伸到第一N井區域104a的第二上部晶面164。第二側156亦具有從底部晶面150朝向第二上部晶面164延伸的第二下部晶面166。第二上部晶面164和第二下部晶面166在第二點168相交，第二點168位於第一 N井區域104a的最上方表面104a'下方一段距離d1。因此，磊晶P型源極114可嵌埋於第一N井區域104a中，使第一點162和第二點168位於最上方表面104a'下方一段距離d1。在一些實施例中，第一點162可位於閘極介電質124或側壁間隔物126的一個側壁間隔物下方。
磊晶P型源極114的一部分延伸於第一N井區域104a的最上方表面104a'上方一段距離d2。延伸於最上方表面104a'上方之磊晶P型源極114的量可基於磊晶成長製程而定。距離d2可大於距離d1。在一些實施例中，距離d2可大於基板102上的其它特徵的高度。例如，距離d2可大於閘極120的高度。由於磊晶P型源極114的磊晶成長，因而晶面150、152、158、160、164及166實質上是平滑的。
第1B圖繪示磊晶P型源極114、磊晶P型汲極116即使不是相同的尺寸，也可具有相似的尺寸。舉例而言，磊晶P型汲極116也可在側面具有斜角晶面，其延伸而在P井區域106的最上方表面下方的點之位置相交。此外，可基於多邊形的拉伸強度，而選擇用於磊晶P型源極114及/或磊晶P型汲極116的多邊形形狀，然而，也可使用其它形狀。
請參照回1A圖，在一些實施例中，磊晶P型源極114及磊晶P型汲極116可為包括晶體結構之矽或鍺的P型元素半導體。在其它實施例中，磊晶P型源極114及磊晶P型汲極116包括P型合金，例如，矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)、磷砷化銦鎵(GaInAsP)、或鍺組成從在一個位置的一 比例變化為在另一個位置的另一比例。磊晶P型源極114及磊晶P型汲極116的摻雜濃度範圍介於約1020-1021雜質/cm3之間。
P型輕摻雜擴散(P-type lightly doped diffusion,PLDD)區域118設置在第一N井區域104a中並且與閘極120的邊緣對準，並且位於間隔物126下方。閘極120形成於基板102的最上方表面，並且在水平方向上插入在磊晶P型源極114與磊晶P型汲極116之間。閘極120可延伸於第二隔離結構112b上，第二隔離結構112b位於磊晶P型源極114與磊晶P型汲極116之間。閘極120包括閘極介電質122、閘極電極124及側壁間隔物126，側壁間隔物126鄰接閘極介電質122及閘極電極124的側壁。
磊晶P型源極114、磊晶P型汲極116及閘極120共同形成P型金屬氧化物半導體電晶體100。因為磊晶P型源極114及磊晶p型汲極116成長，所以磊晶P型源極114及磊晶P型汲極116不會產生藉由離子佈植形成源極與汲極時通常會發生的缺陷。此外，磊晶成長可為磊晶P型源極114和磊晶P型汲極116提供更高的摻雜濃度。這些優點具有降低P型金屬氧化物半導體電晶體100的RDS(on)的作用。較低的RDS(on)有利於促進P型金屬氧化物半導體電晶體100中的電流流動，因此，可降低閘極燒毀(burnout)並提高開關速度，而適合於高電壓之應用。
請參照第2圖，其係繪示一具有磊晶N型源極與汲極的N型金屬氧化物半導體(NMOS)電晶體200的一些實施例的剖面圖。N型金屬氧化物半導體電晶體200包括基板202。基板102具有P井區域，P井區域包括第一P井區域204a及第二P井區 域204b。在一些實施例中，P井區域204a、204b是高電壓P型井(high-voltage P-well,HVPW)，如同以上第1A圖所述之P井區域106。基板202亦包括N井區域206。N井區域206設置在第一P井區域204a與第二P井區域204b之間。在一些實施例中，N井區域206是高電壓N型井(high-voltage N-well,HVNW)，如同以上第1A圖所述之N井區域104a、104b。
佈植隔離N井(isolated N-well)208於第一P井區域204a中。在一些實施例中，隔離N井208具有N型摻質，並且可具有介於約1016-1018摻質/cm3之間的摻雜濃度。P井區域204a、204b亦分別包括P+摻雜區域210a、210b。舉例而言，在第一P井區域204a中佈植第一P+摻雜區域210a，並且在第二P井區域204b中佈植第二P+摻雜區域210b。P+摻雜區域210a、210b的功能在於作為與P井區域204的主體接觸。
隔離結構212a、212b、212c可包括第一隔離結構212a、第二隔離結構212b及第三隔離結構212c。舉例而言，隔離結構212a、212b、212c可以是，例如，淺溝槽隔離結構、深溝槽隔離結構或一些其它類型的隔離結構。隔離結構212a、212b、212c從基板202的頂部表面延伸，如同以上第1A圖所述。
磊晶N型源極214設置在第一P井區域204a中，且磊晶N型汲極216設置在N井區域206中。磊晶N型源極214及磊晶N型汲極216成長為之具有N型材料的磊晶層，如同以上所述。舉例而言，在此，磊晶N型源極214及磊晶N型汲極216包括N型元素半導體，N型元素半導體包括矽或磷，例如，磷化矽(SiP)。此外，即使不是相同的多邊形形狀，磊晶N型源極214及磊晶N 型汲極216也可具有相似的多邊形形狀，如同以上第1B圖所述。
N型輕摻雜擴散(N-type lightly doped diffusion,NLDD)區域218設置在第一P井區域204a中並且與閘極220的邊緣對準。閘極220形成於基板202的最上方表面，並且在水平方向上插入在磊晶N型源極214與磊晶N型汲極216之間。閘極220包括閘極介電質222、閘極電極224及側壁間隔物226，側壁間隔物226鄰接閘極介電質222及閘極電極224的側壁。磊晶N型源極214、磊晶N型汲極216及閘極220共同形成N型金屬氧化物半導體電晶體200。如同上述的P型金屬氧化物半導體電晶體100，N型金屬氧化物半導體電晶體200提供較低的RDS(on)。
請參照第3圖，其係繪示一具有用於高電壓裝置之磊晶源極與汲極的積體電路(IC)的一些實施例的剖面圖。積體電路300包括設置於半導體基板302之上的P型金屬氧化物半導體裝置304及N型金屬氧化物半導體裝置306。P型金屬氧化物半導體裝置304包括P型金屬氧化物半導體井區域308設置於半導體基板302之中。P型金屬氧化物半導體井區域308包括第一P型金屬氧化物半導體井區域308a及第二P型金屬氧化物半導體井區域308b。第一P型金屬氧化物半導體井區域308a具有第一摻雜類型，第二P型金屬氧化物半導體井區域308b具有第二摻雜類型，且第二摻雜類型不同於第一摻雜類型。舉例而言，當第二P型金屬氧化物半導體井區域308b為高電壓P型井，第一P型金屬氧化物半導體井區域308a可為高電壓N型井。P型金屬氧化物半導體電晶體設置於P型金屬氧化物半導體井區域308之中。P型金屬氧化物半導體電晶體包括磊晶源極310s，磊晶源極310s藉由通道區域312而與磊晶汲極310d隔開。閘極結構314設置於通道區域312之上。閘極結構314包括閘極電極316，閘極電極316藉由閘極介電質318而與通道區域312隔開。在一些實施例中，隔離區域320a(例如，淺溝槽隔離區域)設置於半導體基板302之中，且位於磊晶源極310s與磊晶汲極310d之間。
N型金屬氧化物半導體裝置306包括N型金屬氧化物半導體井區域322設置於半導體基板302之中。N型金屬氧化物半導體井區域322包括第一N型金屬氧化物半導體井區域322a及第二N型金屬氧化物半導體井區域322b。第一N型金屬氧化物半導體井區域322a具有第一摻雜類型，第二N型金屬氧化物半導體井區域3具有第二摻雜類型，且第二摻雜類型不同於第一摻雜類型。舉例而言，當第二N型金屬氧化物半導體井區域322b為高電壓N型井，第一N型金屬氧化物半導體井區域322a可為高電壓P型井。N型金屬氧化物半導體電晶體設置於N型金屬氧化物半導體井區域322之中。N型金屬氧化物半導體電晶體包括磊晶源極324s，磊晶源極324s藉由通道區域326而與磊晶汲極324d隔開。閘極結構328設置於通道區域326之上。閘極結構328包括閘極電極330，閘極電極330藉由閘極介電質332而與通道區域326隔開。在一些實施例中，隔離區域320b(例如，淺溝槽隔離區域)設置於半導體基板302之中，且位於磊晶源極324s與磊晶汲極324d之間。
層間介電質(inter-layer dielectric,ILD)結構334設置於半導體基板302之上。在一些實施例中，層間介電質結構334可包括氧化物、低介電常數(low-k)介電質或超低介電常數 (ultra-low-k)介電質。第一組內連線層336包括接觸336a、金屬線層336b及金屬介層窗層336c，其受到層間介電質結構334包圍，並且覆蓋P型金屬氧化物半導體裝置304。第二組內連線層338包括接觸338a、金屬線層338b及金屬介層窗層338c，其受到層間介電質結構334包圍，並且覆蓋N型金屬氧化物半導體裝置306。在一些實施例中，第一組內連線層336及第二組內連線層338可包括銅、鎢及/或鋁。層間介電質結構334受到覆蓋結構340所覆蓋。覆蓋結構340可包括複數個鈍化層，例如，第一鈍化層342及第二鈍化層344。第一鈍化層342及第二鈍化層344可包括以下材料：第一鈍化層342和第二鈍化層344可以包括作為氧化物或氮化物(例如，氧化矽、氮化矽)、未摻雜的矽酸鹽玻璃及/或上述之多層結構。接合墊，其包括第一接合墊346及第二接合墊348，被設置在覆蓋結構340中。第一接合墊346及第二接合墊348由導電材料所製成，例如，銅。在一些實施例中，第一接合墊346透過第一組內連線層336連接到P型金屬氧化物半導體裝置304，且第二接合墊348透過第二組內連線層338連接到N型金屬氧化物半導體裝置306。
請參照第4-13圖，其係一系列剖面圖400-1300，用以繪示一具有磊晶源極與磊晶汲極的積體電路的製造方法的一些實施例，其係用於P型金屬氧化物半導體電晶體，例如，第1A圖的P型金屬氧化物半導體電晶體。
如第4圖的剖面圖400所繪示，提供基板102。基板102可由半導體材料所形成。在一些實施例中，基板102為塊材(bulk)單晶矽基板。在另一些實施例中，基板102為絕緣體上覆半導體(SOI)基板，包括承載基板，位於承載基板上的絕緣層，以及位於絕緣層上的裝置層，其中裝置層由半導體材料所形成。隔離結構112a、112b、112c形成於基板之中，且延伸進入基板102的頂部表面中。基板102可具有介於約1.5-4μm的厚度。舉例而言，基板102可為約2.5μm厚。隔離結構112a、112b、112c可從基板102的頂部表面延伸到深度為，例如，約1μm。隔離結構112a、112b、112c劃分基板102的裝置區域，例如，邏輯區域或高電壓裝置區域。在一些實施例中，用以形成隔離結構112a、112b、112c的製程包括：形成溝槽，以及隨後使用介電質材料填充這些溝槽。
使用摻質佈植基板，以形成N井區域104a、104b及P井區域106。如上所述，N井區域104a、104b具有N型摻質，並且可具有介於約1015-1017摻質/cm3之間的摻雜濃度，P井區域106具有P型摻質，並且可具有介於約1015-1017摻質/cm3之間的摻雜濃度。N井區域104a、104b可具有介於約2-5μm的厚度。
如第5圖的剖面圖500所繪示，複數個閘極層502形成於基板102上。在一些實施例中，閘極層502包括閘極介電質層504及閘極電極層506。在一些實施例中，閘極介電質層504，例如，可包括高介電常數(high-k)介電質，且閘極電極層506可包括多晶矽。雖然閘極介電質層504與閘極電極層506被繪示為單層，然而，其每一層可分別由多層所形成。閘極罩幕508選擇性地沉積於上述複數個閘極層502上。特別是，閘極罩幕508被形成並圖案化，以位於第一隔離結構112a和第二隔離結構112b之間。在一些實施例中，閘極罩幕508為光阻層。
如第6圖的剖面圖600所繪示，使用閘極罩幕(第5圖的508)將複數個閘極層502在適當的位置圖案化。舉例而言，可利用光微影(photolithography)製程將上述複數個閘極層(第5圖的502)圖案化，以實施第一圖案化602。或者，可藉由將上述複數個閘極層(第5圖的502)暴露於蝕刻劑中，以實施第一圖案化602。在另一實施例中，可利用蝕刻劑蝕刻上述複數個閘極層(第5圖的502)，以實施第一圖案化602。蝕刻劑可包括具有蝕刻化學性質之包括氟物質的乾式蝕刻劑(例如，四氟甲烷、三氟甲烷、八氟環丁烷等)，或是包括氫氟酸(HF)的濕式蝕刻劑。之後，將閘極罩幕(第5圖的508)剝除，以形成閘極介電質122與閘極電極124。
如第7圖的剖面圖700所繪示，側壁間隔物126沿著閘極介電質122及閘極電極124的側壁而形成，以形成閘極120。側壁間隔物126可為，例如，氧化物或其他介電質，例如，氮化矽。在一些實施例中，用以形成側壁間隔物126的製程包括：形成側壁間隔物層分別順應性地覆蓋於且襯墊於閘極介電質122及閘極電極124。側壁間隔物層可藉由，例如，高溫氧化(high temperature oxidation,HTO)之後進行快速熱退火(rapid thermal annealing,RTA)而形成。此外，在一些實施例中，上述製程包括對側壁間隔物層實施回蝕刻(etch back)，以移除側壁間隔物層的水平部份，而不移除側壁間隔物層的垂直部份。在回蝕刻之後，上述垂直部份仍留在對應於側壁間隔物126之適當的位置。
如第8圖的剖面圖800所繪示，實施斜角佈植802， 以形成P型輕摻雜擴散區域118於閘極120下方且位於第一N井區域104a中。斜角佈植802具有不同於第一N井區域104a的導電類型(例如，P+)。在一些實施例中，斜角佈植802可佈植於基板之包括104a、104b及106暴露的表面區域中(未繪示)，然而，也可藉由場氧化物(field oxide)或其他阻擋結構(未繪示)阻擋斜角佈植802，且因此只有P型輕摻雜擴散區域118被繪示。
如第9圖的剖面圖900所繪示，使用P井罩幕(未繪示)在適當的位置實施正常的P型離子佈植操作，以形成隔離P井108(所謂「正常」，意指垂直於基板102的表面)。使用N井罩幕(未繪示)在適當的位置實施正常的N型離子佈植操作，以在第一N井區域104a中形成第一N+摻雜區域110a，且同時在第二N井區域104b中形成第二N+摻雜區域110b。隔離P井108可具有介於約0.5-2μm的厚度。在另一實施例中，隔離P井108的厚度可介於約1-1.5μm。
如第10圖的剖面圖1000所繪示，沉積硬罩幕層1002-1006。硬罩幕層1002及1006選擇性地沉積於基板102上，且硬罩幕層1004選擇性地沉積於閘極120上。硬罩幕層1002-1006可由氮化矽(Si3N4)所形成。
如第11圖的剖面圖1100所繪示，藉由第二圖案化1202蝕刻基板102的最上方表面，以形成多邊源極凹孔(multi-edged source cavity)1104與多邊汲極凹孔(multi-edged drain cavity)1106。在一些實施例中，第二圖案化1202為斜角蝕刻，其可允許凹孔沿著一斜角延伸於基板102中。多邊源極凹孔1104與多邊汲極凹孔1106具有複數個實質上平面的邊 緣，且這些邊緣在角落相連接。第二圖案化1202的蝕刻劑可包括具有蝕刻化學性質的乾式蝕刻劑，例如，氟物質(例如，四氟甲烷、三氟甲烷、八氟環丁烷等)，或是濕式蝕刻劑，例如，氫氟酸。
如第12圖的剖面圖1200所繪示，藉由磊晶成長製程形成磊晶P型源極114及磊晶P型汲極116。磊晶P型源極114形成於多邊源極凹孔中(第11圖的1104)，且磊晶P型汲極116形成於多邊汲極凹孔中(第11圖的1106)。磊晶P型源極114及磊晶P型汲極116藉由磊晶技術成長。假設磊晶P型源極114是矽鍺(SiGe)。可在化學氣相沉積(CVD)反應器、低壓化學氣相沉積(LPCVD)反應器或超高真空化學氣相沉積(ultra-high vacuum CVD,UHVCVD)中進行，反應器溫度可介於600-800℃之間，反應器壓力可介於1-760Torr之間。載送氣體可由氫或氦形成，流速介於10-50SLM之間。
可使用矽源前驅物氣體進行沉積，例如，二氯矽烷(DCS或SiH2Cl2)、矽烷(SiH4)或乙矽烷(Si2H6)。舉例而言，可在流速介於15-100SCCM的條件下使用二氯矽烷。沉積也可使用鍺源前驅物氣體，例如，四氫化鍺(GeH4)稀釋於氫氣中(例如，四氫化鍺可被稀釋為1-5%)。舉例而言，可在濃度為1%且流速介於50-300SCCM的條件下使用稀釋的四氫化鍺。據此，可成長磊晶P型源極114。
在此，此一製造具有磊晶源極與汲極的積體電路的方法是針對P型金屬氧化物半導體電晶體而描述，例如，第1A圖的P型金屬氧化物半導體電晶體。據此，磊晶P型汲極116可以也是矽鍺。因此，磊晶P型汲極116可藉由相似的製程而成長。然而，此一製造具有磊晶源極與汲極的積體電路的方法也可使用於N型金屬氧化物半導體電晶體，例如，第2圖的N型金屬氧化物半導體電晶體。磊晶N型源極214及磊晶N型汲極216可由磷化矽(SiP)所形成。舉例而言，不使用鍺源前驅物氣體，而可使用磷源前驅物氣體形成磊晶N型源極214及磊晶N型汲極216。磊晶成長製程可使磊晶P型源極114汲磊晶P型汲極116成長高於基板102的最上方表面。
如第13圖的剖面圖1300所繪示，在成長磊晶P型源極114及磊晶P型汲極116之後，從基板102及閘極120移除硬罩幕層1002-1006。舉例而言，在一些實施例中，移除硬罩幕層1002-1006可能會使高於基板102上的磊晶P型源極114及磊晶P型汲極116的厚度降低約1%到約10%(例如，從約10Å到約9Å)。在其他實施例中，移除硬罩幕層1002-1006可能會使磊晶P型源極114及磊晶P型汲極116位於或低於基板102的表面。
雖然第4-13圖描述具有磊晶P型源極與磊晶P型汲極的P型金屬氧化物半導體裝置的製造方法，然而，此方法可以藉由改變裝置的摻雜特性而適用於N型金屬氧化物半導體裝置。舉例而言，N型金屬氧化物半導體裝置將具有磊晶N型源極與磊晶N型汲極。因此，此方法不會改變，而是改變摻質以適用於裝置的類型。
請參照第14圖，提供第4-13圖之方法的一些實施例的流程圖。
在步驟1402，形成隔離結構於基板中。基板包括N 井區域及P井區域。N井區域可為高電壓N型井，且P井區域可為高電壓P型井。隔離結構從基板的頂部表面延伸進入基板的內部。請參照，例如，第4圖。
在步驟1404，形成閘極層於基板上，閘極層可包括閘極介電質層及閘極電極層。此外，閘極罩幕沉積於閘極層上。請參照，例如，第5圖。
在步驟1406，藉由圖案化閘極層，以形成閘極。閘極包括閘極介電質及閘極電極。請參照，例如，第6圖。
在步驟1408，形成側壁間隔物於閘極的每一個側壁上。請參照，例如，第7圖。
在步驟1410，藉由斜角佈植，以形成P型輕摻雜擴散區域於閘極下方且位於N井區域中。在一些實施例中，P型輕摻雜擴散區域的一側壁對準於閘極。請參照，例如，第8圖。
在步驟1412，藉由離子佈植操作，以形成隔離P井及N+摻雜區域於第一N井區域中，並且形成N+摻雜區域於第二N井區域中。請參照，例如，第9圖。
在步驟1414，選擇性地沉積硬罩幕層於基板及閘極上。請參照，例如，第10圖。
在步驟1416，形成多邊源極凹孔於基板的N井區域中，且形成多邊汲極凹孔於基板的P井區域中。請參照，例如，第11圖。
在步驟1418，形成磊晶P型源極於多邊源極凹孔中，且形成磊晶P型汲極於多邊汲極凹孔中。請參照，例如，第12圖。
在步驟1420，移除硬罩幕層。請參照，例如，第13圖。
磊晶P型源極及磊晶P型汲極可有益於降低RDS(on)。
雖然在此所繪示及描述之第14圖的流程圖1400為一系列的動作或事件，然而，應可理解的是，在此所繪示的這些動作或事件的排序不被解釋為具有限制性的。舉例而言，一些動作可能會以不同的順序發生及/或與其他動作或事件同時發生，這些其他動作或事件可能是與在此所繪示及描述的這一些動作彼此獨立。此外，並非所有繪示的動作都需要實施於在此所描述的一或多個實施例中，且在此所描述的一或多個動作可實施於一或多個獨立的動作及/或階段中。
如上所述，本揭露之一些實施例提供一種具有磊晶源極與汲極的積體電路，其可降低閘極燒毀並提高開關速度，因而適合於高電壓之應用。此積體電路包括具有高電壓N型井高電壓P型井的半導體基板。此積體電路亦包括高電壓裝置位於該半導體基板之上。此高電壓裝置包括磊晶P型源極設置於高電壓N型井中，磊晶P型汲極設置於高電壓P型井中，以及閘極位於半導體基板之表面上之磊晶P型源極與磊晶P型汲極之間。
此外，本揭露之其他實施例提供一種具有磊晶源極與汲極的積體電路。此積體電路包括具有高電壓P型井與高電壓N型井的半導體基板。此積體電路亦包括高電壓裝置位於該半導體基板之上。此高電壓裝置包括磊晶N型源極設置於高 電壓P型井中，磊晶N型汲極設置於高電壓N型井中，以及閘極位於半導體基板之表面上之高電壓P型井與高電壓N型井之間。
此外，本揭露之其他實施例提供一種具有磊晶源極與汲極的積體電路之製造方法。此積體電路之製造方法包括形成複數層閘極層於基板之上。此基板具有高電壓N型井與高電壓P型井。圖案化上述複數層閘極層，以形成具有閘極介電質與閘極電極的閘極。形成複數個側壁間隙壁於閘極介電質與閘極電極之每一個側壁上。此積體電路之製造方法亦包括選擇性沉積複數個硬罩幕層於基板與閘極之上。進行斜角蝕刻，以形成多邊源極凹孔於高電壓N型井之中，且形成多邊汲極凹孔於高電壓P型井之中。多邊源極凹孔與多邊汲極凹孔具有實質上平面的複數個邊緣，且上述複數個邊緣在複數個角落相連接。形成磊晶P型源極於多邊源極凹孔之中，且形成磊晶P型汲極於多邊汲極凹孔之中。磊晶P型源極與磊晶P型汲極具有多邊形形狀。接著移除上述複數個硬罩幕層。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。

Claims (9)

  1. 一種積體電路，包括：一半導體基板，具有一高電壓N型井與一高電壓P型井；以及一高電壓裝置位於該半導體基板之上，其中該高電壓裝置包括一磊晶P型源極設置於該高電壓N型井中，一磊晶P型汲極設置於該高電壓P型井中，以及一閘極位於該半導體基板之一表面上之該磊晶P型源極與該磊晶P型汲極之間；其中該磊晶P型源極具有六個實質上平面的晶面，包括一底部晶面、一頂部晶面、具有兩個斜角晶面的一第一側、以及具有兩個斜角晶面的一第二側；其中該第一側包括：一第一上部晶面從該頂部晶面延伸至該高電壓N型井中；以及一第一下部晶面從該底部晶面延伸朝向該第一上部晶面，其中該第一上部晶面與該第一下部晶面交會於一第一點，該第一點低於該半導體基板之該表面。
  2. 如申請專利範圍第1項所述之積體電路，其中該磊晶P型源極與該磊晶P型汲極具有一多邊形形狀，且其中該多邊形是六邊形。
  3. 如申請專利範圍第1項所述之積體電路，其中該第二側包括：一第二上部晶面從該頂部晶面延伸至該高電壓P型井中；以及一第二下部晶面從該底部晶面延伸朝向該第二上部晶面，其中該第二上部晶面與該第二下部晶面交會於一第二點，該第二點低於該半導體基板之該表面，且其中該第一點與該第二點延伸至該半導體基板之該表面下方的一距離d1。
  4. 如申請專利範圍第3項所述之積體電路，其中該閘極包括一閘極介電質、一閘極電極以及複數個側壁間隙壁，其中該等側壁間隙壁被該閘極介電質和該閘極電極隔離，其中該第一點位於該等側壁間隙壁的一個側壁間隙壁之下。
  5. 如申請專利範圍第1項所述之積體電路，其中該磊晶P型源極延伸至高於該半導體基板之該表面。
  6. 一種積體電路，包括：一半導體基板，具有一高電壓P型井與一高電壓N型井；以及一高電壓裝置位於該半導體基板之上，其中該高電壓裝置包括一磊晶N型源極設置於該高電壓P型井中，一磊晶N型汲極設置於該高電壓N型井中，以及一閘極位於該半導體基板之一表面上之該高電壓P型井與該高電壓N型井之間；其中該磊晶N型源極具有六個實質上平面的晶面，包括一底部晶面、一頂部晶面、具有兩個斜角晶面的一第一側、以及具有兩個斜角晶面的一第二側；其中該第一側包括：一第一上部晶面從該頂部晶面延伸至該高電壓P型井中；以及一第一下部晶面從該底部晶面延伸朝向該第一上部晶面，其中該第一上部晶面與該第一下部晶面交會於一第一點，該第一點低於該高電壓P型井之一最上方表面。
  7. 如申請專利範圍第6項所述之積體電路，其中該磊晶N型源極與該磊晶N型汲極具有一多邊形形狀，且其中該多邊形是六邊形。
  8. 一種積體電路之製造方法，包括：形成複數層閘極層於一基板之上，其中該基板具有一高電壓N型井與一高電壓P型井；圖案化該等閘極層，以形成具有一閘極介電質與一閘極電極的一閘極；形成複數個側壁間隙壁於該閘極介電質與該閘極電極之每一個側壁上；選擇性沉積複數個硬罩幕層於該基板與該閘極之上；進行一斜角蝕刻，以形成一多邊源極凹孔於該高電壓N型井之中，且形成一多邊汲極凹孔於該高電壓P型井之中，其中該多邊源極凹孔與該多邊汲極凹孔具有實質上平面的複數個邊緣，且該等邊緣在複數個角落相連接；形成一磊晶P型源極於該多邊源極凹孔之中，且形成一磊晶P型汲極於該多邊汲極凹孔之中，其中該磊晶P型源極與該磊晶P型汲極具有一多邊形形狀；以及移除該等硬罩幕層。
  9. 如申請專利範圍第8項所述之積體電路之製造方法，其中該磊晶P型源極與該磊晶P型汲極各自具有六個實質上平面的晶面，包括一底部晶面、一頂部晶面、具有兩個斜角晶面的一第一側、以及具有兩個斜角晶面的一第二側，且其中該第一側的該兩個斜角晶面交會於一第一點，且該第二側的該兩個斜角晶面交會於一第二點，且其中該第一點與該第二點位於至高於該半導體基板的一上表面下方的一距離d1。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189565B2 (en) 2020-02-19 2021-11-30 Nanya Technology Corporation Semiconductor device with programmable anti-fuse feature and method for fabricating the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI706532B (zh) * 2019-04-03 2020-10-01 世界先進積體電路股份有限公司 半導體裝置
CN111834284B (zh) * 2019-04-17 2024-08-27 世界先进积体电路股份有限公司 半导体装置
US10910469B2 (en) 2019-06-07 2021-02-02 Vanguard International Semiconductor Corporation Semiconductor device with conducting structure for reducing parasitic capacitance and improving RC delay
US11387242B2 (en) * 2020-03-03 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory (NVM) cell structure to increase reliability
DE102020134570A1 (de) * 2020-05-27 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201436215A (zh) * 2013-03-13 2014-09-16 Macronix Int Co Ltd 於崩潰時具有減少漏電流之半導體裝置及其製造方法
TW201608716A (zh) * 2014-08-20 2016-03-01 台灣積體電路製造股份有限公司 具有鰭片嵌入隔離區之多閘極裝置結構及其製作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7372083B2 (en) * 2005-08-09 2008-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection
US7459382B2 (en) * 2006-03-24 2008-12-02 International Business Machines Corporation Field effect device with reduced thickness gate
US20080073745A1 (en) * 2006-09-25 2008-03-27 Chien-Shao Tang High-voltage MOS device improvement by forming implantation regions
US7718494B2 (en) * 2007-04-09 2010-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
US7816744B2 (en) 2008-07-09 2010-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gate electrodes of HVMOS devices having non-uniform doping concentrations
US8828813B2 (en) * 2012-04-13 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement channels
US10170554B2 (en) * 2014-12-26 2019-01-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201436215A (zh) * 2013-03-13 2014-09-16 Macronix Int Co Ltd 於崩潰時具有減少漏電流之半導體裝置及其製造方法
TW201608716A (zh) * 2014-08-20 2016-03-01 台灣積體電路製造股份有限公司 具有鰭片嵌入隔離區之多閘極裝置結構及其製作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189565B2 (en) 2020-02-19 2021-11-30 Nanya Technology Corporation Semiconductor device with programmable anti-fuse feature and method for fabricating the same
US11735520B2 (en) 2020-02-19 2023-08-22 Nanya Technology Corporation Method for fabricating semiconductor device with programmable anti-fuse feature

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KR102136178B1 (ko) 2020-07-23
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