CN114434729A - 半导体装置用的框体的制造方法 - Google Patents

半导体装置用的框体的制造方法 Download PDF

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Publication number
CN114434729A
CN114434729A CN202111240502.8A CN202111240502A CN114434729A CN 114434729 A CN114434729 A CN 114434729A CN 202111240502 A CN202111240502 A CN 202111240502A CN 114434729 A CN114434729 A CN 114434729A
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China
Prior art keywords
insert
housing
hole
semiconductor device
lower mold
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CN202111240502.8A
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English (en)
Inventor
益本宽之
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN114434729A publication Critical patent/CN114434729A/zh
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B29C45/17—Component parts, details or accessories; Auxiliary operations
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    • B29C45/2602—Mould construction elements
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    • B29C45/14426—Coating the end of wire-like or rod-like or cable-like or blade-like or belt-like articles
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    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
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Abstract

提供与对框体所具有的端子进行配置的自由度高的嵌入成形有关的技术。半导体装置用的框体的制造方法是对框体进行制造的方法，该框体具有框和与框一起嵌入成形的多个端子，该框体与半导体元件一起设置于半导体装置。端子具有第1部分和作为与半导体元件的连接对象的第2部分。该方法具有以下工序：第1工序，向设置有成为供第1部分插入的对象的多个孔的下模，配置具有将至少一个孔覆盖的第3部分的嵌块；第2工序，针对配置有嵌块的下模，向未被第3部分覆盖的孔插入第1部分，配置端子；第3工序，向配置有嵌块以及端子的下模配置上模；以及第4工序，在第3工序之后被执行，使用下模和上模进行树脂成形而得到框体。

Description

半导体装置用的框体的制造方法
技术领域
本发明涉及半导体装置用的框体的制造方法。
背景技术
半导体装置的封装件是公知的，该半导体装置具有基座板、载置于基座板之上的半导体搭载基板、作为与基座板固接的框体的母壳体、固定部件、螺钉端子和引脚端子(例如参照下述的专利文献1)。
在专利文献1中例示了如下技术：母壳体具有开口；在构成开口的周缘使用固定部件将螺钉端子与引脚端子固定；通过多个固定位置之中的任意的固定位置的固定部件对螺钉端子以及引脚端子进行固定；通过固定位置的变更而构成各种封装件；以及可以使用外嵌成形来制造螺钉端子。
还公知下述技术，即，通过嵌入成形将电绝缘性的树脂材料和与功率半导体芯片的电极电连接的外部端子进行一体化，由此形成具有中央开口的外围壳体(例如参照专利文献2)。
专利文献1：日本特开2008-10656号公报
专利文献2：日本特开2014-103284号公报
嵌入成形与外嵌成形相比，不容易使水分向半导体装置的内部侵入，耐吸湿性的可靠性高。就以往的嵌入成形而言，对端子进行配置的自由度小。在以往的嵌入成形中，在针对端子采用多种配置时，准备多种模具。从少量地生成其它品种的观点来看，该准备是不利的。
发明内容
本发明提供与对框体所具有的端子进行配置的自由度高的嵌入成形有关的技术。
本发明涉及的半导体装置用的框体的制造方法是对框体进行制造的方法，该框体具有框和与所述框一起嵌入成形的多个端子，该框体与半导体元件一起设置于半导体装置。所述端子具有第1部分和作为与所述半导体元件的连接对象的第2部分。该方法具有以下工序：第1工序，向设置有成为供所述第1部分插入的对象的多个孔的下模，配置具有将至少一个所述孔覆盖的第3部分的嵌块；第2工序，针对配置有所述嵌块的所述下模，向未被所述第3部分覆盖的所述孔插入所述第1部分，配置所述端子；第3工序，向配置有所述嵌块以及所述端子的所述下模配置上模；以及第4工序，在所述第3工序之后被执行，使用所述下模和所述上模进行树脂成形而得到所述框体。
发明的效果
本发明涉及的半导体装置用的框体的制造方法有助于对框体所具有的端子进行配置的自由度高的嵌入成形。
附图说明
图1是例示通过本发明涉及的制造方法得到的框体的斜视图。
图2是例示通过本发明涉及的制造方法得到的框体的俯视图。
图3是例示通过本发明涉及的制造方法得到的框体的侧视图。
图4是将通过本发明涉及的制造方法得到的框体的一部分放大地示出的图。
图5是例示框体的制造所采用的下模的俯视图。
图6是局部地示出下模的斜视图。
图7是例示框体的制造所采用的上模的俯视图。
图8是例示下模和嵌块的俯视图。
图9是局部地示出下模和嵌块的斜视图。
图10是例示嵌块的俯视图。
图11是例示嵌块的侧视图。
图12是例示下模、嵌块和端子的俯视图。
图13是局部地示出下模、嵌块和端子的斜视图。
图14是例示一个端子的斜视图。
图15是例示端子在框体中的配置的斜视图。
图16是例示框体的制造工序的流程图。
图17是局部地示出嵌块和下模的俯视图。
图18是例示半导体装置的剖视图。
图19是例示半导体装置的制造工序的流程图。
图20是例示能够对下模进行收容的下模的斜视图。
图21是例示配置了端子以及嵌块的状态的下模和收容了该状态的下模后的状态的下模的斜视图。
图22是例示端子、嵌块以及下模的俯视图。
图23是例示框体的其它制造工序的流程图。
具体实施方式
＜形状的说明＞
图1是例示通过本发明涉及的制造方法得到的框体100的斜视图。图2是例示框体100的俯视图。图3是例示框体100的侧视图。
框体100具有框1和多个端子2。端子2与框1一起嵌入成形，得到框体100。
框1的材料是绝缘性树脂。框1具有壁11和底12。壁11呈环状。端子2各自具有部分21和部分22。端子2各自在将部分21与部分22连结的部位处弯折。在框体100处，部分21彼此平行地配置。
为了便于以下的说明，引入方向X、Y、Z。在从部分22进行观察时部分21的延伸方向采用方向Z。例如部分22从部分21沿与方向Z垂直的方向延伸。壁11所呈现的环状在沿方向Z观察时，具有与方向X平行的两条边和与方向Y平行的两条边。方向X、Y彼此正交，均与方向Z正交。方向X、Y、Z对应于所谓的右手系的坐标系。
底12在沿方向Z观察时呈环状。在底12弯折的部位开设有孔14。孔14沿方向Z将底12贯通。在孔14中贯通有紧固件例如螺母。该紧固件将框体100紧固至后述的散热板8(参照图18)。
底12具有与方向Z平行的内表面10。内表面10在沿方向Z观察时呈矩形。壁11相对于底12而在方向Z侧沿方向Z延伸。壁11在沿方向Z观察时比内表面10更靠外侧，与孔14相比位于内侧。在壁11处相邻的两条边的边界与两条边相比向内表面10侧凹陷。在孔14的附近，在壁11处在方向Z侧开设有孔15。孔15被用于将未图示的印刷电路基板向框体100进行螺钉紧固。
部分22在底12的方向Z侧的面露出。部分22的前端在内表面10露出。部分21的前端在壁11的方向Z侧的面露出。
壁11具有在方向Z侧开口的凹部13。端子2不配置于凹部13，因此，部分21没有在凹部13露出。
图4是将框体100的一部分放大地示出的图。图4将图1中的范围A放大地示出。为了便于之后的说明，引入壁11的厚度d、凹部13的深度h、距离L、间距t。
深度h是凹部13的方向Z侧的面与未设置凹部13的壁11的方向Z侧的面之间的距离。距离L是凹部13与最靠近凹部13的部分21的位置之间的距离。间距t是在不夹着凹部13的状态下相邻地配置的一对部分21彼此的间隔。
＜制造工序的说明＞
图5是表示框体100的制造所使用的下模5的俯视图。图6是局部地示出对下模5的斜视图。在图6中，图5中的位置BB处的剖面显现在纸面近端侧。
在图5以及图6中一并记述的方向X、Y、Z对应于在示出框体100的图1至图4中一并记述的方向X、Y、Z。
下模5具有彼此平行的上表面58、59。在图5以及图6中，上表面58、59与方向Z垂直。下模5具有彼此平行的柱54、55。柱54、55均沿方向Z延伸。
如果不考虑制造上的公差，则柱54的与方向Z相反侧的端面(以下暂称为“上端面”)、柱55的上端面和上表面58、59共面。如果不考虑制造上的公差，则在方向Z，柱54的上端面、柱55的上端面、上表面58的位置和上表面59的位置是一致的。
下模5具有上表面52、56。例如上表面52、56均与上表面58、59平行。上表面52位于比上表面58、59更靠方向Z侧处。上表面56位于比上表面52更靠方向Z侧处。
下模5具有侧面50、51、57。例如侧面50、51、57均与方向Z平行。
侧面50是将上表面59、52连结的环状的面。能够看做由上表面59和侧面50构成相对于上表面52而向与方向Z相反的方向(以下也称为“方向(-Z)”)凸出的凸部5A。
侧面51是将上表面52、56连结的环状的面。侧面57是将上表面58、56连结的面。能够看做由侧面51、57和上表面56构成相对于上表面58、59而向方向Z凹陷、在与方向Z相反侧开口的凹部5B。
在上表面56处开设、沿侧面51配置的多个孔53贯穿下模5。孔53沿方向Z延伸。孔53没有将下模5贯通。如果不考虑制造上的公差，相邻的一对孔53彼此的间隔与间距t一致。孔53是供部分21插入的对象。
图7是例示上模6的俯视图。上模6与下模5一起被用于框体100的制造。在图7中一并记述的方向X、Y、Z对应于在示出框体100的图1至图4中一并记述的方向X、Y、Z。
上模6具有平坦的面64、68、69。如果不考虑制造上的公差，面64、68、69的方向Z上的位置一致。在俯视观察时，这里，在沿方向(-Z)观察时，面69被面68包围。在面68、69之间形成与面68、69相比向方向(-Z)侧凹陷的环状的凹部60。面64能够看做在凹部60处朝向方向Z而凸出的凸部在方向Z侧显现出的面。凹部60能够看做朝向方向Z而开口。
在使用了上模6和下模5的成形时，柱54与面64抵接，上表面59与面69抵接，上表面58与面68抵接。
在成形中导入的树脂是在与凹部60相比更靠方向Z侧处导入的。但是，为了避免附图的复杂，在上模6或者下模5中省略用于注入树脂的孔(浇口)的绘制。在与上表面59对应的位置不形成树脂，得到反映出上表面52的形状的底12，该底12具有反映出侧面50的形状的内表面10。不向柱54、55导入树脂。由此，得到孔14、15。
图8是例示下模5和嵌块3的俯视图。嵌块3也被用于框体100的制造。图9是局部地示出下模5和嵌块3的斜视图。在图9中，图8中的位置CC处的剖面显现在纸面近端侧。在图8、图9中一并记述的方向X、Y、Z对应于在示出框体100的图1至图4中一并记述的方向X、Y、Z。
图10是表示嵌块3的俯视图。图11是表示嵌块3的侧视图。在图10、图11中一并记述的方向Z对应于在示出框体100的图1至图4中一并记述的方向Z。
嵌块3嵌入至凹部5B。图10以及图11示出在图8所示的状态下配置的嵌块3。嵌块3具有底面33、上表面34、35、侧面36、37、38、端面30、39。嵌块3具有部分31和部分32。部分31与部分32连结。
底面33是在部分31和部分32都显现出的平坦面。在嵌块3被嵌入至凹部5B时，底面33与上表面56抵接。
上表面34是在部分32处显现出的平坦面。在嵌块3被嵌入至凹部5B时，上表面34位于与上表面58、59相同的平面。
上表面35是在部分31处显现出的平坦面，例如与上表面34平行。上表面35与底面33之间的距离能够看做是部分31的沿方向Z的长度(下面，也简称为部分31的“厚度”)。如果不考虑制造上的公差，则在上表面34、35平行时，部分31的厚度H与深度h一致。
侧面36是在部分31处显现出的平坦面。在嵌块3被嵌入至凹部5B时，侧面36与侧面51抵接。
侧面37是在部分32处显现出的平坦面，例如与侧面36平行。侧面36与侧面37之间的距离能够看做是部分31从部分32凸出的长度(以下，也简称为部分31的“凸出长度”)。如果不考虑制造上的公差，则在侧面36、37平行时，部分31的凸出长度D与厚度d一致。
侧面38是在部分32处显现出的平坦面，例如与侧面36平行。在嵌块3被嵌入至凹部5B时，侧面38与侧面57抵接。
端面39是在部分32处显现出的平坦面。端面30是在部分31处显现出的平坦面。在嵌块3被嵌入至凹部5B时，端面39与侧面57抵接。端面39、30例如均与底面33、上表面34、35、侧面36、37、38都垂直。例如部分31以及部分32均呈长方体的形状。
在图10以及图11中，例示了部分31以及部分32均呈长方体的形状的情况。在图11中，示出部分31的厚度H和部分31的凸出长度D。
部分31在与方向Z相反侧将一个或者大于或等于两个孔53覆盖。部分31与侧面51、上表面56均接触。
在嵌块3被嵌入至凹部5B时，侧面38以及端面39与侧面57抵接，底面33与上表面56抵接，侧面36与侧面51抵接，部分32具有将部分31的位置固定的功能。在一个嵌块3具有多个部分31时，能够看做部分32具有将这些部分31连结起来的功能。
图12以及图13例示出在向下模5配置了嵌块3之后，配置了端子2的状态。图12是例示下模5、嵌块3和端子2的俯视图。图13是局部地示出下模5、嵌块3和端子2的斜视图。在图13中，图12中的位置DD处的剖面显现在纸面近端侧。在图12、图13中一并记述的方向X、Y、Z对应于在示出框体100的图1至图4中一并记述的方向X、Y、Z。
图14是例示一个端子2的斜视图。在图14中一并记述的方向Z对应于在示出框体100的图1至图4中一并记述的方向Z。在孔53中的未被部分31覆盖的孔53中插入端子2，更具体而言，插入部分21。
在成形时，不仅是部分31自身所处的区域，在被部分31覆盖的孔53中也不导入树脂。就与未配置端子2的位置相应的孔53而言，通过部分31阻止树脂的导入。该阻止有助于避免反映出该孔53的形状的、不需要的树脂的成形。得到具有反映出部分31的形状的凹部13的框体100。
图15是例示端子2在框体100中的配置的斜视图。在图15中一并记述的方向Z对应于在示出框体100的图1至图4中一并记述的方向Z。在图15中，为了容易观察端子2的配置姿态，被壁11掩埋而隐藏的部分的端子2的形状由作为隐藏线的虚线描绘。
使上模6与图12、图13所示的状态的下模5、嵌块3和端子2对位，通过公知的嵌入成形而得到端子2和框1一体化的框体100。
图16是例示框体100的制造工序的流程图。能够看做该流程图表示框体100的制造方法。
步骤S1是在下模5配置嵌块3的工序。具体地说，步骤S1是向凹部5B嵌入嵌块3的工序。在步骤S1完成之后，在步骤S2中向配置有嵌块3的下模5配置端子2。具体地说，向未被部分31覆盖的孔53插入部分21(参照图8)。例如部分22与上表面52抵接。在这种情况下，在得到的框体100处，部分22在底12的方向Z侧的面露出。
在步骤S2完成之后，在步骤S3中向配置有嵌块3以及端子2的下模5配置上模6。具体地说，面64、68、69分别与柱54、上表面58、59抵接。
在步骤S3完成之后，在步骤S4中，进行使用了下模5和上模6的树脂成形。具体地说，步骤S4是向由下模5和上模6夹着的空间导入树脂的工序。由此得到框体100。在步骤S4完成之后，在步骤S5中，将上模6从下模5以及嵌块3取下。在步骤S5完成之后，在步骤S6中，将框体100从下模5以及嵌块3取下。在步骤S6完成之后，在步骤S7中，将嵌块3从下模5取下(参照图5)。
为了得到端子2的配置不同的框体100，采用不同形状的嵌块3。具体地说，采用部分31的形状不同的嵌块3。更具体而言，采用具有将孔53覆盖的部位不同的部分31的嵌块3。使用不同的嵌块3，使用共通的下模5，得到具有在不同的位置配置的端子2的框体100。通过采用部分31的形状不同的多种嵌块3，从而使下模5的形状共通化，并制造端子2的配置不同的框体100。
在例如图5所例示的下模5处，存在8个与方向Y平行地并排配置的孔53。并且，在图1所例示的框体100处，存在6个与方向Y平行地并排配置的端子2，3个端子2的端子组夹着凹部13而配置。为了得到这样的端子2的配置，如图8所示，采用具有将与方向Y平行地并排配置的孔53的中央的2个覆盖的部分31的嵌块3。
例如设想如下框体100：存在4个与方向Y平行地并排配置的端子2，2个端子2的端子组夹着凹部13而配置。为了得到该框体100，采用具有将与方向Y平行地并排配置的孔53的中央的4个覆盖的部分31的嵌块3。对与方向X平行地并排配置的端子2而言，这样的部分31不同的嵌块3的使用也是相同的。
在对端子2的配置并无不同的多个框体100进行制造时，无需替换嵌块3。在这种情况下，在执行一次步骤S1～S7而制造出框体100之后，其它框体100通过反复执行步骤S2～S6而进行制造。
＜对各种尺寸的说明＞
在嵌块3被嵌入至凹部5B时，端面30位于被部分31覆盖的第1孔53与未被该部分31覆盖的第2孔53(其中，第1孔53与第2孔53相邻)之间。凹部13的形状反映出部分31的形状，因而，如果不考虑制造上的公差，则端面30与第2孔53之间的距离与距离L一致(参照图9)。
距离L越短，则孔53的排列方向上的部分31的长度越长。部分31的长度长有助于提高部分31的刚性。部分31的刚性高有助于减小进行嵌入成形时的嵌块3的变形。进行嵌入成形时的嵌块3的变形小既有助于抑制凹部13以及凹部13周围的壁11处的毛刺的产生，也有助于抑制非预期的形状的产生。
例如优选距离L小于或等于间距t的一半(参照图4、图6)。如果由数学式表示，则优选L≤t/2。
例如作为在工业用半导体的领域中利用的半导体装置，大量制作间距t为3.81mm、端子2的宽度m(参照图15)为1.15mm的产品。在这种情况下，如果设为L＝t/2，则在从端子2至凹部13的端部为止，壁11存在的距离n(参照图15)为3.81/2-1.15/2＝1.33mm。
图17是局部地示出具有将3个孔53覆盖的部分31的嵌块3、下模5的俯视图。在图17中一并记述未被部分31覆盖的孔53中的部分21所接触的部分与端面30之间的距离N。如果不考虑制造上的公差，则距离n、N一致。
尽管也依赖于壁11所使用的树脂，但如果距离N小于1mm，则需要提高成形时的压力。如果成形时的压力高，则例如产生以下情形的可能性提高，即，毛刺的产生、树脂进入嵌块3与下模5之间的间隙。如果考虑兼顾嵌块3的刚性和成形性这两者，则优选L≤t/2的关系。但是，优选距离N大于或等于0.5mm，因而优选距离L大于或等于1.0mm。
如果不考虑制造上的公差，则在上表面34、35平行时，深度h与部分31的厚度H一致。如果不考虑制造上的公差，则在侧面36、37平行时，厚度d与部分31的凸出长度D一致(参照图9)。
凸出长度D相对于厚度H的比率小有助于提高部分31的刚性。部分31的刚性高有助于减小进行嵌入成形时的嵌块3的变形。进行嵌入成形时的嵌块3的变形小有助于抑制凹部13以及凹部13周围的壁11处的毛刺的产生。
例如优选凸出长度D小于或等于厚度H的两倍。如果由数学式表示，则优选D/2≤H。不考虑制造上的公差，例如优选厚度d小于或等于深度h的两倍。如果由数学式表示，则优选d/2≤h。
例如作为在工业用半导体的领域中利用的半导体装置，大量制作厚度d为2～3mm的产品。从制造嵌块3的观点来看，优选厚度H大于或等于1mm。通过如上所述将厚度d的最小值设想为2mm，优选厚度H大于或等于1mm，从而优选d/2≤h或者D/2≤H的关系。
＜向半导体装置的应用＞
图18是例示具有框体100的半导体装置200的剖视图。例示了框体100被用于半导体装置200的情况。图18中的框体100例如作为图2所示的位置EE处的剖面而显现出来。为了使结构容易理解，后述的导线W也在图18中示出。
半导体装置200具有框体100、散热板8、半导体电路基板7、封装材料75、盖76和多根导线W。框体100与散热板8通过将孔14(参照图1、图2)贯通的紧固件(未图示)而连接。散热板8由金属(例如，铜)构成。为了避免附图的复杂，仅对框体100所具有的端子2标注阴影。
半导体电路基板7具有导电部71、72a、72b、基板73、接合材料70、74和至少一个半导体元件Q(在图18中例示了多个半导体元件Q)。例如在半导体电路基板7形成利用了半导体元件Q的半导体电路。
基板73具有绝缘性。基板73经由导电部71和接合材料70而与散热板8连接。基板73例如由陶瓷构成。接合材料70例如是焊料。
导电部71、72a、72b各自例如由铜构成。导电部71在与基板73相比更靠近散热板8侧配置于基板73。导电部71经由接合材料70而与散热板8接合。导电部72a、72b在与基板73相比更远离散热板8侧配置于基板73。
半导体元件Q例如是半导体芯片，更具体而言，例如是电力用半导体元件。该电力用半导体元件例如是开关元件，以绝缘栅型双极晶体管以及场效应晶体管进行例示。电力用半导体元件具有用于控制其动作的控制端子。就设置多个作为电力用半导体元件的半导体元件Q的半导体装置200而言，存在大量用于单独地控制半导体元件Q的控制端子。框体100被用于半导体装置200这一做法适于具有作为电力用半导体元件的半导体元件Q、谋求控制端子的配置的高自由度的半导体装置200。
半导体元件Q各自被安装于基板73。在半导体元件Q各自设置有经由接合材料74而与导电部72a连接的背面电极(未图示)。半导体元件Q各自的背面电极经由接合材料74而与导电部72a电连接。接合材料74例如是焊料。在各个半导体元件Q，在远离基板73侧的面设置有表面电极(未图示)。安装于基板73的半导体元件Q的个数不限定于图示的2个，也可以是1个或者大于或等于3个。
端子2在其部分22处与半导体电路基板7电连接。具体地说，部分22例如通过导线W与半导体元件Q的表面电极连接。部分22例如通过导线W与导电部72b连接。半导体元件Q与框体100一起设置于半导体装置200，部分22是与半导体元件Q的连接对象。
导线W例如将多个半导体元件Q的表面电极彼此连接。导线W例如将半导体元件Q的表面电极与导电部72b连接。导线W具有导电性，例如由金属构成。
封装材料75至少将半导体电路基板7和部分22覆盖而填充被散热板8和框体100包围的区域。在图18中例示了封装材料75也将导线W覆盖的情况。盖76与壁11抵接，盖76从与散热板8相反侧将封装材料75覆盖。
图19是例示半导体装置200的制造工序的流程图。能够看做该流程图表示半导体装置200的制造方法。步骤T1是将散热板8安装于框体100的工序。例如通过使用将孔14贯通的紧固件而实现步骤T1的处理。
在步骤T1结束之后，执行步骤T2。步骤T2是将半导体电路基板7安装于散热板8的工序。例如通过使用接合材料70将半导体电路基板7所具有的导电部71与散热板8连接而实现步骤T2的处理。
在步骤T2结束之后，执行步骤T3。步骤T3是将部分22与半导体电路基板7进行连接的工序。例如通过使用导线W将半导体元件Q与部分22连接、将导电部72b与部分22连接，从而实现步骤T3的处理。
在步骤T3结束之后，执行步骤T4。步骤T4是使用封装材料75将半导体电路基板7和部分22进行封装的工序。例如通过封装材料75将半导体电路基板7和部分22覆盖而填充被散热板8和框体100包围的区域，从而实现步骤T4的处理。在步骤T4中，也可以如图18所图示那样，将导线W封装。
在步骤T4结束之后，在步骤T5中，在框体100安装盖76。例如，盖76与壁11抵接，盖76从与散热板8相反侧将封装材料75覆盖。
步骤T5的执行结束，由此得到具有框体100、散热板8、半导体电路基板7、封装材料75、盖76和多根导线W的半导体装置200。
在半导体装置200被安装于印刷电路基板时，该印刷电路基板被向半导体装置200所具有的框体100的孔15通过螺钉进行紧固。
＜变形＞
使用了能够对下模5进行收容的其它下模的树脂成形有助于嵌块3的容易更换。图20是例示能够对下模5进行收容的下模9的斜视图。
图21是例示配置有端子2以及嵌块3的状态的下模5和收容了该状态的下模5后的状态的下模9的斜视图。图22是例示该状态的端子2、嵌块3以及下模5、9的俯视图。在图20至图22中一并记述的方向X、Y、Z对应于在示出框体100的图1至图4中一并记述的方向X、Y、Z。
下模9在其方向(-Z)侧具有平坦的面98和凹部90。凹部90朝向方向(-Z)而开口。在沿方向Z观察时，凹部90被面98包围。
凹部90呈能够对下模5进行收容的形状。在下模5被收容于凹部90时，凹部90以使得下模5相对于下模9的方向X、Y上的相对移动受到抑制的程度对下模5进行保持。
如果不考虑制造上的公差，则在下模5被收容于凹部90时，面98的方向Z上的位置与方向Z上的柱54的上端面、柱55的上端面、上表面58的位置、上表面59的位置一致。
例如下模5是长方体。如果不考虑制造上的公差，则下模5的方向Z上的长度与凹部90的方向Z上的深度一致，下模5的方向X上的长度与凹部90的方向X上的内尺寸一致，下模5的方向Y上的长度与凹部90的方向Y上的内尺寸一致。
图23是例示框体100的其它制造工序的流程图。这里“其它”表示与图16的流程图不同的变形涉及的流程图。
图23所示的流程图示出相对于图16所示的流程图而追加了步骤S8、S9的结构。步骤S8是在步骤S1、S2之间执行的工序。步骤S9是在步骤S6、S7之间执行的工序。
在步骤S8中，将执行步骤S1而配置有嵌块3的下模5配置于下模9。具体地说，通过向凹部90收容下模5，从而实现步骤S8的处理。
在执行了步骤S8之后，如使用图16而说明的那样，执行步骤S2～S6。在该变形中，优选上模6不仅与下模5抵接，也与下模9抵接。例如优选上模6的面68以在执行步骤S3时与下模9的面98中的至少凹部90的周围而环状地抵接的程度，沿方向X、Y而扩展。
在步骤S9中，将执行步骤S6而将框体100取下后的配置有嵌块3的状态的下模5从下模9取下。具体地说，通过将该状态的下模5从凹部90取下而实现步骤S9的处理。
在执行了步骤S9之后，在步骤S7中将嵌块3从下模5取下。
通过使用这样的下模9，从而在使嵌块3的配置改变而制造多种框体100时，不需要从进行嵌入成形的成形机将下模9取下。这在制造其它品种的框体100的情况下，会缩短对嵌块3的配置进行更换的时间。该缩短有助于其它品种的框体100的高效化。
上述实施方式能够适当地变形、省略。
标号的说明
1框，2端子，5、9下模，6上模，21、22、31、32部分，30端面，100框体，200半导体装置，S1～S8步骤(工序)，D凸出长度，H厚度，L距离，Q半导体元件，t间距(间隔)。

Claims (4)

1.一种半导体装置用的框体的制造方法，其制造框体，该框体具有框和与所述框一起嵌入成形的多个端子，该框体与半导体元件一起设置于半导体装置，
所述端子具有第1部分和作为与所述半导体元件的连接对象的第2部分，
该半导体装置用的框体的制造方法具有以下工序：
第1工序，向设置有成为供所述第1部分插入的对象的多个孔的下模，配置具有将至少一个所述孔覆盖的第3部分的嵌块；
第2工序，针对配置有所述嵌块的所述下模，向未被所述第3部分覆盖的所述孔插入所述第1部分，配置所述端子；
第3工序，向配置有所述嵌块以及所述端子的所述下模配置上模；以及
第4工序，在所述第3工序之后被执行，使用所述下模和所述上模进行树脂成形而得到所述框体。
2.根据权利要求1所述的半导体装置用的框体的制造方法，其中，
在执行了所述第1工序的状态下，所述第3部分的端面位于被所述第3部分覆盖的第1所述孔和与所述第1所述孔相邻且未被所述第3部分覆盖的第2所述孔之间，
所述端面与所述第2所述孔之间的距离小于或等于所述第1所述孔与所述第2所述孔之间的间隔的一半。
3.根据权利要求1或2所述的半导体装置用的框体的制造方法，其中，
所述嵌块还具有将多个所述第3部分连结的第4部分，
所述第3部分从所述第4部分凸出的长度小于或等于沿所述孔的延伸方向的所述第3部分的长度的两倍。
4.根据权利要求1至3中任一项所述的半导体装置用的框体的制造方法，其还具有以下工序：
第5工序，在所述第4工序之后被执行，将所述上模从所述下模以及所述嵌块取下；
第6工序，在所述第5工序之后被执行，将所述框体从所述下模以及所述嵌块取下；
第7工序，在所述第6工序之后被执行，将所述嵌块从所述下模取下；
第8工序，在所述第1工序与所述第2工序之间被执行，将所述下模配置于其它下模；以及
第9工序，在所述第6工序与所述第7工序之间被执行，将所述下模从所述其它下模取下。
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