CN1142588C - 提供双功函数掺杂的方法及保护绝缘帽盖 - Google Patents
提供双功函数掺杂的方法及保护绝缘帽盖 Download PDFInfo
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Abstract
一种提供双功函数掺杂和无边界阵列扩散接触的方法,该方法包括:提供半导体衬底、栅绝缘体、栅绝缘体上的导体、导体上的绝缘帽盖、及一部分所说导体和所说绝缘帽盖的侧壁上的绝缘间隔层。该方法还包括用第一导电类型的掺杂剂,掺杂部分所说半导体衬底和所说导体,用第二导电类型的掺杂剂掺杂其余部分。可以退火所说导体,使所说第一和第二导电类型的掺杂剂分布于所说各导体中。
Description
本发明一般涉及提供双功函数掺杂的方法,特别涉及提供栅结构阵列,从而使某些栅结构为P+掺杂,另一些栅结构为N+掺杂。本发明尤其适用于提供既包括DRAM又包括逻辑电路的结构。
近些年来,在用集成电路芯片技术增大电路密度方面取得了巨大进步。在集成电路芯片上设置显著增大数量的器件和电路的能力进而产生了在一个集成电路芯片上引入或集成附加系统功能的提高的要求。具体说,存在着对将存储电路和逻辑电路结合在一起置于同一集成电路芯片上的提高的要求。
在制造动态随机存取存储(DRAM)电路中,重点在电路密度及其降低成本。另一方面,在制造逻辑电路时,重点在形成更快速度工作的电路。因此,对双功函数的这种要求产生了制造工艺复杂和成本较高方面的问题。例如,使用容易用具有单一类型(例如一般为N+型)栅功函数的工艺实现的自对准接触(无边界位线接触),可以实现存储电路密度的提高。在形成DRAM时,采用埋置沟道P型金属氧化物半导体(PMOSFET),是由于这样做允许在整个制造工艺中使用单一功函数栅导体N+。于是很大程度上节约了制造DRAM的成本,但代价是生产很差性能的PMOSFET。另一方面,逻辑电路需要P+和N+栅MOSFET,以实现必要的开关速度。对于合并逻辑和DRAM产品来说,特别希望P+和N+栅导体器件。
高性能的逻辑要求使用N+和P+掺杂栅导体。尽管目前实际的高性能逻辑工艺提供了双功函数栅导体,但由于密度的要求没有采用绝缘栅帽盖,因此需要扩散相对栅导体无边界的接触,它们对速度来说第二重要。在13 DRAM中,与栅导体自对准的绝缘帽盖是形成相对于字线无边界的位线接触的关键。需要无边界接触实现最高密度的存储单元布局。然而,性能价格比高的DRAM工艺只采用单一N+多晶硅栅导体。所以,目前还没有从经济角度出发具有吸引力的提供双功函数栅掺杂和能实现无边界扩散接触的工艺。
考虑到常规技术的上述和其它问题,本发明的目的在于提供双功函数掺杂栅导体,包括自对准绝缘帽盖。
本发明另一目的是提供双功函数掺杂。可以包括一种形成双功函数掺杂的方法,该方法包括:提供半导体衬底、所说半导体衬底上的栅绝缘层、栅绝缘层上的未掺杂多晶硅层、所说未掺杂多晶硅层上的导电硅化物层及绝缘帽盖;腐蚀部分所说硅化物层和部分所说绝缘帽盖以形成局部栅导体叠层;在所说绝缘帽盖和所说硅化物层的侧壁上提供包括间隔材料的绝缘间隔层;腐蚀所说未掺杂多晶硅层的未被间隔材料覆盖的部分;去掉间隔材料,使所说未掺杂多晶硅层包括用于形成不同导电类型栅导体的第一和第二暴露部分;用第一导电类型的掺杂剂,掺杂所说多晶硅层的第一暴露部分;用第二导电类型的掺杂剂,掺杂所说多晶硅层的第二暴露部分;退火多晶硅层,使所说多晶硅层的其余部分被所说第一和第二导电类型的掺杂剂掺杂。
半导体衬底的某些部分可以对应于源和漏接触区。该方法还可以包括使衬底外围区的源和漏区延伸到至少退火导体之下的区。该方法还包括形成阵列区的源和漏。
本发明再一目的是满足双功函数的要求,选择性给栅导体施加P+或N+掺杂,同时在栅导体上形成自对准绝缘帽盖。
在以下结合公开了本发明的优选实施例的附图的详细介绍中,本发明的其它目的、优点和突出特点将变得更清楚。
下面结合附图详细介绍本发明,各附图中类似的参考标记表示类似的元件,其中:
图1是原始半导体结构;
图2是腐蚀后的图1所示半导体结构;
图3A和3B是淀积间隔材料后阵列区和外围区的半导体结构;
图4A和4B是腐蚀间隔材料后的半导体结构;
图5A和5B是形成屏蔽氧化层后的半导体结构;
图6A和6B是掺杂后的半导体结构;
图7A和7B是退火后的半导体结构;
图8A和8B是源-漏延伸后的半导体结构;
图9A和9B是淀积了层间介质层后的半导体结构;
图10是展示本发明的各步骤的流程图。
下面相对于形成局部栅导体叠层介绍图1和2。这些讨论后,各附图将被分成分别展示半导体结构的外围区和阵列区的栅导体叠层;
图1是原始提供的半导体衬底5,衬底5上提供有栅氧化层10。半导体衬底5一般是硅,但可以是任何半导体材料,例如II-VI族半导体、III-V族半导体或如碳化硅等复合硅半导体。半导体衬底5一般包含在形成各上层之前已注入的阱掺杂区。另外,可以采用氮化物或氮氧化物栅绝缘体,而不采用栅氧化层10。
在衬底5和栅氧化层10上,淀积栅叠层。栅叠层可以包括本征(即未掺杂)多晶硅11、硅化钨(WSix)层12和用作氮化物帽盖13的氮化物层13。
在氮化物帽盖13上,设置采用公知的平版印刷掩蔽和腐蚀技术的栅导体(GC)掩模,例如抗蚀材料层(未示出)。可以采用任何公知的光可聚合的抗蚀材料。抗蚀材料例如可通过旋涂或喷涂施加。通过氮化物帽盖13和WSix层12,构图并向下腐蚀栅叠层到多晶硅层11,如图2所示。对多晶硅层的过腐蚀是可以接受的。
如所属领域所公知的,该半导体结构可以包括阵列区和外围区,相对于图3A-9B进行的以下讨论包含外围区和阵列区的不同工艺。由于阵列区的布局要求极高密度,所以,采用最小的沟道长度(最小多晶硅栅导体叠层宽度)和栅导体间的最小间隙。在阵列区中,栅导体间的最小间隙要求扩散接触相对于阵列栅导体(字线)无边界。无边界接触技术最适用于单功函数栅导体(即较好是N+),并且最廉价。
由于外围区的密度要求比阵列区松,所以,不需要无边界接触和具有绝缘帽盖的栅导体。然而,希望用外围区中的双功函数栅导体来改善性能。在以下的讨论中,图3A、4A、5A、6A、7A、8A和9A都表示阵列区结构。图3B、4B、5B、6B、7B、8B和9B都表示外围区结构。
如图3所示,在局部构图的栅叠层上,保形式淀积硼硅玻璃(BSG)层32。BSG 32的厚度选择为完全填充阵列区(图3A)中栅导体(字线)间的窄间隙,同时外围区(图3B)中较宽的间隙具有BSG 32保形层的形貌(图3B)。在例示情况下,对于150nm的最小特征尺寸来说,阵列区中栅导体间的间隙约标称为150nm(图3A)。而外围区中栅导体间的间隙一般为300nm或更大(图3B)。BSG层32的厚度较好介于约80nm和140nm之间。
然后,相对氮化硅,选择性反应离子腐蚀(RIE)所淀积的BSG32,在外围区(图4B)中栅侧壁上形成间隔层30,但在阵列区(图4A)留下用BSG 32填充的间隙。
在外围区,相对氧化物和氮化物,选择性反应离子腐蚀栅叠层中暴露的本征多晶硅层11,腐蚀停止于衬底5上的栅氧化层10上。由于外围区(图5B)的间隔层30和保护BSG 32(即阻挡层)填充阵列区的栅导体间的间隙(图5A),只有外围区栅多晶硅层11被RIE工艺开口。较好是在暴露的硅衬底5上,热生长屏蔽氧化层41,如5B所示。屏蔽层41保护衬底5表面不受由于随后源-漏掺杂剂注入造成的离子注入损伤。另外,屏蔽氧化物还“修复”栅多晶硅反应离子腐蚀期间产生的任何等离子损伤的硅表面。
然后,利用所属领域公知的腐蚀剂(即,湿HF/硫酸),相对于SiN、WSix和热氧化物,选择性各向同性腐蚀BSG 32。由于BSG腐蚀得比热生长氧化层41快得多,屏蔽氧化层41几乎原封不动地留了下来。然后,采用掩蔽离子注入,在阵列区的栅多晶硅层11中(图6A)、在外围区的NFET的栅多晶硅层11(即,在暴露边缘43)中(图6B)、在外围区的NFET的源-漏区51的一部分中,引入N+掺杂剂(例如As或磷)。外围区的PFET接收P型掺杂剂(一般为硼)注入到栅多晶硅层和源-漏区51。N+注入的能量选择为可以忽略穿过阵列区的栅多晶硅层11进入衬底5的掺杂剂的量。
然后,如图7A和7B所示,进行高温退火,在栅多晶硅层11的横向分布掺杂剂。该退火可以有很宽的时间和温度范围,例如1100℃下10秒至850℃下30分钟。由于多晶硅中掺杂剂的扩散系数一般是单晶硅中的扩散系数的100倍,所以,在退火期间,被注入到硅衬底5中的结扩散的程度不大。然后,进行硅反应离子腐蚀,去掉外围区中栅多晶硅边缘43(图7B),并分隔阵列区中的栅多晶硅导体(图7A)。
然后,利用稀释的HF腐蚀,去掉氧化物耳42,并生长栅侧壁氧化物90(图8B)。根据FET的类型,注入阵列扩散(N型)53和外围源-漏延伸层(N和P型)54,如图8B所示。较好可以以5×1013-5×1014cm-2的剂量、5-20KeV的能量、用磷,或以5×1013-5×1014cm-2的剂量、15-50KeV的能量、用砷进行NFET的典型延伸层注入。对PFET,可以5×1013-5×1014cm-2的剂量、5-20KeV的能量、用硼来进行。
然后,如图9A和9B所示,在栅导体侧壁(在无边界接触中需要)上,形成氮化物间隔层92,然后是所属领域的标准处理。淀积层间介质100(一般是CVD氧化物),腐蚀随后将形成接触柱塞的通路。相对于阵列区的栅导体无边界式开出通路(通路开口叠于栅导体之上),同时在外围区栅导体之间形成通路(图9B)。这种不同做法的原因是外围区中低电阻和性能方面要求的金属柱塞94(即钨)使外围区中无边界接触复杂且昂贵。因此,为避免外围区中接触柱塞94与栅短路,在栅导体上不开出通路。所以需要外围区中栅导体间隙更宽。由于阵列区中能够承受较高的串联电阻,所以,采用多晶硅柱塞95,这样便可以较容易地形成无边界接触。这种双功函数/帽盖的栅导体工艺适用于含有深沟槽或层叠电容器存储元件的DRAM。为简单起见,图9A中未示出存储电容器。
图10是展示本发明的各步骤的流程图。具体说,在步骤S100,形成半导体结构,较好是包括含有隔离区和阱掺杂区的半导体衬底5,阱掺杂区上形成有栅氧化层10、本征多晶硅层11、硅化钨层12和氮化物帽盖13。然后,在步骤S102,向下各向异性腐蚀各层到多晶硅层11。然后,在步骤S104,无掩模工艺在阵列区形成阻挡层,在外围区形成间隔层30。然后,在步骤S106,腐蚀暴露的多晶硅层11,在步骤S108,生长屏蔽氧化层41。
然后,在步骤S110,去掉阵列区中的BSG阻挡层和外围区中的间隔层30。在步骤S112,注入源/漏接触区51和多晶硅层11的暴露边缘43。然后,在步骤S114,退火该结构,将掺杂剂分布在整个多晶硅层中,形成掺杂的多晶硅层61。在步骤S116,腐蚀掺杂多晶硅层61的暴露部分。然后,在步骤S118,去掉部分氧化层41和氧化层10。然后,在步骤S120,生长侧壁氧化层90,注入源/漏延伸区54,并注入阵列扩散区53。然后,在步骤S122,形成氮化物间隔层92,并淀积层间介质100。
因而,所得结构形成希望的包括自对准绝缘栅帽盖的双功函数掺杂。即,通过对栅导体进行P+或N+掺杂,同时在栅导体上形成自对准帽盖,本发明满足双功函数的要求。本发明还允许轻掺杂阵列区的源-漏,以便于产生低结漏电,允许在外围区中形成源-漏延伸区,以便于具有高热载流子可靠性,并且不需要引入额外的掩模。
另外,本发明允许在阵列区高密度地形成无边界扩散接触。外围区中的双功函数栅可以形成高性能的表面沟道MOSFET。
尽管结合特定实施例介绍了本发明,但对特定实施例的介绍只是例示性的,不能作为对本发明范围的限制。在不背离本发明精神和范围的情况下,所属领域的技术人员,可以做出各种其它改进和变化。
Claims (11)
1、一种形成双功函数掺杂的方法,该方法包括:
提供半导体衬底、所说半导体衬底上的栅绝缘层、栅绝缘层上的未掺杂多晶硅层、所说未掺杂多晶硅层上的导电硅化物层及绝缘帽盖;
腐蚀部分所说硅化物层和部分所说绝缘帽盖以形成局部栅导体叠层;
在所说绝缘帽盖和所说硅化物层的侧壁上提供包括间隔材料的绝缘间隔层;
腐蚀所说未掺杂多晶硅层的未被间隔材料覆盖的部分;
去掉间隔材料,使所说未掺杂多晶硅层包括用于形成不同导电类型栅导体的第一和第二暴露部分;
用第一导电类型的掺杂剂,掺杂所说多晶硅层的第一暴露部分;
用第二导电类型的掺杂剂,掺杂所说多晶硅层的第二暴露部分;
退火多晶硅层,使所说多晶硅层的其余部分被所说第一和第二导电类型的掺杂剂掺杂。
2、根据权利要求1的方法,其中所说硅化物层是WSix。
3、根据权利要求1的方法,其中所说绝缘间隔层包括硼硅玻璃间隔层。
4、根据权利要求1的方法,还包括在未用所说多晶硅层覆盖的所说半导体衬底部分上形成氧化层。
5、根据权利要求1的方法,在退火所说多晶硅层前,还包括用所说第一导电类型的掺杂剂掺杂部分衬底形成第一导电类型的源和漏接触区,和/或用所说第二导电类型的掺杂剂掺杂另一部分衬底形成第二导电类型的源和漏接触区。
6、根据权利要求5的方法,其中所说半导体衬底包括外围区和阵列区。
7、根据权利要求6的方法,还包括使所说衬底中的源和漏接触区延伸到至少所说退火后多晶硅层之下的区域。
8、根据权利要求6的方法,其中退火所说多晶硅层后,该方法还包括在所说阵列区形成源和漏区。
9、根据权利要求1的方法,其中退火所说多晶硅层后,该方法还包括腐蚀所说多晶硅层的未被所说栅导体叠层覆盖的部分。
10、根据权利要求1的方法,还包括在所说退火后多晶硅层的侧壁上形成栅侧壁氧化物。
11、利用权利要求1的方法得到的栅结构阵列,在半导体衬底上具有不同导电类型的栅导体叠层,所说栅导体叠层包括:
所说半导体衬底上的栅绝缘层、栅绝缘层上的未掺杂的多晶硅层、未掺杂多晶硅层上的导电硅化物层及绝缘帽盖,所说不同导电类型的栅导体叠层是通过用不同类型的掺杂剂对栅导体叠层中的多晶硅层进行选择性掺杂并退火而形成的。
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