CN114207825A - 电子器件用基板及其制造方法 - Google Patents

电子器件用基板及其制造方法 Download PDF

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Publication number
CN114207825A
CN114207825A CN202080055655.2A CN202080055655A CN114207825A CN 114207825 A CN114207825 A CN 114207825A CN 202080055655 A CN202080055655 A CN 202080055655A CN 114207825 A CN114207825 A CN 114207825A
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CN
China
Prior art keywords
substrate
wafer
bonded
bonding
silicon
Prior art date
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Pending
Application number
CN202080055655.2A
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English (en)
Chinese (zh)
Inventor
萩本和德
后藤正三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of CN114207825A publication Critical patent/CN114207825A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H10P14/2908—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
CN202080055655.2A 2019-08-06 2020-07-02 电子器件用基板及其制造方法 Pending CN114207825A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019-144251 2019-08-06
JP2019144251A JP6863423B2 (ja) 2019-08-06 2019-08-06 電子デバイス用基板およびその製造方法
PCT/JP2020/025934 WO2021024654A1 (ja) 2019-08-06 2020-07-02 電子デバイス用基板およびその製造方法

Publications (1)

Publication Number Publication Date
CN114207825A true CN114207825A (zh) 2022-03-18

Family

ID=74502945

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080055655.2A Pending CN114207825A (zh) 2019-08-06 2020-07-02 电子器件用基板及其制造方法

Country Status (5)

Country Link
US (1) US20220367188A1 (https=)
EP (1) EP4012750A4 (https=)
JP (1) JP6863423B2 (https=)
CN (1) CN114207825A (https=)
WO (1) WO2021024654A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7279552B2 (ja) * 2019-07-11 2023-05-23 信越半導体株式会社 電子デバイス用基板およびその製造方法
JP7692638B2 (ja) * 2021-04-16 2025-06-16 テクタス コーポレイション 窒化ガリウム発光ダイオード用のシリコン二重ウェーハ基板
JP7597081B2 (ja) * 2021-12-01 2024-12-10 信越半導体株式会社 電子デバイス用基板及びその製造方法
WO2023100577A1 (ja) 2021-12-01 2023-06-08 信越半導体株式会社 電子デバイス用基板及びその製造方法
JP7616088B2 (ja) * 2022-01-05 2025-01-17 信越半導体株式会社 窒化物半導体基板及びその製造方法
DE102022000425A1 (de) * 2022-02-03 2023-08-03 Azur Space Solar Power Gmbh III-N-Silizium Halbleiterscheibe
DE102022000424A1 (de) * 2022-02-03 2023-08-03 Azur Space Solar Power Gmbh Herstellungsverfahren für eine Halbleiterscheibe mit Silizium und mit einer III-N-Schicht
JP7694523B2 (ja) * 2022-04-13 2025-06-18 信越半導体株式会社 電子デバイス用基板及びその製造方法
US20250273587A1 (en) 2022-04-13 2025-08-28 Shin-Etsu Handotai Co., Ltd. Substrate for electronic device and method for producing the same
JP7563434B2 (ja) * 2022-05-27 2024-10-08 信越半導体株式会社 電子デバイス用基板及びその製造方法
WO2023228868A1 (ja) 2022-05-27 2023-11-30 信越半導体株式会社 電子デバイス用基板及びその製造方法

Citations (6)

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Publication number Priority date Publication date Assignee Title
JP2008140856A (ja) * 2006-11-30 2008-06-19 Sumco Corp エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。
US20090297426A1 (en) * 2008-06-03 2009-12-03 Sumco Corporation Silicon wafer
US20100096668A1 (en) * 2007-11-26 2010-04-22 International Rectifier Corporation High voltage durability III-Nitride semiconductor device
US20120153440A1 (en) * 2009-08-04 2012-06-21 Dowa Electronics Materials Co., Ltd. Epitaxial substrate for electronic device and method of producing the same
US20150084163A1 (en) * 2012-05-11 2015-03-26 Sanken Electric Co., Ltd. Epitaxial substrate, semiconductor device, and method for manufacturing semiconductor device
JP2018041851A (ja) * 2016-09-08 2018-03-15 クアーズテック株式会社 窒化物半導体基板

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JPH0590117A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JPH09246505A (ja) * 1996-03-01 1997-09-19 Hitachi Ltd 半導体集積回路装置
US7902039B2 (en) * 2006-11-30 2011-03-08 Sumco Corporation Method for manufacturing silicon wafer
JP5636183B2 (ja) * 2009-11-11 2014-12-03 コバレントマテリアル株式会社 化合物半導体基板
JP2014192226A (ja) 2013-03-26 2014-10-06 Sharp Corp 電子デバイス用エピタキシャル基板
JP2014236093A (ja) * 2013-05-31 2014-12-15 サンケン電気株式会社 シリコン系基板、半導体装置、及び、半導体装置の製造方法
CN103681992A (zh) * 2014-01-07 2014-03-26 苏州晶湛半导体有限公司 半导体衬底、半导体器件及半导体衬底制造方法
US10943813B2 (en) * 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
JP7279552B2 (ja) * 2019-07-11 2023-05-23 信越半導体株式会社 電子デバイス用基板およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140856A (ja) * 2006-11-30 2008-06-19 Sumco Corp エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。
US20100096668A1 (en) * 2007-11-26 2010-04-22 International Rectifier Corporation High voltage durability III-Nitride semiconductor device
US20090297426A1 (en) * 2008-06-03 2009-12-03 Sumco Corporation Silicon wafer
US20120153440A1 (en) * 2009-08-04 2012-06-21 Dowa Electronics Materials Co., Ltd. Epitaxial substrate for electronic device and method of producing the same
US20150084163A1 (en) * 2012-05-11 2015-03-26 Sanken Electric Co., Ltd. Epitaxial substrate, semiconductor device, and method for manufacturing semiconductor device
JP2018041851A (ja) * 2016-09-08 2018-03-15 クアーズテック株式会社 窒化物半導体基板

Also Published As

Publication number Publication date
JP6863423B2 (ja) 2021-04-21
WO2021024654A1 (ja) 2021-02-11
EP4012750A4 (en) 2023-10-18
JP2021027186A (ja) 2021-02-22
EP4012750A1 (en) 2022-06-15
US20220367188A1 (en) 2022-11-17

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